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drm/malidp: Enable MMU prefetch on Mali-DP650
Mali-DP650 supports warming up the SMMU translations, by sending requsts to the SMMU before a buffer is read. There are two modes supported: - PARTIAL: could be enabled when the buffer is composed of 4K or 64K pages, the display hardware will send a configurable number of requests before the actual reading. - FULL: could be enabled when the buffer is composed of 1M or 2M pages, the display hardware will send requests before reading for all pages composing the buffer. This patch adds a mechanism for detecting the page size and set the MMU prefetch mode if possible. Changes since v1: - For imported buffers use the already populated drm_gem_cma_object.sgt instead of calling driver.gem_prime_get_sg_table, which works just for buffers allocated through the gem_cma API. Signed-off-by: Jamie Fox <jamie.fox@arm.com> Signed-off-by: Alexandru Gheorghe <alexandru-cosmin.gheorghe@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> [rebased and re-ordered functions] Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
This commit is contained in:
parent
187f7f21b2
commit
1f23a56a46
5 changed files with 296 additions and 9 deletions
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@ -55,6 +55,12 @@ struct malidp_plane {
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const struct malidp_layer *layer;
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};
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enum mmu_prefetch_mode {
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MALIDP_PREFETCH_MODE_NONE,
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MALIDP_PREFETCH_MODE_PARTIAL,
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MALIDP_PREFETCH_MODE_FULL,
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};
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struct malidp_plane_state {
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struct drm_plane_state base;
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@ -63,6 +69,8 @@ struct malidp_plane_state {
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/* internal format ID */
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u8 format;
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u8 n_planes;
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enum mmu_prefetch_mode mmu_prefetch_mode;
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u32 mmu_prefetch_pgsize;
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};
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#define to_malidp_plane(x) container_of(x, struct malidp_plane, base)
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@ -84,16 +84,45 @@ static const struct malidp_format_id malidp550_de_formats[] = {
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};
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static const struct malidp_layer malidp500_layers[] = {
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{ DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE, MALIDP_DE_LV_STRIDE0, MALIDP500_LV_YUV2RGB },
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{ DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE, MALIDP_DE_LG_STRIDE, 0 },
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{ DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE, MALIDP_DE_LG_STRIDE, 0 },
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/* id, base address, fb pointer address base, stride offset,
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* yuv2rgb matrix offset, mmu control register offset
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*/
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{ DE_VIDEO1, MALIDP500_DE_LV_BASE, MALIDP500_DE_LV_PTR_BASE,
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MALIDP_DE_LV_STRIDE0, MALIDP500_LV_YUV2RGB, 0 },
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{ DE_GRAPHICS1, MALIDP500_DE_LG1_BASE, MALIDP500_DE_LG1_PTR_BASE,
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MALIDP_DE_LG_STRIDE, 0, 0 },
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{ DE_GRAPHICS2, MALIDP500_DE_LG2_BASE, MALIDP500_DE_LG2_PTR_BASE,
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MALIDP_DE_LG_STRIDE, 0, 0 },
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};
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static const struct malidp_layer malidp550_layers[] = {
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{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE, MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB },
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{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE, MALIDP_DE_LG_STRIDE, 0 },
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{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE, MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB },
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{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE, MALIDP550_DE_LS_R1_STRIDE, 0 },
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/* id, base address, fb pointer address base, stride offset,
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* yuv2rgb matrix offset, mmu control register offset
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*/
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{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE,
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MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB, 0 },
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{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE,
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MALIDP_DE_LG_STRIDE, 0, 0 },
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{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE,
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MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB, 0 },
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{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE,
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MALIDP550_DE_LS_R1_STRIDE, 0, 0 },
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};
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static const struct malidp_layer malidp650_layers[] = {
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/* id, base address, fb pointer address base, stride offset,
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* yuv2rgb matrix offset, mmu control register offset
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*/
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{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE,
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MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB,
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MALIDP650_DE_LV_MMU_CTRL },
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{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE,
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MALIDP_DE_LG_STRIDE, 0, MALIDP650_DE_LG_MMU_CTRL },
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{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE,
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MALIDP_DE_LV_STRIDE0, MALIDP550_LV_YUV2RGB,
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MALIDP650_DE_LV_MMU_CTRL },
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{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE,
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MALIDP550_DE_LS_R1_STRIDE, 0, MALIDP650_DE_LS_MMU_CTRL },
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};
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#define SE_N_SCALING_COEFFS 96
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@ -853,8 +882,8 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = {
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.dc_base = MALIDP550_DC_BASE,
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.out_depth_base = MALIDP550_DE_OUTPUT_DEPTH,
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.features = MALIDP_REGMAP_HAS_CLEARIRQ,
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.n_layers = ARRAY_SIZE(malidp550_layers),
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.layers = malidp550_layers,
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.n_layers = ARRAY_SIZE(malidp650_layers),
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.layers = malidp650_layers,
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.de_irq_map = {
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.irq_mask = MALIDP_DE_IRQ_UNDERRUN |
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MALIDP650_DE_IRQ_DRIFT |
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@ -62,6 +62,7 @@ struct malidp_layer {
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u16 ptr; /* address offset for the pointer register */
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u16 stride_offset; /* offset to the first stride register. */
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s16 yuv2rgb_offset; /* offset to the YUV->RGB matrix entries */
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u16 mmu_ctrl_offset; /* offset to the MMU control register */
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};
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enum malidp_scaling_coeff_set {
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@ -10,11 +10,14 @@
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* ARM Mali DP plane manipulation routines.
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*/
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#include <linux/iommu.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_gem_framebuffer_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drm_print.h>
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@ -57,6 +60,13 @@
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*/
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#define MALIDP_ALPHA_LUT 0xffaa5500
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/* page sizes the MMU prefetcher can support */
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#define MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES (SZ_4K | SZ_64K)
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#define MALIDP_MMU_PREFETCH_FULL_PGSIZES (SZ_1M | SZ_2M)
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/* readahead for partial-frame prefetch */
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#define MALIDP_MMU_PREFETCH_READAHEAD 8
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static void malidp_de_plane_destroy(struct drm_plane *plane)
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{
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struct malidp_plane *mp = to_malidp_plane(plane);
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@ -101,6 +111,9 @@ drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane)
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state->format = m_state->format;
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state->n_planes = m_state->n_planes;
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state->mmu_prefetch_mode = m_state->mmu_prefetch_mode;
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state->mmu_prefetch_pgsize = m_state->mmu_prefetch_pgsize;
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return &state->base;
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}
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@ -113,6 +126,12 @@ static void malidp_destroy_plane_state(struct drm_plane *plane,
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kfree(m_state);
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}
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static const char * const prefetch_mode_names[] = {
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[MALIDP_PREFETCH_MODE_NONE] = "MMU_PREFETCH_NONE",
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[MALIDP_PREFETCH_MODE_PARTIAL] = "MMU_PREFETCH_PARTIAL",
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[MALIDP_PREFETCH_MODE_FULL] = "MMU_PREFETCH_FULL",
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};
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static void malidp_plane_atomic_print_state(struct drm_printer *p,
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const struct drm_plane_state *state)
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{
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@ -121,6 +140,9 @@ static void malidp_plane_atomic_print_state(struct drm_printer *p,
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drm_printf(p, "\trotmem_size=%u\n", ms->rotmem_size);
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drm_printf(p, "\tformat_id=%u\n", ms->format);
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drm_printf(p, "\tn_planes=%u\n", ms->n_planes);
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drm_printf(p, "\tmmu_prefetch_mode=%s\n",
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prefetch_mode_names[ms->mmu_prefetch_mode]);
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drm_printf(p, "\tmmu_prefetch_pgsize=%d\n", ms->mmu_prefetch_pgsize);
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}
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static const struct drm_plane_funcs malidp_de_plane_funcs = {
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@ -174,6 +196,199 @@ static int malidp_se_check_scaling(struct malidp_plane *mp,
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return 0;
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}
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static u32 malidp_get_pgsize_bitmap(struct malidp_plane *mp)
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{
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u32 pgsize_bitmap = 0;
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if (iommu_present(&platform_bus_type)) {
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struct iommu_domain *mmu_dom =
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iommu_get_domain_for_dev(mp->base.dev->dev);
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if (mmu_dom)
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pgsize_bitmap = mmu_dom->pgsize_bitmap;
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}
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return pgsize_bitmap;
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}
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/*
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* Check if the framebuffer is entirely made up of pages at least pgsize in
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* size. Only a heuristic: assumes that each scatterlist entry has been aligned
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* to the largest page size smaller than its length and that the MMU maps to
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* the largest page size possible.
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*/
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static bool malidp_check_pages_threshold(struct malidp_plane_state *ms,
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u32 pgsize)
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{
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int i;
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for (i = 0; i < ms->n_planes; i++) {
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struct drm_gem_object *obj;
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struct drm_gem_cma_object *cma_obj;
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struct sg_table *sgt;
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struct scatterlist *sgl;
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obj = drm_gem_fb_get_obj(ms->base.fb, i);
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cma_obj = to_drm_gem_cma_obj(obj);
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if (cma_obj->sgt)
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sgt = cma_obj->sgt;
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else
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sgt = obj->dev->driver->gem_prime_get_sg_table(obj);
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if (!sgt)
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return false;
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sgl = sgt->sgl;
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while (sgl) {
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if (sgl->length < pgsize) {
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if (!cma_obj->sgt)
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kfree(sgt);
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return false;
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}
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sgl = sg_next(sgl);
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}
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if (!cma_obj->sgt)
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kfree(sgt);
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}
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return true;
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}
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/*
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* Check if it is possible to enable partial-frame MMU prefetch given the
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* current format, AFBC state and rotation.
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*/
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static bool malidp_partial_prefetch_supported(u32 format, u64 modifier,
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unsigned int rotation)
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{
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bool afbc, sparse;
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/* rotation and horizontal flip not supported for partial prefetch */
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if (rotation & (DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 |
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DRM_MODE_ROTATE_270 | DRM_MODE_REFLECT_X))
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return false;
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afbc = modifier & DRM_FORMAT_MOD_ARM_AFBC(0);
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sparse = modifier & AFBC_FORMAT_MOD_SPARSE;
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switch (format) {
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case DRM_FORMAT_ARGB2101010:
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case DRM_FORMAT_RGBA1010102:
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case DRM_FORMAT_BGRA1010102:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_RGBA8888:
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case DRM_FORMAT_BGRA8888:
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case DRM_FORMAT_XRGB8888:
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case DRM_FORMAT_XBGR8888:
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case DRM_FORMAT_RGBX8888:
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case DRM_FORMAT_BGRX8888:
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case DRM_FORMAT_RGB888:
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case DRM_FORMAT_RGBA5551:
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case DRM_FORMAT_RGB565:
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/* always supported */
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return true;
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case DRM_FORMAT_ABGR2101010:
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case DRM_FORMAT_ABGR8888:
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case DRM_FORMAT_ABGR1555:
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case DRM_FORMAT_BGR565:
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/* supported, but if AFBC then must be sparse mode */
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return (!afbc) || (afbc && sparse);
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case DRM_FORMAT_BGR888:
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/* supported, but not for AFBC */
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return !afbc;
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case DRM_FORMAT_YUYV:
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case DRM_FORMAT_UYVY:
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case DRM_FORMAT_NV12:
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case DRM_FORMAT_YUV420:
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/* not supported */
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return false;
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default:
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return false;
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}
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}
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/*
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* Select the preferred MMU prefetch mode. Full-frame prefetch is preferred as
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* long as the framebuffer is all large pages. Otherwise partial-frame prefetch
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* is selected as long as it is supported for the current format. The selected
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* page size for prefetch is returned in pgsize_bitmap.
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*/
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static enum mmu_prefetch_mode malidp_mmu_prefetch_select_mode
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(struct malidp_plane_state *ms, u32 *pgsize_bitmap)
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{
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u32 pgsizes;
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/* get the full-frame prefetch page size(s) supported by the MMU */
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pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_FULL_PGSIZES;
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while (pgsizes) {
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u32 largest_pgsize = 1 << __fls(pgsizes);
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if (malidp_check_pages_threshold(ms, largest_pgsize)) {
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*pgsize_bitmap = largest_pgsize;
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return MALIDP_PREFETCH_MODE_FULL;
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}
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pgsizes -= largest_pgsize;
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}
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/* get the partial-frame prefetch page size(s) supported by the MMU */
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pgsizes = *pgsize_bitmap & MALIDP_MMU_PREFETCH_PARTIAL_PGSIZES;
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if (malidp_partial_prefetch_supported(ms->base.fb->format->format,
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ms->base.fb->modifier,
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ms->base.rotation)) {
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/* partial prefetch using the smallest page size */
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*pgsize_bitmap = 1 << __ffs(pgsizes);
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return MALIDP_PREFETCH_MODE_PARTIAL;
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}
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*pgsize_bitmap = 0;
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return MALIDP_PREFETCH_MODE_NONE;
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}
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static u32 malidp_calc_mmu_control_value(enum mmu_prefetch_mode mode,
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u8 readahead, u8 n_planes, u32 pgsize)
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{
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u32 mmu_ctrl = 0;
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if (mode != MALIDP_PREFETCH_MODE_NONE) {
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mmu_ctrl |= MALIDP_MMU_CTRL_EN;
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if (mode == MALIDP_PREFETCH_MODE_PARTIAL) {
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mmu_ctrl |= MALIDP_MMU_CTRL_MODE;
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mmu_ctrl |= MALIDP_MMU_CTRL_PP_NUM_REQ(readahead);
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}
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if (pgsize == SZ_64K || pgsize == SZ_2M) {
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int i;
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for (i = 0; i < n_planes; i++)
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mmu_ctrl |= MALIDP_MMU_CTRL_PX_PS(i);
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}
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}
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return mmu_ctrl;
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}
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static void malidp_de_prefetch_settings(struct malidp_plane *mp,
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struct malidp_plane_state *ms)
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{
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if (!mp->layer->mmu_ctrl_offset)
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return;
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/* get the page sizes supported by the MMU */
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ms->mmu_prefetch_pgsize = malidp_get_pgsize_bitmap(mp);
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ms->mmu_prefetch_mode =
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malidp_mmu_prefetch_select_mode(ms, &ms->mmu_prefetch_pgsize);
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}
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static int malidp_de_plane_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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@ -250,6 +465,8 @@ static int malidp_de_plane_check(struct drm_plane *plane,
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fb->format->has_alpha)
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return -EINVAL;
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malidp_de_prefetch_settings(mp, ms);
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return 0;
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}
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@ -326,6 +543,24 @@ static void malidp_de_set_color_encoding(struct malidp_plane *plane,
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}
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}
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static void malidp_de_set_mmu_control(struct malidp_plane *mp,
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struct malidp_plane_state *ms)
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{
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u32 mmu_ctrl;
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/* check hardware supports MMU prefetch */
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if (!mp->layer->mmu_ctrl_offset)
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return;
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mmu_ctrl = malidp_calc_mmu_control_value(ms->mmu_prefetch_mode,
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MALIDP_MMU_PREFETCH_READAHEAD,
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ms->n_planes,
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ms->mmu_prefetch_pgsize);
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malidp_hw_write(mp->hwdev, mmu_ctrl,
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mp->layer->base + mp->layer->mmu_ctrl_offset);
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}
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static void malidp_de_plane_update(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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|
@ -358,6 +593,9 @@ static void malidp_de_plane_update(struct drm_plane *plane,
|
|||
malidp_hw_write(mp->hwdev, lower_32_bits(fb_addr), ptr);
|
||||
malidp_hw_write(mp->hwdev, upper_32_bits(fb_addr), ptr + 4);
|
||||
}
|
||||
|
||||
malidp_de_set_mmu_control(mp, ms);
|
||||
|
||||
malidp_de_set_plane_pitches(mp, ms->n_planes,
|
||||
state->fb->pitches);
|
||||
|
||||
|
|
|
@ -247,6 +247,17 @@
|
|||
#define MALIDP550_CONFIG_VALID 0x0c014
|
||||
#define MALIDP550_CONFIG_ID 0x0ffd4
|
||||
|
||||
/* register offsets specific to DP650 */
|
||||
#define MALIDP650_DE_LV_MMU_CTRL 0x000D0
|
||||
#define MALIDP650_DE_LG_MMU_CTRL 0x00048
|
||||
#define MALIDP650_DE_LS_MMU_CTRL 0x00078
|
||||
|
||||
/* bit masks to set the MMU control register */
|
||||
#define MALIDP_MMU_CTRL_EN (1 << 0)
|
||||
#define MALIDP_MMU_CTRL_MODE (1 << 4)
|
||||
#define MALIDP_MMU_CTRL_PX_PS(x) (1 << (8 + (x)))
|
||||
#define MALIDP_MMU_CTRL_PP_NUM_REQ(x) (((x) & 0x7f) << 12)
|
||||
|
||||
/*
|
||||
* Starting with DP550 the register map blocks has been standardised to the
|
||||
* following layout:
|
||||
|
|
Loading…
Reference in a new issue