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clk: mediatek: Add MT8186 mcusys clock support
Add MT8186 mcusys clock controller which provides muxes to select the clock source of APMCU. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220409132251.31725-3-chun-jie.chen@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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3 changed files with 117 additions and 0 deletions
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@ -512,6 +512,14 @@ config COMMON_CLK_MT8183_VENCSYS
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help
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This driver supports MediaTek MT8183 vencsys clocks.
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config COMMON_CLK_MT8186
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bool "Clock driver for MediaTek MT8186"
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depends on ARM64 || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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default ARCH_MEDIATEK
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help
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This driver supports MediaTek MT8186 clocks.
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config COMMON_CLK_MT8192
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bool "Clock driver for MediaTek MT8192"
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depends on ARM64 || COMPILE_TEST
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@ -71,6 +71,7 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o
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obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
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obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
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obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o
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obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
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obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
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obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
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108
drivers/clk/mediatek/clk-mt8186-mcu.c
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108
drivers/clk/mediatek/clk-mt8186-mcu.c
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@ -0,0 +1,108 @@
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// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2022 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/mt8186-clk.h>
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#include "clk-mtk.h"
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static const char * const mcu_armpll_ll_parents[] = {
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"clk26m",
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"armpll_ll",
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"mainpll",
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"univpll_d2"
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};
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static const char * const mcu_armpll_bl_parents[] = {
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"clk26m",
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"armpll_bl",
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"mainpll",
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"univpll_d2"
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};
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static const char * const mcu_armpll_bus_parents[] = {
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"clk26m",
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"ccipll",
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"mainpll",
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"univpll_d2"
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};
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/*
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* We only configure the CPU muxes when adjust CPU frequency in MediaTek CPUFreq Driver.
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* Other fields like divider always keep the same value. (set once in bootloader)
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*/
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static struct mtk_composite mcu_muxes[] = {
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/* CPU_PLLDIV_CFG0 */
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MUX(CLK_MCU_ARMPLL_LL_SEL, "mcu_armpll_ll_sel", mcu_armpll_ll_parents, 0x2A0, 9, 2),
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/* CPU_PLLDIV_CFG1 */
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MUX(CLK_MCU_ARMPLL_BL_SEL, "mcu_armpll_bl_sel", mcu_armpll_bl_parents, 0x2A4, 9, 2),
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/* BUS_PLLDIV_CFG */
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MUX(CLK_MCU_ARMPLL_BUS_SEL, "mcu_armpll_bus_sel", mcu_armpll_bus_parents, 0x2E0, 9, 2),
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};
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static const struct of_device_id of_match_clk_mt8186_mcu[] = {
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{ .compatible = "mediatek,mt8186-mcusys", },
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{}
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};
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static int clk_mt8186_mcu_probe(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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int r;
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void __iomem *base;
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clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base)) {
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r = PTR_ERR(base);
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goto free_mcu_data;
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}
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r = mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
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NULL, clk_data);
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if (r)
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goto free_mcu_data;
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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goto unregister_composite_muxes;
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platform_set_drvdata(pdev, clk_data);
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return r;
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unregister_composite_muxes:
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mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), clk_data);
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free_mcu_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static int clk_mt8186_mcu_remove(struct platform_device *pdev)
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{
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struct clk_onecell_data *clk_data = platform_get_drvdata(pdev);
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struct device_node *node = pdev->dev.of_node;
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of_clk_del_provider(node);
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mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), clk_data);
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mtk_free_clk_data(clk_data);
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return 0;
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}
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static struct platform_driver clk_mt8186_mcu_drv = {
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.probe = clk_mt8186_mcu_probe,
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.remove = clk_mt8186_mcu_remove,
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.driver = {
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.name = "clk-mt8186-mcu",
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.of_match_table = of_match_clk_mt8186_mcu,
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},
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};
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builtin_platform_driver(clk_mt8186_mcu_drv);
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