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arm64: __clean_dcache_area_poc to take end parameter instead of size

Browse source 
To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.

Because the code is shared with __dma_clean_area, it changes the
parameters for that as well. However, __dma_clean_area is local to
cache.S, so no other users are affected.

No functional change intended.

Reported-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-14-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Fuad Tabba 2021-05-24 09:29:56 +01:00 committed by Will Deacon
parent 814b186079
commit 1f42faf1d2
3 changed files with 11 additions and 12 deletions
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2
arch/arm64/include/asm/cacheflush.h
View file

@ -60,7 +60,7 @@ extern void __flush_icache_range(unsigned long start, unsigned long end);
extern void invalidate_icache_range(unsigned long start, unsigned long end);
extern void __flush_dcache_area(unsigned long start, unsigned long end);
extern void __inval_dcache_area(unsigned long start, unsigned long end);
extern void __clean_dcache_area_poc(void *addr, size_t len);
extern void __clean_dcache_area_poc(unsigned long start, unsigned long end);
extern void __clean_dcache_area_pop(void *addr, size_t len);
extern void __clean_dcache_area_pou(void *addr, size_t len);
extern long __flush_cache_user_range(unsigned long start, unsigned long end);

5
arch/arm64/kernel/efi-entry.S
View file

@ -28,6 +28,7 @@ SYM_CODE_START(efi_enter_kernel)
* stale icache entries from before relocation.
*/
ldr w1, =kernel_size
add x1, x0, x1
bl __clean_dcache_area_poc
ic ialluis
@ -36,7 +37,7 @@ SYM_CODE_START(efi_enter_kernel)
* so that we can safely disable the MMU and caches.
*/
adr x0, 0f
ldr w1, 3f
adr x1, 3f
bl __clean_dcache_area_poc
0:
/* Turn off Dcache and MMU */
@ -64,5 +65,5 @@ SYM_CODE_START(efi_enter_kernel)
mov x2, xzr
mov x3, xzr
br x19
3:
SYM_CODE_END(efi_enter_kernel)
3: .long . - 0b

16
arch/arm64/mm/cache.S
View file

@ -171,24 +171,23 @@ SYM_FUNC_END_PI(__inval_dcache_area)
SYM_FUNC_END(__dma_inv_area)
/*
* __clean_dcache_area_poc(kaddr, size)
* __clean_dcache_area_poc(start, end)
*
* Ensure that any D-cache lines for the interval [kaddr, kaddr+size)
* Ensure that any D-cache lines for the interval [start, end)
* are cleaned to the PoC.
*
* - kaddr - kernel address
* - size - size in question
* - start - virtual start address of region
* - end - virtual end address of region
*/
SYM_FUNC_START_LOCAL(__dma_clean_area)
SYM_FUNC_START_PI(__clean_dcache_area_poc)
/* FALLTHROUGH */
/*
* __dma_clean_area(start, size)
* __dma_clean_area(start, end)
* - start - virtual start address of region
* - size - size in question
* - end - virtual end address of region
*/
add x1, x0, x1
dcache_by_line_op cvac, sy, x0, x1, x2, x3
ret
SYM_FUNC_END_PI(__clean_dcache_area_poc)
@ -204,10 +203,10 @@ SYM_FUNC_END(__dma_clean_area)
* - size - size in question
*/
SYM_FUNC_START_PI(__clean_dcache_area_pop)
add x1, x0, x1
alternative_if_not ARM64_HAS_DCPOP
b __clean_dcache_area_poc
alternative_else_nop_endif
add x1, x0, x1
dcache_by_line_op cvap, sy, x0, x1, x2, x3
ret
SYM_FUNC_END_PI(__clean_dcache_area_pop)
@ -236,7 +235,6 @@ SYM_FUNC_START_PI(__dma_map_area)
add x1, x0, x1
cmp w2, #DMA_FROM_DEVICE
b.eq __dma_inv_area
sub x1, x1, x0
b __dma_clean_area
SYM_FUNC_END_PI(__dma_map_area)