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mmc: dw_mmc: set the supported max/min frequency
Both f_max and f_min will be informed for core layer to request valid clock rate. But current setting from 'host->bus_hz' may not represent the max/min frequency properly. Even if host can actually support high speed than bus_hz, core layer will not request clock rate over bus_hz. Basically, f_max/f_min can be set with the values according to spec. And then host will make its best effort to meet the rate. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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2 changed files with 16 additions and 2 deletions
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@ -52,6 +52,9 @@ Optional properties:
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is specified and the ciu clock is specified then we'll try to set the ciu
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is specified and the ciu clock is specified then we'll try to set the ciu
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clock to this at probe time.
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clock to this at probe time.
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* clock-freq-min-max: Minimum and Maximum clock frequency for card output
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clock(cclk_out). If it's not specified, max is 200MHZ and min is 400KHz by default.
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* num-slots: specifies the number of slots supported by the controller.
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* num-slots: specifies the number of slots supported by the controller.
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The number of physical slots actually used could be equal or less than the
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The number of physical slots actually used could be equal or less than the
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value specified by num-slots. If this property is not specified, the value
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value specified by num-slots. If this property is not specified, the value
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@ -97,6 +100,7 @@ board specific portions as listed below.
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dwmmc0@12200000 {
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dwmmc0@12200000 {
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clock-frequency = <400000000>;
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clock-frequency = <400000000>;
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clock-freq-min-max = <400000 200000000>;
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num-slots = <1>;
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num-slots = <1>;
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supports-highspeed;
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supports-highspeed;
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caps2-mmc-hs200-1_8v;
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caps2-mmc-hs200-1_8v;
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@ -50,6 +50,9 @@
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#define DW_MCI_RECV_STATUS 2
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#define DW_MCI_RECV_STATUS 2
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#define DW_MCI_DMA_THRESHOLD 16
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#define DW_MCI_DMA_THRESHOLD 16
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#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
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#define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
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#ifdef CONFIG_MMC_DW_IDMAC
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#ifdef CONFIG_MMC_DW_IDMAC
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#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
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#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
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SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
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SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
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@ -1936,6 +1939,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
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struct dw_mci_slot *slot;
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struct dw_mci_slot *slot;
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const struct dw_mci_drv_data *drv_data = host->drv_data;
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const struct dw_mci_drv_data *drv_data = host->drv_data;
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int ctrl_id, ret;
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int ctrl_id, ret;
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u32 freq[2];
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u8 bus_width;
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u8 bus_width;
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mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
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mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
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@ -1951,8 +1955,14 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
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slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
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slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
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mmc->ops = &dw_mci_ops;
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mmc->ops = &dw_mci_ops;
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mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
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if (of_property_read_u32_array(host->dev->of_node,
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mmc->f_max = host->bus_hz;
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"clock-freq-min-max", freq, 2)) {
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mmc->f_min = DW_MCI_FREQ_MIN;
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mmc->f_max = DW_MCI_FREQ_MAX;
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} else {
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mmc->f_min = freq[0];
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mmc->f_max = freq[1];
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}
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if (host->pdata->get_ocr)
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if (host->pdata->get_ocr)
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mmc->ocr_avail = host->pdata->get_ocr(id);
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mmc->ocr_avail = host->pdata->get_ocr(id);
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