mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-29 23:53:32 +00:00
Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: [SPARC64]: Avoid JBUS errors on some Niagara systems. [FUSION]: Fix mptspi.c build with CONFIG_PM not set. [TG3]: Handle Sun onboard tg3 chips more correctly. [SPARC64]: Dump local cpu registers in sun4v_log_error()
This commit is contained in:
Linus Torvalds
commit
1f4d4a7e8f
5 changed files with 177 additions and 107 deletions
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@ -599,18 +599,128 @@ struct pci_iommu_ops pci_sun4v_iommu_ops = {
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/* SUN4V PCI configuration space accessors. */
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static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func)
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struct pdev_entry {
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struct pdev_entry *next;
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u32 devhandle;
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unsigned int bus;
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unsigned int device;
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unsigned int func;
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};
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#define PDEV_HTAB_SIZE 16
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#define PDEV_HTAB_MASK (PDEV_HTAB_SIZE - 1)
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static struct pdev_entry *pdev_htab[PDEV_HTAB_SIZE];
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static inline unsigned int pdev_hashfn(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
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{
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if (bus == pbm->pci_first_busno) {
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if (device == 0 && func == 0)
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return 0;
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return 1;
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unsigned int val;
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val = (devhandle ^ (devhandle >> 4));
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val ^= bus;
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val ^= device;
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val ^= func;
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return val & PDEV_HTAB_MASK;
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}
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static int pdev_htab_add(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
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{
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struct pdev_entry *p = kmalloc(sizeof(*p), GFP_KERNEL);
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struct pdev_entry **slot;
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if (!p)
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return -ENOMEM;
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slot = &pdev_htab[pdev_hashfn(devhandle, bus, device, func)];
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p->next = *slot;
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*slot = p;
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p->devhandle = devhandle;
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p->bus = bus;
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p->device = device;
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p->func = func;
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return 0;
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}
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/* Recursively descend into the OBP device tree, rooted at toplevel_node,
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* looking for a PCI device matching bus and devfn.
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*/
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static int obp_find(struct linux_prom_pci_registers *pregs, int toplevel_node, unsigned int bus, unsigned int devfn)
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{
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toplevel_node = prom_getchild(toplevel_node);
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while (toplevel_node != 0) {
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int ret = obp_find(pregs, toplevel_node, bus, devfn);
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if (ret != 0)
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return ret;
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ret = prom_getproperty(toplevel_node, "reg", (char *) pregs,
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sizeof(*pregs) * PROMREG_MAX);
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if (ret == 0 || ret == -1)
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goto next_sibling;
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if (((pregs[0].phys_hi >> 16) & 0xff) == bus &&
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((pregs[0].phys_hi >> 8) & 0xff) == devfn)
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break;
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next_sibling:
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toplevel_node = prom_getsibling(toplevel_node);
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}
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return toplevel_node;
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}
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static int pdev_htab_populate(struct pci_pbm_info *pbm)
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{
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struct linux_prom_pci_registers pr[PROMREG_MAX];
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u32 devhandle = pbm->devhandle;
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unsigned int bus;
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for (bus = pbm->pci_first_busno; bus <= pbm->pci_last_busno; bus++) {
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unsigned int devfn;
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for (devfn = 0; devfn < 256; devfn++) {
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unsigned int device = PCI_SLOT(devfn);
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unsigned int func = PCI_FUNC(devfn);
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if (obp_find(pr, pbm->prom_node, bus, devfn)) {
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int err = pdev_htab_add(devhandle, bus,
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device, func);
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if (err)
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return err;
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}
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}
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}
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return 0;
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}
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static struct pdev_entry *pdev_find(u32 devhandle, unsigned int bus, unsigned int device, unsigned int func)
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{
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struct pdev_entry *p;
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p = pdev_htab[pdev_hashfn(devhandle, bus, device, func)];
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while (p) {
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if (p->devhandle == devhandle &&
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p->bus == bus &&
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p->device == device &&
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p->func == func)
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break;
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p = p->next;
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}
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return p;
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}
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static inline int pci_sun4v_out_of_range(struct pci_pbm_info *pbm, unsigned int bus, unsigned int device, unsigned int func)
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{
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if (bus < pbm->pci_first_busno ||
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bus > pbm->pci_last_busno)
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return 1;
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return 0;
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return pdev_find(pbm->devhandle, bus, device, func) == NULL;
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}
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static int pci_sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
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@ -1063,6 +1173,8 @@ static void pci_sun4v_pbm_init(struct pci_controller_info *p, int prom_node, u32
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pci_sun4v_get_bus_range(pbm);
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pci_sun4v_iommu_init(pbm);
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pdev_htab_populate(pbm);
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}
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void sun4v_pci_init(int node, char *model_name)
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@ -1797,7 +1797,9 @@ static const char *sun4v_err_type_to_str(u32 type)
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};
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}
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static void sun4v_log_error(struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)
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extern void __show_regs(struct pt_regs * regs);
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static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)
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{
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int cnt;
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@ -1830,6 +1832,8 @@ static void sun4v_log_error(struct sun4v_error_entry *ent, int cpu, const char *
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pfx,
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ent->err_raddr, ent->err_size, ent->err_cpu);
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__show_regs(regs);
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if ((cnt = atomic_read(ocnt)) != 0) {
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atomic_set(ocnt, 0);
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wmb();
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@ -1862,7 +1866,7 @@ void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
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put_cpu();
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sun4v_log_error(&local_copy, cpu,
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sun4v_log_error(regs, &local_copy, cpu,
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KERN_ERR "RESUMABLE ERROR",
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&sun4v_resum_oflow_cnt);
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}
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@ -1910,7 +1914,7 @@ void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
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}
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#endif
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sun4v_log_error(&local_copy, cpu,
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sun4v_log_error(regs, &local_copy, cpu,
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KERN_EMERG "NON-RESUMABLE ERROR",
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&sun4v_nonresum_oflow_cnt);
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@ -2200,7 +2204,6 @@ static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
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void die_if_kernel(char *str, struct pt_regs *regs)
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{
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static int die_counter;
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extern void __show_regs(struct pt_regs * regs);
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extern void smp_report_regs(void);
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int count = 0;
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@ -831,6 +831,7 @@ mptspi_ioc_reset(MPT_ADAPTER *ioc, int reset_phase)
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return rc;
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}
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#ifdef CONFIG_PM
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/*
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* spi module resume handler
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*/
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@ -846,6 +847,7 @@ mptspi_resume(struct pci_dev *pdev)
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return rc;
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}
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#endif
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/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
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/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
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@ -69,8 +69,8 @@
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#define DRV_MODULE_NAME "tg3"
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "3.58"
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#define DRV_MODULE_RELDATE "May 22, 2006"
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#define DRV_MODULE_VERSION "3.59"
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#define DRV_MODULE_RELDATE "June 8, 2006"
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_RX_MODE 0
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@ -4485,7 +4485,6 @@ static void tg3_disable_nvram_access(struct tg3 *tp)
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/* tp->lock is held. */
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static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
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{
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if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
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tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
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NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
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@ -4568,13 +4567,12 @@ static int tg3_chip_reset(struct tg3 *tp)
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void (*write_op)(struct tg3 *, u32, u32);
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int i;
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if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
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tg3_nvram_lock(tp);
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/* No matching tg3_nvram_unlock() after this because
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* chip reset below will undo the nvram lock.
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*/
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tp->nvram_lock_cnt = 0;
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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@ -4727,7 +4725,6 @@ static int tg3_chip_reset(struct tg3 *tp)
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tw32_f(MAC_MODE, 0);
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udelay(40);
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if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
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/* Wait for firmware initialization to complete. */
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for (i = 0; i < 100000; i++) {
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tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
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@ -4735,12 +4732,18 @@ static int tg3_chip_reset(struct tg3 *tp)
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break;
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udelay(10);
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}
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if (i >= 100000) {
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printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
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"firmware will not restart magic=%08x\n",
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tp->dev->name, val);
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return -ENODEV;
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}
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/* Chip might not be fitted with firmare. Some Sun onboard
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* parts are configured like that. So don't signal the timeout
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* of the above loop as an error, but do report the lack of
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* running firmware once.
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*/
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if (i >= 100000 &&
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!(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
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tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
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printk(KERN_INFO PFX "%s: No firmware running.\n",
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tp->dev->name);
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}
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if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
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@ -9075,9 +9078,6 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
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{
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int j;
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if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
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return;
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tw32_f(GRC_EEPROM_ADDR,
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(EEPROM_ADDR_FSM_RESET |
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(EEPROM_DEFAULT_CLOCK_PERIOD <<
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@ -9210,11 +9210,6 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
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{
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int ret;
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if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
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printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
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return -EINVAL;
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}
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if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
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return tg3_nvram_read_using_eeprom(tp, offset, val);
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@ -9447,11 +9442,6 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
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{
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int ret;
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if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
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printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
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return -EINVAL;
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}
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|
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if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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|
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@ -9578,15 +9568,19 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
|
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tp->misc_host_ctrl);
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|
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/* The memory arbiter has to be enabled in order for SRAM accesses
|
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* to succeed. Normally on powerup the tg3 chip firmware will make
|
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* sure it is enabled, but other entities such as system netboot
|
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* code might disable it.
|
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*/
|
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val = tr32(MEMARB_MODE);
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tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
|
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|
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tp->phy_id = PHY_ID_INVALID;
|
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tp->led_ctrl = LED_CTRL_MODE_PHY_1;
|
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|
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/* Do not even try poking around in here on Sun parts. */
|
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if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
|
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/* All SUN chips are built-in LOMs. */
|
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/* Assume an onboard device by default. */
|
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tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
|
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return;
|
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}
|
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|
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tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
|
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if (val == NIC_SRAM_DATA_SIG_MAGIC) {
|
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|
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@ -9686,6 +9680,8 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
|
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|
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if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)
|
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tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
|
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else
|
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tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
|
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|
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if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
|
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tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
|
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|
|
@ -9834,16 +9830,8 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
|
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int i;
|
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u32 magic;
|
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|
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if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
|
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/* Sun decided not to put the necessary bits in the
|
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* NVRAM of their onboard tg3 parts :(
|
||||
*/
|
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strcpy(tp->board_part_number, "Sun 570X");
|
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return;
|
||||
}
|
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|
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if (tg3_nvram_read_swab(tp, 0x0, &magic))
|
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return;
|
||||
goto out_not_found;
|
||||
|
||||
if (magic == TG3_EEPROM_MAGIC) {
|
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for (i = 0; i < 256; i += 4) {
|
||||
|
|
@ -9874,6 +9862,9 @@ static void __devinit tg3_read_partno(struct tg3 *tp)
|
|||
break;
|
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msleep(1);
|
||||
}
|
||||
if (!(tmp16 & 0x8000))
|
||||
goto out_not_found;
|
||||
|
||||
pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
|
||||
&tmp);
|
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tmp = cpu_to_le32(tmp);
|
||||
|
|
@ -9965,37 +9956,6 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp)
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPARC64
|
||||
static int __devinit tg3_is_sun_570X(struct tg3 *tp)
|
||||
{
|
||||
struct pci_dev *pdev = tp->pdev;
|
||||
struct pcidev_cookie *pcp = pdev->sysdata;
|
||||
|
||||
if (pcp != NULL) {
|
||||
int node = pcp->prom_node;
|
||||
u32 venid;
|
||||
int err;
|
||||
|
||||
err = prom_getproperty(node, "subsystem-vendor-id",
|
||||
(char *) &venid, sizeof(venid));
|
||||
if (err == 0 || err == -1)
|
||||
return 0;
|
||||
if (venid == PCI_VENDOR_ID_SUN)
|
||||
return 1;
|
||||
|
||||
/* TG3 chips onboard the SunBlade-2500 don't have the
|
||||
* subsystem-vendor-id set to PCI_VENDOR_ID_SUN but they
|
||||
* are distinguishable from non-Sun variants by being
|
||||
* named "network" by the firmware. Non-Sun cards will
|
||||
* show up as being named "ethernet".
|
||||
*/
|
||||
if (!strcmp(pcp->prom_name, "network"))
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int __devinit tg3_get_invariants(struct tg3 *tp)
|
||||
{
|
||||
static struct pci_device_id write_reorder_chipsets[] = {
|
||||
|
|
@ -10012,11 +9972,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
|
|||
u16 pci_cmd;
|
||||
int err;
|
||||
|
||||
#ifdef CONFIG_SPARC64
|
||||
if (tg3_is_sun_570X(tp))
|
||||
tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
|
||||
#endif
|
||||
|
||||
/* Force memory write invalidate off. If we leave it on,
|
||||
* then on 5700_BX chips we have to enable a workaround.
|
||||
* The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
|
||||
|
|
@ -10312,8 +10267,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
|
|||
if (tp->write32 == tg3_write_indirect_reg32 ||
|
||||
((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
|
||||
(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
|
||||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) ||
|
||||
(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
|
||||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
|
||||
tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
|
||||
|
||||
/* Get eeprom hw config before calling tg3_set_power_state().
|
||||
|
|
@ -10594,8 +10548,7 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
|
|||
#endif
|
||||
|
||||
mac_offset = 0x7c;
|
||||
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
|
||||
!(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
|
||||
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
|
||||
(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
|
||||
if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
|
||||
mac_offset = 0xcc;
|
||||
|
|
@ -10622,8 +10575,7 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
|
|||
}
|
||||
if (!addr_ok) {
|
||||
/* Next, try NVRAM. */
|
||||
if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
|
||||
!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
|
||||
if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
|
||||
!tg3_nvram_read(tp, mac_offset + 4, &lo)) {
|
||||
dev->dev_addr[0] = ((hi >> 16) & 0xff);
|
||||
dev->dev_addr[1] = ((hi >> 24) & 0xff);
|
||||
|
|
|
|||
|
|
@ -2184,7 +2184,7 @@ struct tg3 {
|
|||
#define TG3_FLAG_INIT_COMPLETE 0x80000000
|
||||
u32 tg3_flags2;
|
||||
#define TG3_FLG2_RESTART_TIMER 0x00000001
|
||||
#define TG3_FLG2_SUN_570X 0x00000002
|
||||
/* 0x00000002 available */
|
||||
#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
|
||||
#define TG3_FLG2_IS_5788 0x00000008
|
||||
#define TG3_FLG2_MAX_RXPEND_64 0x00000010
|
||||
|
|
@ -2216,6 +2216,7 @@ struct tg3 {
|
|||
#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
|
||||
#define TG3_FLG2_1SHOT_MSI 0x10000000
|
||||
#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
|
||||
#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
|
||||
|
||||
u32 split_mode_max_reqs;
|
||||
#define SPLIT_MODE_5704_MAX_REQ 3
|
||||
|
|
|
|||
Loading…
Reference in a new issue