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sh: Prepare for dynamic PMB support
To allow the MMU to be switched between 29bit and 32bit mode at runtime some constants need to swapped for functions that return a runtime value. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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8bd642b17b
commit
1f69b6af91
7 changed files with 43 additions and 10 deletions
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@ -57,5 +57,11 @@
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#define P3_ADDR_MAX P4SEG
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#endif
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_PMB
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extern int __in_29bit_mode(void);
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#endif /* CONFIG_PMB */
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_ADDRSPACE_H */
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@ -7,6 +7,8 @@
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#define PMB_PASCR 0xff000070
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#define PMB_IRMCR 0xff000078
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#define PASCR_SE 0x80000000
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#define PMB_ADDR 0xf6100000
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#define PMB_DATA 0xf7100000
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#define PMB_ENTRY_MAX 16
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@ -75,4 +77,3 @@ void pmb_unmap(unsigned long addr);
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#endif /* __ASSEMBLY__ */
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#endif /* __MMU_H */
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@ -75,13 +75,31 @@ static inline unsigned long long neff_sign_extend(unsigned long val)
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#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0
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#ifdef CONFIG_32BIT
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#define PHYS_ADDR_MASK 0xffffffff
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#define PHYS_ADDR_MASK29 0x1fffffff
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#define PHYS_ADDR_MASK32 0xffffffff
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#ifdef CONFIG_PMB
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static inline unsigned long phys_addr_mask(void)
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{
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/* Is the MMU in 29bit mode? */
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if (__in_29bit_mode())
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return PHYS_ADDR_MASK29;
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return PHYS_ADDR_MASK32;
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}
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#elif CONFIG_32BIT
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static inline unsigned long phys_addr_mask(void)
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{
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return PHYS_ADDR_MASK32;
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}
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#else
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#define PHYS_ADDR_MASK 0x1fffffff
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static inline unsigned long phys_addr_mask(void)
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{
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return PHYS_ADDR_MASK29;
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}
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#endif
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#define PTE_PHYS_MASK (PHYS_ADDR_MASK & PAGE_MASK)
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#define PTE_PHYS_MASK (phys_addr_mask() & PAGE_MASK)
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#define PTE_FLAGS_MASK (~(PTE_PHYS_MASK) << PAGE_SHIFT)
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#ifdef CONFIG_SUPERH32
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@ -108,7 +108,7 @@ static inline unsigned long copy_ptea_attributes(unsigned long x)
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#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE)
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#endif
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#define _PAGE_FLAGS_HARDWARE_MASK (PHYS_ADDR_MASK & ~(_PAGE_CLEAR_FLAGS))
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#define _PAGE_FLAGS_HARDWARE_MASK (phys_addr_mask() & ~(_PAGE_CLEAR_FLAGS))
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/* Hardware flags, page size encoding */
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#if !defined(CONFIG_MMU)
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@ -1,7 +1,7 @@
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#ifndef __ASM_SH_SCATTERLIST_H
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#define __ASM_SH_SCATTERLIST_H
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#define ISA_DMA_THRESHOLD PHYS_ADDR_MASK
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#define ISA_DMA_THRESHOLD phys_addr_mask()
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#include <asm-generic/scatterlist.h>
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@ -88,12 +88,12 @@ static inline void flush_cache_4096(unsigned long start,
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unsigned long flags, exec_offset = 0;
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/*
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* All types of SH-4 require PC to be in P2 to operate on the I-cache.
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* Some types of SH-4 require PC to be in P2 to operate on the D-cache.
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* All types of SH-4 require PC to be uncached to operate on the I-cache.
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* Some types of SH-4 require PC to be uncached to operate on the D-cache.
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*/
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if ((boot_cpu_data.flags & CPU_HAS_P2_FLUSH_BUG) ||
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(start < CACHE_OC_ADDRESS_ARRAY))
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exec_offset = 0x20000000;
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exec_offset = cached_to_uncached;
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local_irq_save(flags);
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__flush_cache_4096(start | SH_CACHE_ASSOC,
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@ -323,4 +323,12 @@ int memory_add_physaddr_to_nid(u64 addr)
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}
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EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid);
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#endif
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#endif /* CONFIG_MEMORY_HOTPLUG */
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#ifdef CONFIG_PMB
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int __in_29bit_mode(void)
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{
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return !(ctrl_inl(PMB_PASCR) & PASCR_SE);
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}
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#endif /* CONFIG_PMB */
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