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drm/amdgpu: only harvest gcea/mmea error status in aldebaran
In aldebaran, driver only needs to harvest SDP RdRspStatus, WrRspStatus and first parity error on RdRsp data. Check error type before harvest error information. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Stanley Yang <Stanley.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
53ee6609b4
commit
1f8d3ad2a0
2 changed files with 19 additions and 13 deletions
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@ -808,7 +808,7 @@ static struct gfx_v9_4_2_utc_block gfx_v9_4_2_utc_blocks[] = {
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REG_SET_FIELD(0, ATC_L2_CACHE_4K_DSM_CNTL, WRITE_COUNTERS, 1) },
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};
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static const struct soc15_reg_entry gfx_v9_4_2_rdrsp_status_regs =
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static const struct soc15_reg_entry gfx_v9_4_2_ea_err_status_regs =
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{ SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16 };
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static int gfx_v9_4_2_get_reg_error_count(struct amdgpu_device *adev,
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@ -1041,11 +1041,11 @@ static void gfx_v9_4_2_reset_ea_err_status(struct amdgpu_device *adev)
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uint32_t i, j;
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mutex_lock(&adev->grbm_idx_mutex);
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for (i = 0; i < gfx_v9_4_2_rdrsp_status_regs.se_num; i++) {
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for (j = 0; j < gfx_v9_4_2_rdrsp_status_regs.instance;
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for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) {
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for (j = 0; j < gfx_v9_4_2_ea_err_status_regs.instance;
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j++) {
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gfx_v9_4_2_select_se_sh(adev, i, 0, j);
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WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_rdrsp_status_regs), 0x10);
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WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), 0x10);
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}
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}
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gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
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@ -1090,17 +1090,20 @@ static void gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev)
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mutex_lock(&adev->grbm_idx_mutex);
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for (i = 0; i < gfx_v9_4_2_rdrsp_status_regs.se_num; i++) {
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for (j = 0; j < gfx_v9_4_2_rdrsp_status_regs.instance;
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for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) {
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for (j = 0; j < gfx_v9_4_2_ea_err_status_regs.instance;
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j++) {
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gfx_v9_4_2_select_se_sh(adev, i, 0, j);
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reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
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gfx_v9_4_2_rdrsp_status_regs));
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if ((reg_value & 0xFFF) != GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK)
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gfx_v9_4_2_ea_err_status_regs));
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if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||
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REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||
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REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
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dev_warn(adev->dev, "GCEA err detected at instance: %d, status: 0x%x!\n",
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j, reg_value);
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}
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/* clear after read */
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WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_rdrsp_status_regs), 0x10);
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WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), 0x10);
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}
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}
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@ -1286,7 +1286,7 @@ static void mmhub_v1_7_reset_ras_error_count(struct amdgpu_device *adev)
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}
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}
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static const struct soc15_reg_entry mmhub_v1_7_err_status_regs[] = {
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static const struct soc15_reg_entry mmhub_v1_7_ea_err_status_regs[] = {
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{ SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_ERR_STATUS), 0, 0, 0 },
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{ SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_ERR_STATUS), 0, 0, 0 },
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{ SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_ERR_STATUS), 0, 0, 0 },
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@ -1303,12 +1303,15 @@ static void mmhub_v1_7_query_ras_error_status(struct amdgpu_device *adev)
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if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
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return;
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for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_err_status_regs); i++) {
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for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) {
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reg_value =
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RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_err_status_regs[i]));
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if ((reg_value & 0xFFF) != MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK)
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RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]));
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if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||
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REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||
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REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
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dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n",
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i, reg_value);
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}
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}
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}
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