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drm/amdgpu: use a fence array for VMID management
Just wait for any fence to become available, instead of waiting for the last entry of the LRU. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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8d76001e00
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1fbb2e9299
4 changed files with 110 additions and 112 deletions
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@ -597,10 +597,8 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
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struct amdgpu_sync *sync,
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struct reservation_object *resv,
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void *owner);
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bool amdgpu_sync_is_idle(struct amdgpu_sync *sync,
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struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
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struct amdgpu_ring *ring);
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int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src,
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struct fence *fence);
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struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
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void amdgpu_sync_free(struct amdgpu_sync *sync);
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int amdgpu_sync_init(void);
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@ -909,6 +907,10 @@ struct amdgpu_vm_manager {
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struct list_head ids_lru;
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struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
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/* Handling of VM fences */
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u64 fence_context;
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unsigned seqno[AMDGPU_MAX_RINGS];
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uint32_t max_pfn;
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/* vram base address for page table entry */
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u64 vram_base_offset;
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@ -166,7 +166,7 @@ static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job)
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}
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job = to_amdgpu_job(sched_job);
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BUG_ON(!amdgpu_sync_is_idle(&job->sync, NULL));
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BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
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trace_amdgpu_sched_run_job(job);
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r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
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@ -223,15 +223,15 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
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}
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/**
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* amdgpu_sync_is_idle - test if all fences are signaled
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* amdgpu_sync_peek_fence - get the next fence not signaled yet
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*
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* @sync: the sync object
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* @ring: optional ring to use for test
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*
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* Returns true if all fences in the sync object are signaled or scheduled to
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* the ring (if provided).
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* Returns the next fence not signaled yet without removing it from the sync
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* object.
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*/
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bool amdgpu_sync_is_idle(struct amdgpu_sync *sync,
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struct fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
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struct amdgpu_ring *ring)
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{
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struct amdgpu_sync_entry *e;
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@ -246,9 +246,12 @@ bool amdgpu_sync_is_idle(struct amdgpu_sync *sync,
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/* For fences from the same ring it is sufficient
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* when they are scheduled.
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*/
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if (s_fence->sched == &ring->sched &&
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fence_is_signaled(&s_fence->scheduled))
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if (s_fence->sched == &ring->sched) {
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if (fence_is_signaled(&s_fence->scheduled))
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continue;
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return &s_fence->scheduled;
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}
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}
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if (fence_is_signaled(f)) {
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@ -258,56 +261,10 @@ bool amdgpu_sync_is_idle(struct amdgpu_sync *sync,
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continue;
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}
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return false;
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return f;
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}
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return true;
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}
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/**
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* amdgpu_sync_cycle_fences - move fences from one sync object into another
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*
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* @dst: the destination sync object
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* @src: the source sync object
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* @fence: fence to add to source
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*
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* Remove all fences from source and put them into destination and add
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* fence as new one into source.
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*/
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int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src,
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struct fence *fence)
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{
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struct amdgpu_sync_entry *e, *newone;
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struct hlist_node *tmp;
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int i;
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/* Allocate the new entry before moving the old ones */
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newone = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL);
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if (!newone)
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return -ENOMEM;
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hash_for_each_safe(src->fences, i, tmp, e, node) {
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struct fence *f = e->fence;
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hash_del(&e->node);
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if (fence_is_signaled(f)) {
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fence_put(f);
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kmem_cache_free(amdgpu_sync_slab, e);
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continue;
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}
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if (amdgpu_sync_add_later(dst, f)) {
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kmem_cache_free(amdgpu_sync_slab, e);
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continue;
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}
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hash_add(dst->fences, &e->node, f->context);
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}
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hash_add(src->fences, &newone->node, fence->context);
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newone->fence = fence_get(fence);
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return 0;
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return NULL;
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}
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/**
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@ -25,6 +25,7 @@
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/fence-array.h>
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#include <drm/drmP.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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@ -180,25 +181,60 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
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struct amdgpu_device *adev = ring->adev;
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struct fence *updates = sync->last_vm_update;
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struct amdgpu_vm_id *id, *idle;
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unsigned i = ring->idx;
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int r;
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struct fence **fences;
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unsigned i;
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int r = 0;
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fences = kmalloc_array(sizeof(void *), adev->vm_manager.num_ids,
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GFP_KERNEL);
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if (!fences)
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return -ENOMEM;
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mutex_lock(&adev->vm_manager.lock);
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/* Check if we have an idle VMID */
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i = 0;
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list_for_each_entry(idle, &adev->vm_manager.ids_lru, list) {
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if (amdgpu_sync_is_idle(&idle->active, ring))
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fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
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if (!fences[i])
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break;
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++i;
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}
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/* If we can't find a idle VMID to use, just wait for the oldest */
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/* If we can't find a idle VMID to use, wait till one becomes available */
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if (&idle->list == &adev->vm_manager.ids_lru) {
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id = list_first_entry(&adev->vm_manager.ids_lru,
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struct amdgpu_vm_id,
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list);
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} else {
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u64 fence_context = adev->vm_manager.fence_context + ring->idx;
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unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
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struct fence_array *array;
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unsigned j;
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for (j = 0; j < i; ++j)
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fence_get(fences[j]);
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array = fence_array_create(i, fences, fence_context,
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seqno, true);
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if (!array) {
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for (j = 0; j < i; ++j)
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fence_put(fences[j]);
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kfree(fences);
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r = -ENOMEM;
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goto error;
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}
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r = amdgpu_sync_fence(ring->adev, sync, &array->base);
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fence_put(&array->base);
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if (r)
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goto error;
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mutex_unlock(&adev->vm_manager.lock);
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return 0;
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}
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kfree(fences);
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/* Check if we can use a VMID already assigned to this VM */
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i = ring->idx;
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do {
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struct fence *flushed;
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@ -216,13 +252,13 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
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if (pd_addr != id->pd_gpu_addr)
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continue;
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if (id->last_user != ring && (!id->last_flush ||
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!fence_is_signaled(id->last_flush)))
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if (id->last_user != ring &&
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(!id->last_flush || !fence_is_signaled(id->last_flush)))
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continue;
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flushed = id->flushed_updates;
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if (updates && (!flushed ||
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fence_is_later(updates, flushed)))
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if (updates &&
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(!flushed || fence_is_later(updates, flushed)))
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continue;
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/* Good we can use this VMID */
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@ -243,8 +279,7 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
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*vm_id = id - adev->vm_manager.ids;
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*vm_pd_addr = AMDGPU_VM_NO_FLUSH;
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trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id,
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*vm_pd_addr);
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trace_amdgpu_vm_grab_id(vm, ring->idx, *vm_id, *vm_pd_addr);
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mutex_unlock(&adev->vm_manager.lock);
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return 0;
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@ -253,9 +288,9 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
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/* Still no ID to use? Then use the idle one found earlier */
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id = idle;
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}
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r = amdgpu_sync_cycle_fences(sync, &id->active, fence);
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/* Remember this submission as user of the VMID */
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r = amdgpu_sync_fence(ring->adev, &id->active, fence);
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if (r)
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goto error;
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@ -1515,6 +1550,10 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
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&adev->vm_manager.ids_lru);
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}
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adev->vm_manager.fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
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for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
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adev->vm_manager.seqno[i] = 0;
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atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
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atomic64_set(&adev->vm_manager.client_counter, 0);
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}
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