mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-21 16:29:59 +00:00
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/radeon/kms: fix channel_remap setup (v2) drm/radeon: Set cursor x/y to 0 when x/yorigin > 0. drm/radeon: Update AVIVO cursor coordinate origin before x/yorigin calculation. drm/radeon: Simplify cursor x/yorigin calculation. drm/radeon/kms: fix cursor image off-by-one error drm/radeon/kms: Fix logic error in DP HPD handler drm/radeon/kms: add retry limits for native DP aux defer drm/radeon/kms: fix regression in DP aux defer handling
This commit is contained in:
commit
1fd2a850ec
6 changed files with 33 additions and 158 deletions
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@ -115,6 +115,7 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
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u8 msg[20];
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int msg_bytes = send_bytes + 4;
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u8 ack;
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unsigned retry;
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if (send_bytes > 16)
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return -1;
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@ -125,20 +126,20 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
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msg[3] = (msg_bytes << 4) | (send_bytes - 1);
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memcpy(&msg[4], send, send_bytes);
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while (1) {
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for (retry = 0; retry < 4; retry++) {
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ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
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msg, msg_bytes, NULL, 0, delay, &ack);
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if (ret < 0)
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return ret;
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if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
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break;
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return send_bytes;
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else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
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udelay(400);
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else
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return -EIO;
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}
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return send_bytes;
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return -EIO;
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}
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static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
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@ -149,26 +150,29 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
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int msg_bytes = 4;
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u8 ack;
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int ret;
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unsigned retry;
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msg[0] = address;
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msg[1] = address >> 8;
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msg[2] = AUX_NATIVE_READ << 4;
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msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
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while (1) {
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for (retry = 0; retry < 4; retry++) {
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ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
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msg, msg_bytes, recv, recv_bytes, delay, &ack);
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if (ret == 0)
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return -EPROTO;
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if (ret < 0)
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return ret;
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if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
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return ret;
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else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
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udelay(400);
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else if (ret == 0)
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return -EPROTO;
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else
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return -EIO;
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}
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return -EIO;
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}
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static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
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@ -1590,48 +1590,6 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
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return backend_map;
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}
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static void evergreen_program_channel_remap(struct radeon_device *rdev)
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{
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u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
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tmp = RREG32(MC_SHARED_CHMAP);
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switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
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case 0:
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case 1:
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case 2:
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case 3:
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default:
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/* default mapping */
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mc_shared_chremap = 0x00fac688;
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break;
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}
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switch (rdev->family) {
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case CHIP_HEMLOCK:
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case CHIP_CYPRESS:
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case CHIP_BARTS:
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tcp_chan_steer_lo = 0x54763210;
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tcp_chan_steer_hi = 0x0000ba98;
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break;
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case CHIP_JUNIPER:
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case CHIP_REDWOOD:
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case CHIP_CEDAR:
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case CHIP_PALM:
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case CHIP_SUMO:
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case CHIP_SUMO2:
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case CHIP_TURKS:
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case CHIP_CAICOS:
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default:
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tcp_chan_steer_lo = 0x76543210;
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tcp_chan_steer_hi = 0x0000ba98;
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break;
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}
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WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
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WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
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WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
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}
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static void evergreen_gpu_init(struct radeon_device *rdev)
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{
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u32 cc_rb_backend_disable = 0;
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@ -2078,8 +2036,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
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WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
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WREG32(HDP_ADDR_CONFIG, gb_addr_config);
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evergreen_program_channel_remap(rdev);
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num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
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grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
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@ -569,36 +569,6 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
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return backend_map;
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}
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static void cayman_program_channel_remap(struct radeon_device *rdev)
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{
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u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
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tmp = RREG32(MC_SHARED_CHMAP);
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switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
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case 0:
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case 1:
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case 2:
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case 3:
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default:
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/* default mapping */
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mc_shared_chremap = 0x00fac688;
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break;
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}
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switch (rdev->family) {
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case CHIP_CAYMAN:
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default:
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//tcp_chan_steer_lo = 0x54763210
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tcp_chan_steer_lo = 0x76543210;
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tcp_chan_steer_hi = 0x0000ba98;
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break;
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}
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WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
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WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
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WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
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}
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static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
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u32 disable_mask_per_se,
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u32 max_disable_mask_per_se,
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@ -842,8 +812,6 @@ static void cayman_gpu_init(struct radeon_device *rdev)
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WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
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WREG32(HDP_ADDR_CONFIG, gb_addr_config);
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cayman_program_channel_remap(rdev);
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/* primary versions */
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WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
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WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
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@ -68,11 +68,11 @@ void radeon_connector_hotplug(struct drm_connector *connector)
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if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
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int saved_dpms = connector->dpms;
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if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) &&
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radeon_dp_needs_link_train(radeon_connector))
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drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
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else
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/* Only turn off the display it it's physically disconnected */
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if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
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drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
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else if (radeon_dp_needs_link_train(radeon_connector))
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drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
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connector->dpms = saved_dpms;
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}
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}
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@ -208,24 +208,26 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
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int xorigin = 0, yorigin = 0;
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int w = radeon_crtc->cursor_width;
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if (x < 0)
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xorigin = -x + 1;
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if (y < 0)
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yorigin = -y + 1;
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if (xorigin >= CURSOR_WIDTH)
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xorigin = CURSOR_WIDTH - 1;
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if (yorigin >= CURSOR_HEIGHT)
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yorigin = CURSOR_HEIGHT - 1;
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if (ASIC_IS_AVIVO(rdev)) {
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/* avivo cursor are offset into the total surface */
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x += crtc->x;
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y += crtc->y;
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}
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DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
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if (x < 0) {
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xorigin = min(-x, CURSOR_WIDTH - 1);
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x = 0;
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}
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if (y < 0) {
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yorigin = min(-y, CURSOR_HEIGHT - 1);
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y = 0;
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}
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if (ASIC_IS_AVIVO(rdev)) {
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int i = 0;
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struct drm_crtc *crtc_p;
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/* avivo cursor are offset into the total surface */
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x += crtc->x;
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y += crtc->y;
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DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
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/* avivo cursor image can't end on 128 pixel boundary or
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* go past the end of the frame if both crtcs are enabled
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*/
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@ -253,16 +255,12 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
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radeon_lock_cursor(crtc, true);
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if (ASIC_IS_DCE4(rdev)) {
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WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset,
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((xorigin ? 0 : x) << 16) |
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(yorigin ? 0 : y));
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WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
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WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
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WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
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((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
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} else if (ASIC_IS_AVIVO(rdev)) {
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WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
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((xorigin ? 0 : x) << 16) |
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(yorigin ? 0 : y));
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WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
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WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
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WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
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((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
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@ -276,8 +274,8 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
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| yorigin));
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WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
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(RADEON_CUR_LOCK
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| ((xorigin ? 0 : x) << 16)
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| (yorigin ? 0 : y)));
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| (x << 16)
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| y));
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/* offset is from DISP(2)_BASE_ADDRESS */
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
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(yorigin * 256)));
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@ -536,55 +536,6 @@ static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
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return backend_map;
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}
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static void rv770_program_channel_remap(struct radeon_device *rdev)
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{
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u32 tcp_chan_steer, mc_shared_chremap, tmp;
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bool force_no_swizzle;
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switch (rdev->family) {
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case CHIP_RV770:
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case CHIP_RV730:
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force_no_swizzle = false;
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break;
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case CHIP_RV710:
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case CHIP_RV740:
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default:
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force_no_swizzle = true;
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break;
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}
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tmp = RREG32(MC_SHARED_CHMAP);
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switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
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case 0:
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case 1:
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default:
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/* default mapping */
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mc_shared_chremap = 0x00fac688;
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break;
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case 2:
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case 3:
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if (force_no_swizzle)
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mc_shared_chremap = 0x00fac688;
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else
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mc_shared_chremap = 0x00bbc298;
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break;
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}
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if (rdev->family == CHIP_RV740)
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tcp_chan_steer = 0x00ef2a60;
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else
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tcp_chan_steer = 0x00fac688;
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/* RV770 CE has special chremap setup */
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if (rdev->pdev->device == 0x944e) {
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tcp_chan_steer = 0x00b08b08;
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mc_shared_chremap = 0x00b08b08;
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}
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WREG32(TCP_CHAN_STEER, tcp_chan_steer);
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WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
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}
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static void rv770_gpu_init(struct radeon_device *rdev)
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{
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int i, j, num_qd_pipes;
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@ -785,8 +736,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
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WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
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WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
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rv770_program_channel_remap(rdev);
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WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
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WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
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WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
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