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bcma: change delays to follow timers-howto guide
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
f1b98bb367
commit
1fd41a65f1
4 changed files with 12 additions and 9 deletions
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@ -65,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma_device *core,
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switch (clkmode) {
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switch (clkmode) {
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case BCMA_CLKMODE_FAST:
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case BCMA_CLKMODE_FAST:
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bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
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bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
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udelay(64);
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usleep_range(64, 300);
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for (i = 0; i < 1500; i++) {
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for (i = 0; i < 1500; i++) {
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if (bcma_read32(core, BCMA_CLKCTLST) &
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if (bcma_read32(core, BCMA_CLKCTLST) &
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BCMA_CLKCTLST_HAVEHT) {
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BCMA_CLKCTLST_HAVEHT) {
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@ -76,7 +76,10 @@ static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
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if (max_msk)
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if (max_msk)
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bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
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bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
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/* Add some delay; allow resources to come up and settle. */
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/*
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* Add some delay; allow resources to come up and settle.
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* Delay is required for SoC (early init).
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*/
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mdelay(2);
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mdelay(2);
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}
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}
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@ -51,7 +51,7 @@ static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
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break;
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break;
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msleep(1);
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usleep_range(1000, 2000);
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}
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}
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}
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}
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@ -92,7 +92,7 @@ static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
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ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
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ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
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break;
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break;
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}
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}
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msleep(1);
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usleep_range(1000, 2000);
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}
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}
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
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return ret;
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return ret;
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@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
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if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
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break;
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break;
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msleep(1);
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usleep_range(1000, 2000);
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}
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}
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
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pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
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}
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}
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@ -425,9 +425,9 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
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pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
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pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
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/* Reset RC */
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/* Reset RC */
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udelay(3000);
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usleep_range(3000, 5000);
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pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
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pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
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udelay(1000);
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usleep_range(1000, 2000);
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pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
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pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
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BCMA_CORE_PCI_CTL_RST_OE);
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BCMA_CORE_PCI_CTL_RST_OE);
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@ -481,7 +481,7 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
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* before issuing configuration requests to PCI Express
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* before issuing configuration requests to PCI Express
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* devices.
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* devices.
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*/
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*/
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udelay(100000);
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msleep(100);
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bcma_core_pci_enable_crs(pc);
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bcma_core_pci_enable_crs(pc);
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@ -501,7 +501,7 @@ void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
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set_io_port_base(pc_host->pci_controller.io_map_base);
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set_io_port_base(pc_host->pci_controller.io_map_base);
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/* Give some time to the PCI controller to configure itself with the new
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/* Give some time to the PCI controller to configure itself with the new
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* values. Not waiting at this point causes crashes of the machine. */
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* values. Not waiting at this point causes crashes of the machine. */
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mdelay(10);
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usleep_range(10000, 15000);
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register_pci_controller(&pc_host->pci_controller);
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register_pci_controller(&pc_host->pci_controller);
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return;
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return;
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}
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}
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