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x86/cpu: Restore AMD's DE_CFG MSR after resume
commit2632daebaf
upstream. DE_CFG contains the LFENCE serializing bit, restore it on resume too. This is relevant to older families due to the way how they do S3. Unify and correct naming while at it. Fixes:e4d0e84e49
("x86/cpu/AMD: Make LFENCE a serializing instruction") Reported-by: Andrew Cooper <Andrew.Cooper3@citrix.com> Reported-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: <stable@kernel.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
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30b0263d03
commit
1fd66e3b02
7 changed files with 21 additions and 18 deletions
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@ -454,6 +454,11 @@
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#define MSR_AMD64_OSVW_STATUS 0xc0010141
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#define MSR_AMD64_LS_CFG 0xc0011020
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#define MSR_AMD64_DC_CFG 0xc0011022
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#define MSR_AMD64_DE_CFG 0xc0011029
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#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
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#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
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#define MSR_AMD64_BU_CFG2 0xc001102a
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#define MSR_AMD64_IBSFETCHCTL 0xc0011030
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#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
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@ -522,9 +527,6 @@
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#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
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#define FAM10H_MMIO_CONF_BASE_SHIFT 20
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#define MSR_FAM10H_NODE_ID 0xc001100c
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#define MSR_F10H_DECFG 0xc0011029
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#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
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#define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
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/* K8 MSRs */
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#define MSR_K8_TOP_MEM1 0xc001001a
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@ -794,8 +794,6 @@ static void init_amd_gh(struct cpuinfo_x86 *c)
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set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
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}
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#define MSR_AMD64_DE_CFG 0xC0011029
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static void init_amd_ln(struct cpuinfo_x86 *c)
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{
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/*
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@ -965,8 +963,8 @@ static void init_amd(struct cpuinfo_x86 *c)
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* msr_set_bit() uses the safe accessors, too, even if the MSR
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* is not present.
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*/
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msr_set_bit(MSR_F10H_DECFG,
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MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
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msr_set_bit(MSR_AMD64_DE_CFG,
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MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
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/* A serializing LFENCE stops RDTSC speculation */
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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@ -335,8 +335,8 @@ static void init_hygon(struct cpuinfo_x86 *c)
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* msr_set_bit() uses the safe accessors, too, even if the MSR
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* is not present.
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*/
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msr_set_bit(MSR_F10H_DECFG,
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MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
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msr_set_bit(MSR_AMD64_DE_CFG,
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MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
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/* A serializing LFENCE stops RDTSC speculation */
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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@ -4180,9 +4180,9 @@ static int svm_get_msr_feature(struct kvm_msr_entry *msr)
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msr->data = 0;
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switch (msr->index) {
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case MSR_F10H_DECFG:
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if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
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msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
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case MSR_AMD64_DE_CFG:
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if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
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msr->data |= MSR_AMD64_DE_CFG_LFENCE_SERIALIZE;
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break;
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default:
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return 1;
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@ -4284,7 +4284,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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msr_info->data = 0x1E;
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}
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break;
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case MSR_F10H_DECFG:
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case MSR_AMD64_DE_CFG:
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msr_info->data = svm->msr_decfg;
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break;
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default:
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@ -4451,7 +4451,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
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case MSR_VM_IGNNE:
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vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
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break;
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case MSR_F10H_DECFG: {
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case MSR_AMD64_DE_CFG: {
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struct kvm_msr_entry msr_entry;
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msr_entry.index = msr->index;
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@ -1337,7 +1337,7 @@ static const u32 msr_based_features_all[] = {
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MSR_IA32_VMX_EPT_VPID_CAP,
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MSR_IA32_VMX_VMFUNC,
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MSR_F10H_DECFG,
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MSR_AMD64_DE_CFG,
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MSR_IA32_UCODE_REV,
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MSR_IA32_ARCH_CAPABILITIES,
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};
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@ -528,6 +528,7 @@ static void pm_save_spec_msr(void)
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MSR_TSX_FORCE_ABORT,
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MSR_IA32_MCU_OPT_CTRL,
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MSR_AMD64_LS_CFG,
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MSR_AMD64_DE_CFG,
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};
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msr_build_context(spec_msr_id, ARRAY_SIZE(spec_msr_id));
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@ -635,6 +635,11 @@ void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
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#define MSR_AMD64_OSVW_STATUS 0xc0010141
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#define MSR_AMD64_LS_CFG 0xc0011020
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#define MSR_AMD64_DC_CFG 0xc0011022
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#define MSR_AMD64_DE_CFG 0xc0011029
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#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
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#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
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#define MSR_AMD64_BU_CFG2 0xc001102a
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#define MSR_AMD64_IBSFETCHCTL 0xc0011030
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#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
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@ -685,9 +690,6 @@ void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
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#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
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#define FAM10H_MMIO_CONF_BASE_SHIFT 20
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#define MSR_FAM10H_NODE_ID 0xc001100c
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#define MSR_F10H_DECFG 0xc0011029
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#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1
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#define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
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/* K8 MSRs */
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#define MSR_K8_TOP_MEM1 0xc001001a
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