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PCI: Factor out pcie_retrain_link() function
commit 86fa6a3442
upstream.
Factor out pcie_retrain_link() to use for Pericom Retrain Link quirk. No
functional change intended.
Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
CC: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
600851390c
commit
1ff1691b8f
1 changed files with 24 additions and 16 deletions
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@ -211,6 +211,29 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
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link->clkpm_capable = (blacklist) ? 0 : capable;
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link->clkpm_capable = (blacklist) ? 0 : capable;
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}
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}
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static bool pcie_retrain_link(struct pcie_link_state *link)
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{
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struct pci_dev *parent = link->pdev;
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unsigned long start_jiffies;
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u16 reg16;
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pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
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reg16 |= PCI_EXP_LNKCTL_RL;
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
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/* Wait for link training end. Break out after waiting for timeout */
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start_jiffies = jiffies;
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for (;;) {
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pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_LT))
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break;
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if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
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break;
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msleep(1);
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}
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return !(reg16 & PCI_EXP_LNKSTA_LT);
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}
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/*
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/*
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* pcie_aspm_configure_common_clock: check if the 2 ends of a link
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* pcie_aspm_configure_common_clock: check if the 2 ends of a link
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* could use common clock. If they are, configure them to use the
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* could use common clock. If they are, configure them to use the
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@ -220,7 +243,6 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
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{
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{
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int same_clock = 1;
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int same_clock = 1;
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u16 reg16, parent_reg, child_reg[8];
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u16 reg16, parent_reg, child_reg[8];
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unsigned long start_jiffies;
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struct pci_dev *child, *parent = link->pdev;
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struct pci_dev *child, *parent = link->pdev;
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struct pci_bus *linkbus = parent->subordinate;
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struct pci_bus *linkbus = parent->subordinate;
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/*
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/*
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@ -260,21 +282,7 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
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reg16 &= ~PCI_EXP_LNKCTL_CCC;
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reg16 &= ~PCI_EXP_LNKCTL_CCC;
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
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/* Retrain link */
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if (pcie_retrain_link(link))
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reg16 |= PCI_EXP_LNKCTL_RL;
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pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
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/* Wait for link training end. Break out after waiting for timeout */
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start_jiffies = jiffies;
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for (;;) {
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pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
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if (!(reg16 & PCI_EXP_LNKSTA_LT))
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break;
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if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
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break;
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msleep(1);
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}
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if (!(reg16 & PCI_EXP_LNKSTA_LT))
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return;
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return;
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/* Training failed. Restore common clock configurations */
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/* Training failed. Restore common clock configurations */
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