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ARM: SoC fixes for 4.17-rc

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A handful of fixes. I've been queuing them up a bit too long so the list
 is longer than it otherwise would have been spread out across a few -rcs.
 
 In general, it's a scattering of fixes across several platforms, nothing
 truly serious enough to point out.
 
 There's a slightly larger batch of them for the Davinci platforms due
 to work to bring them back to life after some time, so there's a handful
 of regressions, some of them going back very far, others more recent.
 
 There's also a few patches fixing DT on Renesas platforms since they
 changed some bindings without remaining backwards compatible, splitting
 up describing LVDS as a proper bridge instead of having it as part of the
 display unit. We could push for them to be backwards compatible with old
 device trees, but it's likely to regress eventually if nobody's actually
 using said compatibility.
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "A handful of fixes. I've been queuing them up a bit too long so the
  list is longer than it otherwise would have been spread out across a
  few -rcs.

  In general, it's a scattering of fixes across several platforms,
  nothing truly serious enough to point out.

  There's a slightly larger batch of them for the Davinci platforms due
  to work to bring them back to life after some time, so there's a
  handful of regressions, some of them going back very far, others more
  recent.

  There's also a few patches fixing DT on Renesas platforms since they
  changed some bindings without remaining backwards compatible,
  splitting up describing LVDS as a proper bridge instead of having it
  as part of the display unit.

  We could push for them to be backwards compatible with old device
  trees, but it's likely to regress eventually if nobody's actually
  using said compatibility"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (36 commits)
  ARM: davinci: board-dm646x-evm: set VPIF capture card name
  ARM: davinci: board-dm646x-evm: pass correct I2C adapter id for VPIF
  ARM: davinci: dm646x: fix timer interrupt generation
  ARM: keystone: fix platform_domain_notifier array overrun
  arm64: dts: exynos: Fix interrupt type for I2S1 device on Exynos5433
  ARM: dts: imx51-zii-rdu1: fix touchscreen bindings
  firmware: arm_scmi: Use after free in scmi_create_protocol_device()
  ARM: dts: cygnus: fix irq type for arm global timer
  Revert "ARM: dts: logicpd-som-lv: Fix pinmux controller references"
  tee: check shm references are consistent in offset/size
  tee: shm: fix use-after-free via temporarily dropped reference
  ARM: dts: imx7s: Pass the 'fsl,sec-era' property
  ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20"
  ARM: dts: correct missing "compatible" entry for ti81xx SoCs
  ARM: OMAP1: ams-delta: fix deferred_fiq handler
  arm64: tegra: Make BCM89610 PHY interrupt as active low
  ARM: davinci: fix GPIO lookup for I2C
  ARM: dts: logicpd-som-lv: Fix pinmux controller references
  ARM: dts: logicpd-som-lv: Fix Audio Mute
  ARM: dts: logicpd-som-lv: Fix WL127x Startup Issues
  ...
This commit is contained in:
Linus Torvalds 2018-05-19 19:56:15 -07:00
commit 203ec2fed1
40 changed files with 299 additions and 95 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
Documentation/devicetree/bindings/net/marvell-pp2.txt
View file

@ -21,9 +21,10 @@ Required properties:
- main controller clock (for both armada-375-pp2 and armada-7k-pp2)
- GOP clock (for both armada-375-pp2 and armada-7k-pp2)
- MG clock (only for armada-7k-pp2)
- MG Core clock (only for armada-7k-pp2)
- AXI clock (only for armada-7k-pp2)
- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk"
and "axi_clk" (the 2 latter only for armada-7k-pp2).
- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk",
"mg_core_clk" and "axi_clk" (the 3 latter only for armada-7k-pp2).
The ethernet ports are represented by subnodes. At least one port is
required.
@ -80,8 +81,8 @@ cpm_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
<&cpm_syscon0 1 5>, <&cpm_syscon0 1 18>;
clock-names = "pp_clk", "gop_clk", "gp_clk", "axi_clk";
<&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>;
clock-names = "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk";
eth0: eth0 {
interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm/boot/dts/bcm-cygnus.dtsi
View file

@ -69,7 +69,7 @@ core {
timer@20200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x20200 0x100>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
clocks = <&periph_clk>;
};

4
arch/arm/boot/dts/da850-lcdk.dts
View file

@ -21,8 +21,8 @@ chosen {
stdout-path = "serial2:115200n8";
};
memory {
device_type = "memory";
memory@c0000000 {
/* 128 MB DDR2 SDRAM @ 0xc0000000 */
reg = <0xc0000000 0x08000000>;
};

13
arch/arm/boot/dts/da850.dtsi
View file

@ -7,10 +7,19 @@
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases { };
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x0>;
};
arm {
#address-cells = <1>;
#size-cells = <1>;
@ -46,8 +55,6 @@ soc@1c00000 {
pmx_core: pinmux@14120 {
compatible = "pinctrl-single";
reg = <0x14120 0x50>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <2>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;

2
arch/arm/boot/dts/dm8148-evm.dts
View file

@ -10,7 +10,7 @@
/ {
model = "DM8148 EVM";
compatible = "ti,dm8148-evm", "ti,dm8148";
compatible = "ti,dm8148-evm", "ti,dm8148", "ti,dm814";
memory@80000000 {
device_type = "memory";

2
arch/arm/boot/dts/dm8148-t410.dts
View file

@ -9,7 +9,7 @@
/ {
model = "HP t410 Smart Zero Client";
compatible = "hp,t410", "ti,dm8148";
compatible = "hp,t410", "ti,dm8148", "ti,dm814";
memory@80000000 {
device_type = "memory";

2
arch/arm/boot/dts/dm8168-evm.dts
View file

@ -10,7 +10,7 @@
/ {
model = "DM8168 EVM";
compatible = "ti,dm8168-evm", "ti,dm8168";
compatible = "ti,dm8168-evm", "ti,dm8168", "ti,dm816";
memory@80000000 {
device_type = "memory";

2
arch/arm/boot/dts/dra62x-j5eco-evm.dts
View file

@ -10,7 +10,7 @@
/ {
model = "DRA62x J5 Eco EVM";
compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148";
compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148", "ti,dm814";
memory@80000000 {
device_type = "memory";

6
arch/arm/boot/dts/imx51-zii-rdu1.dts
View file

@ -523,7 +523,7 @@ touchscreen@4c {
};
touchscreen@20 {
compatible = "syna,rmi4_i2c";
compatible = "syna,rmi4-i2c";
reg = <0x20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ts>;
@ -541,8 +541,8 @@ rmi4-f01@1 {
rmi4-f11@11 {
reg = <0x11>;
touch-inverted-y;
touch-swapped-x-y;
touchscreen-inverted-y;
touchscreen-swapped-x-y;
syna,sensor-type = <1>;
};
};

1
arch/arm/boot/dts/imx7s.dtsi
View file

@ -868,6 +868,7 @@ sai3: sai@308c0000 {
crypto: caam@30900000 {
compatible = "fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x30900000 0x40000>;

11
arch/arm/boot/dts/logicpd-som-lv.dtsi
View file

@ -26,7 +26,7 @@ wl12xx_vmmc: wl12xx_vmmc {
gpio = <&gpio1 3 0>; /* gpio_3 */
startup-delay-us = <70000>;
enable-active-high;
vin-supply = <&vmmc2>;
vin-supply = <&vaux3>;
};
/* HS USB Host PHY on PORT 1 */
@ -82,6 +82,7 @@ twl: twl@48 {
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
ti,hs_extmute_gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
};
};
};
@ -199,6 +200,7 @@ i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
>;
};
};
@ -213,7 +215,7 @@ OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */
};
wl127x_gpio: pinmux_wl127x_gpio_pin {
pinctrl-single,pins = <
OMAP3_WKUP_IOPAD(0x2a0c, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */
OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
>;
};
@ -260,6 +262,11 @@ &mcspi1 {
#include "twl4030.dtsi"
#include "twl4030_omap3.dtsi"
&vaux3 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
&twl {
twl_power: power {
compatible = "ti,twl4030-power-idle-osc-off", "ti,twl4030-power-idle";

22
arch/arm/boot/dts/r8a7790-lager.dts
View file

@ -379,7 +379,7 @@ ports {
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
remote-endpoint = <&lvds0_out>;
};
};
@ -467,10 +467,8 @@ &du {
status = "okay";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
<&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
"dclkin.0", "dclkin.1";
clock-names = "du.0", "du.1", "du.2", "dclkin.0", "dclkin.1";
ports {
port@0 {
@ -478,12 +476,26 @@ endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
endpoint {
remote-endpoint = <&adv7511_in>;
};
};
port@2 {
};
};
&lvds1 {
status = "okay";
ports {
port@1 {
lvds_connector: endpoint {
};
};

65
arch/arm/boot/dts/r8a7790.dtsi
View file

@ -1627,18 +1627,13 @@ jpu: jpeg-codec@fe980000 {
du: display@feb00000 {
compatible = "renesas,du-r8a7790";
reg = <0 0xfeb00000 0 0x70000>,
<0 0xfeb90000 0 0x1c>,
<0 0xfeb94000 0 0x1c>;
reg-names = "du", "lvds.0", "lvds.1";
reg = <0 0xfeb00000 0 0x70000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>,
<&cpg CPG_MOD 725>;
clock-names = "du.0", "du.1", "du.2", "lvds.0",
"lvds.1";
<&cpg CPG_MOD 722>;
clock-names = "du.0", "du.1", "du.2";
status = "disabled";
ports {
@ -1653,11 +1648,65 @@ du_out_rgb: endpoint {
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>;
};
};
port@2 {
reg = <2>;
du_out_lvds1: endpoint {
remote-endpoint = <&lvds1_in>;
};
};
};
};
lvds0: lvds@feb90000 {
compatible = "renesas,r8a7790-lvds";
reg = <0 0xfeb90000 0 0x1c>;
clocks = <&cpg CPG_MOD 726>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 726>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
lvds1: lvds@feb94000 {
compatible = "renesas,r8a7790-lvds";
reg = <0 0xfeb94000 0 0x1c>;
clocks = <&cpg CPG_MOD 725>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 725>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds1_in: endpoint {
remote-endpoint = <&du_out_lvds1>;
};
};
port@1 {
reg = <1>;
lvds1_out: endpoint {
};
};
};

12
arch/arm/boot/dts/r8a7791-koelsch.dts
View file

@ -468,10 +468,9 @@ &du {
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "lvds.0",
"dclkin.0", "dclkin.1";
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
ports {
port@0 {
@ -479,6 +478,13 @@ endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds_connector: endpoint {
};

16
arch/arm/boot/dts/r8a7791-porter.dts
View file

@ -441,10 +441,9 @@ &du {
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&x3_clk>, <&x16_clk>;
clock-names = "du.0", "du.1", "lvds.0",
"dclkin.0", "dclkin.1";
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
ports {
port@0 {
@ -455,6 +454,17 @@ endpoint {
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds_connector: endpoint {
};
};
};
};
&rcar_sound {
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
pinctrl-names = "default";

36
arch/arm/boot/dts/r8a7791.dtsi
View file

@ -1633,15 +1633,12 @@ jpu: jpeg-codec@fe980000 {
du: display@feb00000 {
compatible = "renesas,du-r8a7791";
reg = <0 0xfeb00000 0 0x40000>,
<0 0xfeb90000 0 0x1c>;
reg-names = "du", "lvds.0";
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 726>;
clock-names = "du.0", "du.1", "lvds.0";
<&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
status = "disabled";
ports {
@ -1656,6 +1653,33 @@ du_out_rgb: endpoint {
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>;
};
};
};
};
lvds0: lvds@feb90000 {
compatible = "renesas,r8a7791-lvds";
reg = <0 0xfeb90000 0 0x1c>;
clocks = <&cpg CPG_MOD 726>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 726>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};

10
arch/arm/boot/dts/r8a7793-gose.dts
View file

@ -447,10 +447,9 @@ &du {
pinctrl-names = "default";
status = "okay";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "lvds.0",
"dclkin.0", "dclkin.1";
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
ports {
port@0 {
@ -458,6 +457,11 @@ endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
&lvds0 {
ports {
port@1 {
lvds_connector: endpoint {
};

37
arch/arm/boot/dts/r8a7793.dtsi
View file

@ -1292,15 +1292,12 @@ gic: interrupt-controller@f1001000 {
du: display@feb00000 {
compatible = "renesas,du-r8a7793";
reg = <0 0xfeb00000 0 0x40000>,
<0 0xfeb90000 0 0x1c>;
reg-names = "du", "lvds.0";
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 726>;
clock-names = "du.0", "du.1", "lvds.0";
<&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
status = "disabled";
ports {
@ -1315,6 +1312,34 @@ du_out_rgb: endpoint {
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>;
};
};
};
};
lvds0: lvds@feb90000 {
compatible = "renesas,r8a7793-lvds";
reg = <0 0xfeb90000 0 0x1c>;
clocks = <&cpg CPG_MOD 726>;
power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
resets = <&cpg 726>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};

2
arch/arm/boot/dts/tegra20.dtsi
View file

@ -741,7 +741,7 @@ phy2: usb-phy@c5004000 {
phy_type = "ulpi";
clocks = <&tegra_car TEGRA20_CLK_USB2>,
<&tegra_car TEGRA20_CLK_PLL_U>,
<&tegra_car TEGRA20_CLK_PLL_P_OUT4>;
<&tegra_car TEGRA20_CLK_CDEV2>;
clock-names = "reg", "pll_u", "ulpi-link";
resets = <&tegra_car 58>, <&tegra_car 22>;
reset-names = "usb", "utmi-pads";

9
arch/arm/mach-davinci/board-da830-evm.c
View file

@ -205,12 +205,17 @@ static const short da830_evm_mmc_sd_pins[] = {
-1
};
#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1)
#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2)
static struct gpiod_lookup_table mmc_gpios_table = {
.dev_id = "da830-mmc.0",
.table = {
/* gpio chip 1 contains gpio range 32-63 */
GPIO_LOOKUP("davinci_gpio.1", 2, "cd", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.1", 1, "wp", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.0", DA830_MMCSD_CD_PIN, "cd",
GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.0", DA830_MMCSD_WP_PIN, "wp",
GPIO_ACTIVE_LOW),
},
};

9
arch/arm/mach-davinci/board-da850-evm.c
View file

@ -763,12 +763,17 @@ static const short da850_evm_mcasp_pins[] __initconst = {
-1
};
#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
static struct gpiod_lookup_table mmc_gpios_table = {
.dev_id = "da830-mmc.0",
.table = {
/* gpio chip 2 contains gpio range 64-95 */
GPIO_LOOKUP("davinci_gpio.2", 0, "cd", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.2", 1, "wp", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_CD_PIN, "cd",
GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_WP_PIN, "wp",
GPIO_ACTIVE_LOW),
},
};

15
arch/arm/mach-davinci/board-dm355-evm.c
View file

@ -19,6 +19,7 @@
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/clk.h>
#include <linux/dm9000.h>
#include <linux/videodev2.h>
#include <media/i2c/tvp514x.h>
#include <linux/spi/spi.h>
@ -109,12 +110,15 @@ static struct platform_device davinci_nand_device = {
},
};
#define DM355_I2C_SDA_PIN GPIO_TO_PIN(0, 15)
#define DM355_I2C_SCL_PIN GPIO_TO_PIN(0, 14)
static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
.dev_id = "i2c_davinci",
.dev_id = "i2c_davinci.1",
.table = {
GPIO_LOOKUP("davinci_gpio", 15, "sda",
GPIO_LOOKUP("davinci_gpio.0", DM355_I2C_SDA_PIN, "sda",
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
GPIO_LOOKUP("davinci_gpio", 14, "scl",
GPIO_LOOKUP("davinci_gpio.0", DM355_I2C_SCL_PIN, "scl",
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
},
};
@ -179,11 +183,16 @@ static struct resource dm355evm_dm9000_rsrc[] = {
},
};
static struct dm9000_plat_data dm335evm_dm9000_platdata;
static struct platform_device dm355evm_dm9000 = {
.name = "dm9000",
.id = -1,
.resource = dm355evm_dm9000_rsrc,
.num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc),
.dev = {
.platform_data = &dm335evm_dm9000_platdata,
},
};
static struct tvp514x_platform_data tvp5146_pdata = {

10
arch/arm/mach-davinci/board-dm644x-evm.c
View file

@ -17,6 +17,7 @@
#include <linux/i2c.h>
#include <linux/platform_data/pcf857x.h>
#include <linux/platform_data/at24.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
@ -596,12 +597,15 @@ static struct i2c_board_info __initdata i2c_info[] = {
},
};
#define DM644X_I2C_SDA_PIN GPIO_TO_PIN(2, 12)
#define DM644X_I2C_SCL_PIN GPIO_TO_PIN(2, 11)
static struct gpiod_lookup_table i2c_recovery_gpiod_table = {
.dev_id = "i2c_davinci",
.dev_id = "i2c_davinci.1",
.table = {
GPIO_LOOKUP("davinci_gpio", 44, "sda",
GPIO_LOOKUP("davinci_gpio.0", DM644X_I2C_SDA_PIN, "sda",
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
GPIO_LOOKUP("davinci_gpio", 43, "scl",
GPIO_LOOKUP("davinci_gpio.0", DM644X_I2C_SCL_PIN, "scl",
GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
},
};

5
arch/arm/mach-davinci/board-dm646x-evm.c
View file

@ -532,11 +532,12 @@ static struct vpif_display_config dm646x_vpif_display_config = {
.set_clock = set_vpif_clock,
.subdevinfo = dm646x_vpif_subdev,
.subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
.i2c_adapter_id = 1,
.chan_config[0] = {
.outputs = dm6467_ch0_outputs,
.output_count = ARRAY_SIZE(dm6467_ch0_outputs),
},
.card_name = "DM646x EVM",
.card_name = "DM646x EVM Video Display",
};
/**
@ -674,6 +675,7 @@ static struct vpif_capture_config dm646x_vpif_capture_cfg = {
.setup_input_channel_mode = setup_vpif_input_channel_mode,
.subdev_info = vpif_capture_sdev_info,
.subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
.i2c_adapter_id = 1,
.chan_config[0] = {
.inputs = dm6467_ch0_inputs,
.input_count = ARRAY_SIZE(dm6467_ch0_inputs),
@ -694,6 +696,7 @@ static struct vpif_capture_config dm646x_vpif_capture_cfg = {
.fid_pol = 0,
},
},
.card_name = "DM646x EVM Video Capture",
};
static void __init evm_init_video(void)

10
arch/arm/mach-davinci/board-omapl138-hawk.c
View file

@ -123,12 +123,16 @@ static const short hawk_mmcsd0_pins[] = {
-1
};
#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12)
#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13)
static struct gpiod_lookup_table mmc_gpios_table = {
.dev_id = "da830-mmc.0",
.table = {
/* CD: gpio3_12: gpio60: chip 1 contains gpio range 32-63*/
GPIO_LOOKUP("davinci_gpio.0", 28, "cd", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.0", 29, "wp", GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.0", DA850_HAWK_MMCSD_CD_PIN, "cd",
GPIO_ACTIVE_LOW),
GPIO_LOOKUP("davinci_gpio.0", DA850_HAWK_MMCSD_WP_PIN, "wp",
GPIO_ACTIVE_LOW),
},
};

3
arch/arm/mach-davinci/dm646x.c
View file

@ -488,7 +488,8 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
[IRQ_DM646X_MCASP0TXINT] = 7,
[IRQ_DM646X_MCASP0RXINT] = 7,
[IRQ_DM646X_RESERVED_3] = 7,
[IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
[IRQ_DM646X_MCASP1TXINT] = 7,
[IRQ_TINT0_TINT12] = 7, /* clockevent */
[IRQ_TINT0_TINT34] = 7, /* clocksource */
[IRQ_TINT1_TINT12] = 7, /* DSP timer */
[IRQ_TINT1_TINT34] = 7, /* system tick */

1
arch/arm/mach-keystone/pm_domain.c
View file

@ -29,6 +29,7 @@ static struct dev_pm_domain keystone_pm_domain = {
static struct pm_clk_notifier_block platform_domain_notifier = {
.pm_domain = &keystone_pm_domain,
.con_ids = { NULL },
};
static const struct of_device_id of_keystone_table[] = {

26
arch/arm/mach-omap1/ams-delta-fiq.c
View file

@ -58,22 +58,24 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id)
irq_num = gpio_to_irq(gpio);
fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];
while (irq_counter[gpio] < fiq_count) {
if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
struct irq_data *d = irq_get_irq_data(irq_num);
if (irq_counter[gpio] < fiq_count &&
gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
struct irq_data *d = irq_get_irq_data(irq_num);
/*
* It looks like handle_edge_irq() that
* OMAP GPIO edge interrupts default to,
* expects interrupt already unmasked.
*/
if (irq_chip && irq_chip->irq_unmask)
/*
* handle_simple_irq() that OMAP GPIO edge
* interrupts default to since commit 80ac93c27441
* requires interrupt already acked and unmasked.
*/
if (irq_chip) {
if (irq_chip->irq_ack)
irq_chip->irq_ack(d);
if (irq_chip->irq_unmask)
irq_chip->irq_unmask(d);
}
generic_handle_irq(irq_num);
irq_counter[gpio]++;
}
for (; irq_counter[gpio] < fiq_count; irq_counter[gpio]++)
generic_handle_irq(irq_num);
}
return IRQ_HANDLED;
}

4
arch/arm/mach-omap2/powerdomain.c
View file

@ -188,7 +188,7 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
((prev & OMAP_POWERSTATE_MASK) << 0));
trace_power_domain_target_rcuidle(pwrdm->name,
trace_state,
smp_processor_id());
raw_smp_processor_id());
}
break;
default:
@ -518,7 +518,7 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
/* Trace the pwrdm desired target state */
trace_power_domain_target_rcuidle(pwrdm->name, pwrst,
smp_processor_id());
raw_smp_processor_id());
/* Program the pwrdm desired target state */
ret = arch_pwrdm->pwrdm_set_next_pwrst(pwrdm, pwrst);
}

2
arch/arm64/boot/dts/exynos/exynos5433.dtsi
View file

@ -1317,7 +1317,7 @@ i2s1: i2s@14d60000 {
reg = <0x14d60000 0x100>;
dmas = <&pdma0 31 &pdma0 30>;
dma-names = "tx", "rx";
interrupts = <GIC_SPI 435 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_peric CLK_PCLK_I2S1>,
<&cmu_peric CLK_PCLK_I2S1>,
<&cmu_peric CLK_SCLK_I2S1>;

7
arch/arm64/boot/dts/marvell/armada-cp110.dtsi
View file

@ -38,9 +38,10 @@ CP110_LABEL(ethernet): ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
<&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 18>;
<&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
<&CP110_LABEL(clk) 1 18>;
clock-names = "pp_clk", "gop_clk",
"mg_clk", "axi_clk";
"mg_clk", "mg_core_clk", "axi_clk";
marvell,system-controller = <&CP110_LABEL(syscon0)>;
status = "disabled";
dma-coherent;
@ -141,6 +142,8 @@ CP110_LABEL(xmdio): mdio@12a600 {
#size-cells = <0>;
compatible = "marvell,xmdio";
reg = <0x12a600 0x10>;
clocks = <&CP110_LABEL(clk) 1 5>,
<&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
status = "disabled";
};

2
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
View file

@ -46,7 +46,7 @@ phy: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_MAIN_GPIO(M, 5) IRQ_TYPE_LEVEL_HIGH>;
interrupts = <TEGRA_MAIN_GPIO(M, 5) IRQ_TYPE_LEVEL_LOW>;
};
};
};

2
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
View file

@ -414,7 +414,7 @@ emmc: sdhc@5a000000 {
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-legacy = <9>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
cdns,phy-dll-delay-sdclk = <21>;

8
arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
View file

@ -67,3 +67,11 @@ ethphy: ethphy@0 {
reg = <0>;
};
};
&pinctrl_ether_rgmii {
tx {
pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1",
"RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL";
drive-strength = <9>;
};
};

2
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
View file

@ -519,7 +519,7 @@ emmc: sdhc@5a000000 {
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-legacy = <9>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
cdns,phy-dll-delay-sdclk = <21>;

2
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
View file

@ -334,7 +334,7 @@ emmc: sdhc@5a000000 {
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-pwrseq = <&emmc_pwrseq>;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-legacy = <9>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
cdns,phy-dll-delay-sdclk = <21>;

1
drivers/firmware/arm_scmi/driver.c
View file

@ -778,6 +778,7 @@ scmi_create_protocol_device(struct device_node *np, struct scmi_info *info,
if (scmi_mbox_chan_setup(info, &sdev->dev, prot_id)) {
dev_err(&sdev->dev, "failed to setup transport\n");
scmi_device_destroy(sdev);
return;
}
/* setup handle now as the transport is ready */

6
drivers/reset/reset-uniphier.c
View file

@ -110,7 +110,7 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */
UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC) */
UNIPHIER_RESETX(12, 0x200c, 5), /* GIO (PCIe, USB3) */
UNIPHIER_RESETX(14, 0x200c, 5), /* USB30 */
UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
@ -127,8 +127,8 @@ static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
UNIPHIER_RESETX(6, 0x200c, 9), /* Ether0 */
UNIPHIER_RESETX(7, 0x200c, 10), /* Ether1 */
UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */
UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link (GIO0) */
UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link (GIO1) */
UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link */
UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link */
UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */
UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */
UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */

11
drivers/tee/tee_core.c
View file

@ -238,6 +238,17 @@ static int params_from_user(struct tee_context *ctx, struct tee_param *params,
if (IS_ERR(shm))
return PTR_ERR(shm);
/*
* Ensure offset + size does not overflow offset
* and does not overflow the size of the referred
* shared memory object.
*/
if ((ip.a + ip.b) < ip.a ||
(ip.a + ip.b) > shm->size) {
tee_shm_put(shm);
return -EINVAL;
}
params[n].u.memref.shm_offs = ip.a;
params[n].u.memref.size = ip.b;
params[n].u.memref.shm = shm;

5
drivers/tee/tee_shm.c
View file

@ -360,9 +360,10 @@ int tee_shm_get_fd(struct tee_shm *shm)
if (!(shm->flags & TEE_SHM_DMA_BUF))
return -EINVAL;
get_dma_buf(shm->dmabuf);
fd = dma_buf_fd(shm->dmabuf, O_CLOEXEC);
if (fd >= 0)
get_dma_buf(shm->dmabuf);
if (fd < 0)
dma_buf_put(shm->dmabuf);
return fd;
}