Qualcomm driver updates for 5.13
This introduces SC7280 and SM8350 support in the RPMH power-domain driver, SC7280 support to the LLCC driver, SC7280 support tot he AOSS QMP driver, cleanups to the RPMH driver and a few smaller fixes to the SMEM, QMI and EBI2 drivers. -----BEGIN PGP SIGNATURE----- iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmBp5LYbHGJqb3JuLmFu ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FHBQP/08HEI7gyfrNkGHq0cMr F0tDl0wUyh06meEnBT4G9O2Pzuu2vPUxUACEW1EwB61Qo/0Rin9pscSceNLYa7ul BSevZKYbMu4yTylTkSTZIy9bIuTmOlcc7krk4MDpl/c8HzuGgILhm9nSTTv7pYfE JLtoUdoZS77ToSsv8WVaAinslQKTA4j/YoZ6EKDcTxWw9L6IzkGphfo3p/8Bs3l/ y4iU87INu+oiINJF5TeLncB5VEBGQIDzBwIf/4R67bZ+lQiRVfPFmg44y/R7NK1f NwJB8Ty2oCV1on62yJ93S5YhecJjzedhcIzyn5hsULKUHQT89fneFxVngK2LHTrC l+aZLpH6MwC+9qAce5utmlfFFRKpzMtqnXnpexq8fT+EXt4wAnwDacOPcHDDblcS zskyTGPGvyt54m3UwS9DOJy3Ed9NJL2D1Xmfonx94H9G8hkFyVBEOMXuegh0Sgtf eYGjrYew3ajGiQeC5SaGMkd80CrLN4uUizPt9O6yHETeoQKzE4EluFkaLVlvgbEj eauNu6uSiN/ESUc2LvkKN4pmPBspkTh/CyDArV+15IlE/AcSNgSeylxF1lXzo335 Msl0+3tKpW+i6AASdD8b74f6kV72VdaVflrI3rmacSwCkWP1bvO/1cWBeFzs0S+W FtpgLl7nyng7tdMo/9FbeKkE =sgiW -----END PGP SIGNATURE----- Merge tag 'qcom-drivers-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers Qualcomm driver updates for 5.13 This introduces SC7280 and SM8350 support in the RPMH power-domain driver, SC7280 support to the LLCC driver, SC7280 support tot he AOSS QMP driver, cleanups to the RPMH driver and a few smaller fixes to the SMEM, QMI and EBI2 drivers. * tag 'qcom-drivers-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: bus: qcom: Put child node before return dt-bindings: firmware: scm: Add sc7280 support soc: qcom: rpmh-rsc: Fold WARN_ON() into if condition soc: qcom: rpmh-rsc: Loop over fewer bits in irq handler soc: qcom: rpmh-rsc: Remove tcs_is_free() API soc: qcom: smem: Update max processor count soc: qcom: aoss: Add AOSS QMP support for SC7280 dt-bindings: soc: qcom: aoss: Add SC7280 compatible soc: qcom: llcc: Add configuration data for SC7280 dt-bindings: arm: msm: Add LLCC for SC7280 soc: qcom: Fix typos in the file qmi_encdec.c soc: qcom: rpmhpd: Add sc7280 powerdomains dt-bindings: power: rpmpd: Add sc7280 to rpmpd binding soc: qcom: rpmhpd: Add SM8350 power domains dt-bindings: power: Add rpm power domain bindings for SM8350 Link: https://lore.kernel.org/r/20210404164951.713045-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
207481077b
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@ -22,6 +22,7 @@ properties:
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compatible:
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enum:
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- qcom,sc7180-llcc
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- qcom,sc7280-llcc
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- qcom,sdm845-llcc
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- qcom,sm8150-llcc
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- qcom,sm8250-llcc
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@ -20,6 +20,7 @@ Required properties:
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* "qcom,scm-msm8996"
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* "qcom,scm-msm8998"
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* "qcom,scm-sc7180"
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* "qcom,scm-sc7280"
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* "qcom,scm-sdm845"
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* "qcom,scm-sm8150"
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* "qcom,scm-sm8250"
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@ -25,10 +25,12 @@ properties:
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- qcom,qcs404-rpmpd
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- qcom,sdm660-rpmpd
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- qcom,sc7180-rpmhpd
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- qcom,sc7280-rpmhpd
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- qcom,sdm845-rpmhpd
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- qcom,sdx55-rpmhpd
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- qcom,sm8150-rpmhpd
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- qcom,sm8250-rpmhpd
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- qcom,sm8350-rpmhpd
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'#power-domain-cells':
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const: 1
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@ -17,6 +17,7 @@ power-domains.
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Value type: <string>
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Definition: must be one of:
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"qcom,sc7180-aoss-qmp"
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"qcom,sc7280-aoss-qmp"
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"qcom,sdm845-aoss-qmp"
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"qcom,sm8150-aoss-qmp"
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"qcom,sm8250-aoss-qmp"
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@ -353,8 +353,10 @@ static int qcom_ebi2_probe(struct platform_device *pdev)
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/* Figure out the chipselect */
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ret = of_property_read_u32(child, "reg", &csindex);
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if (ret)
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if (ret) {
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of_node_put(child);
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return ret;
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}
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if (csindex > 5) {
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dev_err(dev,
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@ -109,6 +109,18 @@ static const struct llcc_slice_config sc7180_data[] = {
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{ LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
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};
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static const struct llcc_slice_config sc7280_data[] = {
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{ LLCC_CPUSS, 1, 768, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 1, 0},
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{ LLCC_MDMHPGRW, 7, 512, 2, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
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{ LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
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{ LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
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{ LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
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{ LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 1, 0},
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{ LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
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{ LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
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{ LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0},
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};
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static const struct llcc_slice_config sdm845_data[] = {
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{ LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 },
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{ LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
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@ -179,6 +191,12 @@ static const struct qcom_llcc_config sc7180_cfg = {
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.need_llcc_cfg = true,
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};
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static const struct qcom_llcc_config sc7280_cfg = {
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.sct_data = sc7280_data,
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.size = ARRAY_SIZE(sc7280_data),
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.need_llcc_cfg = true,
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};
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static const struct qcom_llcc_config sdm845_cfg = {
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.sct_data = sdm845_data,
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.size = ARRAY_SIZE(sdm845_data),
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@ -606,6 +624,7 @@ err:
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static const struct of_device_id qcom_llcc_of_match[] = {
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{ .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
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{ .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg },
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{ .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
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{ .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg },
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{ .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg },
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@ -597,6 +597,7 @@ static int qmp_remove(struct platform_device *pdev)
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static const struct of_device_id qmp_dt_match[] = {
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{ .compatible = "qcom,sc7180-aoss-qmp", },
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{ .compatible = "qcom,sc7280-aoss-qmp", },
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{ .compatible = "qcom,sdm845-aoss-qmp", },
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{ .compatible = "qcom,sm8150-aoss-qmp", },
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{ .compatible = "qcom,sm8250-aoss-qmp", },
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@ -451,11 +451,11 @@ static int qmi_decode_basic_elem(void *buf_dst, const void *buf_src,
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/**
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* qmi_decode_struct_elem() - Decodes elements of struct data type
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* @ei_array: Struct info array descibing the struct element.
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* @ei_array: Struct info array describing the struct element.
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* @buf_dst: Buffer to store the decoded element.
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* @buf_src: Buffer containing the elements in QMI wire format.
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* @elem_len: Number of elements to be decoded.
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* @tlv_len: Total size of the encoded inforation corresponding to
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* @tlv_len: Total size of the encoded information corresponding to
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* this struct element.
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* @dec_level: Depth of the nested structure from the main structure.
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*
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@ -499,10 +499,10 @@ static int qmi_decode_struct_elem(struct qmi_elem_info *ei_array,
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/**
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* qmi_decode_string_elem() - Decodes elements of string data type
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* @ei_array: Struct info array descibing the string element.
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* @ei_array: Struct info array describing the string element.
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* @buf_dst: Buffer to store the decoded element.
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* @buf_src: Buffer containing the elements in QMI wire format.
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* @tlv_len: Total size of the encoded inforation corresponding to
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* @tlv_len: Total size of the encoded information corresponding to
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* this string element.
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* @dec_level: Depth of the string element from the main structure.
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*
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@ -194,22 +194,6 @@ static void write_tcs_reg_sync(const struct rsc_drv *drv, int reg, int tcs_id,
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data, tcs_id, reg);
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}
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/**
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* tcs_is_free() - Return if a TCS is totally free.
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* @drv: The RSC controller.
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* @tcs_id: The global ID of this TCS.
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*
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* Returns true if nobody has claimed this TCS (by setting tcs_in_use).
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*
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* Context: Must be called with the drv->lock held.
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*
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* Return: true if the given TCS is free.
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*/
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static bool tcs_is_free(struct rsc_drv *drv, int tcs_id)
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{
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return !test_bit(tcs_id, drv->tcs_in_use);
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}
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/**
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* tcs_invalidate() - Invalidate all TCSes of the given type (sleep or wake).
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* @drv: The RSC controller.
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@ -408,12 +392,10 @@ static irqreturn_t tcs_tx_done(int irq, void *p)
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irq_status = readl_relaxed(drv->tcs_base + RSC_DRV_IRQ_STATUS);
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for_each_set_bit(i, &irq_status, BITS_PER_LONG) {
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for_each_set_bit(i, &irq_status, BITS_PER_TYPE(u32)) {
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req = get_req_from_tcs(drv, i);
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if (!req) {
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WARN_ON(1);
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if (WARN_ON(!req))
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goto skip;
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}
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err = 0;
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for (j = 0; j < req->num_cmds; j++) {
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@ -520,7 +502,7 @@ static void __tcs_buffer_write(struct rsc_drv *drv, int tcs_id, int cmd_id,
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*
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* Return: 0 if nothing in flight or -EBUSY if we should try again later.
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* The caller must re-enable interrupts between tries since that's
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* the only way tcs_is_free() will ever return true and the only way
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* the only way tcs_in_use will ever be updated and the only way
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* RSC_DRV_CMD_ENABLE will ever be cleared.
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*/
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static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs,
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@ -528,17 +510,14 @@ static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs,
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{
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unsigned long curr_enabled;
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u32 addr;
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int i, j, k;
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int tcs_id = tcs->offset;
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int j, k;
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int i = tcs->offset;
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for (i = 0; i < tcs->num_tcs; i++, tcs_id++) {
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if (tcs_is_free(drv, tcs_id))
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continue;
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curr_enabled = read_tcs_reg(drv, RSC_DRV_CMD_ENABLE, tcs_id);
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for_each_set_bit_from(i, drv->tcs_in_use, tcs->offset + tcs->num_tcs) {
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curr_enabled = read_tcs_reg(drv, RSC_DRV_CMD_ENABLE, i);
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for_each_set_bit(j, &curr_enabled, MAX_CMDS_PER_TCS) {
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addr = read_tcs_cmd(drv, RSC_DRV_CMD_ADDR, tcs_id, j);
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addr = read_tcs_cmd(drv, RSC_DRV_CMD_ADDR, i, j);
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for (k = 0; k < msg->num_cmds; k++) {
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if (addr == msg->cmds[k].addr)
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return -EBUSY;
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@ -556,18 +535,19 @@ static int check_for_req_inflight(struct rsc_drv *drv, struct tcs_group *tcs,
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*
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* Must be called with the drv->lock held since that protects tcs_in_use.
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*
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* Return: The first tcs that's free.
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* Return: The first tcs that's free or -EBUSY if all in use.
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*/
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static int find_free_tcs(struct tcs_group *tcs)
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{
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int i;
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const struct rsc_drv *drv = tcs->drv;
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unsigned long i;
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unsigned long max = tcs->offset + tcs->num_tcs;
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for (i = 0; i < tcs->num_tcs; i++) {
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if (tcs_is_free(tcs->drv, tcs->offset + i))
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return tcs->offset + i;
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}
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i = find_next_zero_bit(drv->tcs_in_use, max, tcs->offset);
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if (i >= max)
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return -EBUSY;
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return -EBUSY;
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return i;
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}
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/**
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@ -754,8 +734,9 @@ int rpmh_rsc_write_ctrl_data(struct rsc_drv *drv, const struct tcs_request *msg)
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*/
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static bool rpmh_rsc_ctrlr_is_busy(struct rsc_drv *drv)
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{
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int m;
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struct tcs_group *tcs = &drv->tcs[ACTIVE_TCS];
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unsigned long set;
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const struct tcs_group *tcs = &drv->tcs[ACTIVE_TCS];
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unsigned long max;
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/*
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* If we made an active request on a RSC that does not have a
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@ -766,12 +747,10 @@ static bool rpmh_rsc_ctrlr_is_busy(struct rsc_drv *drv)
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if (!tcs->num_tcs)
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tcs = &drv->tcs[WAKE_TCS];
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for (m = tcs->offset; m < tcs->offset + tcs->num_tcs; m++) {
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if (!tcs_is_free(drv, m))
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return true;
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}
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max = tcs->offset + tcs->num_tcs;
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set = find_next_bit(drv->tcs_in_use, max, tcs->offset);
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return false;
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return set < max;
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}
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/**
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@ -200,6 +200,42 @@ static const struct rpmhpd_desc sm8250_desc = {
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.num_pds = ARRAY_SIZE(sm8250_rpmhpds),
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};
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/* SM8350 Power domains */
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static struct rpmhpd sm8350_mxc_ao;
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static struct rpmhpd sm8350_mxc = {
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.pd = { .name = "mxc", },
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.peer = &sm8150_mmcx_ao,
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.res_name = "mxc.lvl",
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};
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static struct rpmhpd sm8350_mxc_ao = {
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.pd = { .name = "mxc_ao", },
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.active_only = true,
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.peer = &sm8350_mxc,
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.res_name = "mxc.lvl",
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};
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static struct rpmhpd *sm8350_rpmhpds[] = {
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[SM8350_CX] = &sdm845_cx,
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[SM8350_CX_AO] = &sdm845_cx_ao,
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[SM8350_EBI] = &sdm845_ebi,
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[SM8350_GFX] = &sdm845_gfx,
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[SM8350_LCX] = &sdm845_lcx,
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[SM8350_LMX] = &sdm845_lmx,
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[SM8350_MMCX] = &sm8150_mmcx,
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[SM8350_MMCX_AO] = &sm8150_mmcx_ao,
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[SM8350_MX] = &sdm845_mx,
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[SM8350_MX_AO] = &sdm845_mx_ao,
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[SM8350_MXC] = &sm8350_mxc,
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[SM8350_MXC_AO] = &sm8350_mxc_ao,
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[SM8350_MSS] = &sdm845_mss,
|
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};
|
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|
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static const struct rpmhpd_desc sm8350_desc = {
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.rpmhpds = sm8350_rpmhpds,
|
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.num_pds = ARRAY_SIZE(sm8350_rpmhpds),
|
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};
|
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|
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/* SC7180 RPMH powerdomains */
|
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static struct rpmhpd *sc7180_rpmhpds[] = {
|
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[SC7180_CX] = &sdm845_cx,
|
||||
|
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@ -217,12 +253,32 @@ static const struct rpmhpd_desc sc7180_desc = {
|
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.num_pds = ARRAY_SIZE(sc7180_rpmhpds),
|
||||
};
|
||||
|
||||
/* SC7280 RPMH powerdomains */
|
||||
static struct rpmhpd *sc7280_rpmhpds[] = {
|
||||
[SC7280_CX] = &sdm845_cx,
|
||||
[SC7280_CX_AO] = &sdm845_cx_ao,
|
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[SC7280_EBI] = &sdm845_ebi,
|
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[SC7280_GFX] = &sdm845_gfx,
|
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[SC7280_MX] = &sdm845_mx,
|
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[SC7280_MX_AO] = &sdm845_mx_ao,
|
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[SC7280_LMX] = &sdm845_lmx,
|
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[SC7280_LCX] = &sdm845_lcx,
|
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[SC7280_MSS] = &sdm845_mss,
|
||||
};
|
||||
|
||||
static const struct rpmhpd_desc sc7280_desc = {
|
||||
.rpmhpds = sc7280_rpmhpds,
|
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.num_pds = ARRAY_SIZE(sc7280_rpmhpds),
|
||||
};
|
||||
|
||||
static const struct of_device_id rpmhpd_match_table[] = {
|
||||
{ .compatible = "qcom,sc7180-rpmhpd", .data = &sc7180_desc },
|
||||
{ .compatible = "qcom,sc7280-rpmhpd", .data = &sc7280_desc },
|
||||
{ .compatible = "qcom,sdm845-rpmhpd", .data = &sdm845_desc },
|
||||
{ .compatible = "qcom,sdx55-rpmhpd", .data = &sdx55_desc},
|
||||
{ .compatible = "qcom,sm8150-rpmhpd", .data = &sm8150_desc },
|
||||
{ .compatible = "qcom,sm8250-rpmhpd", .data = &sm8250_desc },
|
||||
{ .compatible = "qcom,sm8350-rpmhpd", .data = &sm8350_desc },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rpmhpd_match_table);
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@
|
|||
#define SMEM_GLOBAL_HOST 0xfffe
|
||||
|
||||
/* Max number of processors/hosts in a system */
|
||||
#define SMEM_HOST_COUNT 11
|
||||
#define SMEM_HOST_COUNT 14
|
||||
|
||||
/**
|
||||
* struct smem_proc_comm - proc_comm communication struct (legacy)
|
||||
|
|
|
|||
|
|
@ -45,6 +45,21 @@
|
|||
#define SM8250_MX 8
|
||||
#define SM8250_MX_AO 9
|
||||
|
||||
/* SM8350 Power Domain Indexes */
|
||||
#define SM8350_CX 0
|
||||
#define SM8350_CX_AO 1
|
||||
#define SM8350_EBI 2
|
||||
#define SM8350_GFX 3
|
||||
#define SM8350_LCX 4
|
||||
#define SM8350_LMX 5
|
||||
#define SM8350_MMCX 6
|
||||
#define SM8350_MMCX_AO 7
|
||||
#define SM8350_MX 8
|
||||
#define SM8350_MX_AO 9
|
||||
#define SM8350_MXC 10
|
||||
#define SM8350_MXC_AO 11
|
||||
#define SM8350_MSS 12
|
||||
|
||||
/* SC7180 Power Domain Indexes */
|
||||
#define SC7180_CX 0
|
||||
#define SC7180_CX_AO 1
|
||||
|
|
@ -55,6 +70,17 @@
|
|||
#define SC7180_LCX 6
|
||||
#define SC7180_MSS 7
|
||||
|
||||
/* SC7280 Power Domain Indexes */
|
||||
#define SC7280_CX 0
|
||||
#define SC7280_CX_AO 1
|
||||
#define SC7280_EBI 2
|
||||
#define SC7280_GFX 3
|
||||
#define SC7280_MX 4
|
||||
#define SC7280_MX_AO 5
|
||||
#define SC7280_LMX 6
|
||||
#define SC7280_LCX 7
|
||||
#define SC7280_MSS 8
|
||||
|
||||
/* SDM845 Power Domain performance levels */
|
||||
#define RPMH_REGULATOR_LEVEL_RETENTION 16
|
||||
#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
|
||||
|
|
|
|||
Loading…
Reference in New Issue