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dmaengine: zxdma: Fix data width bug
Align src and dst width to fix data alignment issue as trailing single transaction that does not fill a full burst require identical src/dst data width. Burst length limitation can be addressed well too. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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2f2560e348
commit
2092539b77
1 changed files with 5 additions and 4 deletions
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@ -476,15 +476,16 @@ static int zx_pre_config(struct zx_dma_chan *c, enum dma_transfer_direction dir)
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c->dev_addr = cfg->dst_addr;
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/* dst len is calculated from src width, len and dst width.
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* We need make sure dst len not exceed MAX LEN.
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* Trailing single transaction that does not fill a full
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* burst also require identical src/dst data width.
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*/
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dst_width = zx_dma_burst_width(cfg->dst_addr_width);
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maxburst = cfg->dst_maxburst * cfg->dst_addr_width
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/ DMA_SLAVE_BUSWIDTH_8_BYTES;
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maxburst = cfg->dst_maxburst;
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maxburst = maxburst < ZX_MAX_BURST_LEN ?
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maxburst : ZX_MAX_BURST_LEN;
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c->ccfg = ZX_DST_FIFO_MODE | ZX_CH_ENABLE
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| ZX_SRC_BURST_LEN(maxburst - 1)
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| ZX_SRC_BURST_WIDTH(ZX_DMA_WIDTH_64BIT)
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| ZX_SRC_BURST_WIDTH(dst_width)
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| ZX_DST_BURST_WIDTH(dst_width);
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break;
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case DMA_DEV_TO_MEM:
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@ -496,7 +497,7 @@ static int zx_pre_config(struct zx_dma_chan *c, enum dma_transfer_direction dir)
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c->ccfg = ZX_SRC_FIFO_MODE | ZX_CH_ENABLE
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| ZX_SRC_BURST_LEN(maxburst - 1)
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| ZX_SRC_BURST_WIDTH(src_width)
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| ZX_DST_BURST_WIDTH(ZX_DMA_WIDTH_64BIT);
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| ZX_DST_BURST_WIDTH(src_width);
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break;
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default:
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return -EINVAL;
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