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media: staging: atomisp: Remove dead code for MID (#4)
Since we switched to upstream IOSF MBI API the custom code become not in use anymore. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
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4 changed files with 0 additions and 122 deletions
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@ -1,22 +0,0 @@
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/*
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* Access to message bus through three registers
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* in CUNIT(0:0:0) PCI configuration space.
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* MSGBUS_CTRL_REG(0xD0):
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* 31:24 = message bus opcode
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* 23:16 = message bus port
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* 15:8 = message bus address, low 8 bits.
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* 7:4 = message bus byte enables
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* MSGBUS_CTRL_EXT_REG(0xD8):
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* 31:8 = message bus address, high 24 bits.
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* MSGBUS_DATA_REG(0xD4):
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* hold the data for write or read
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*/
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#define PCI_ROOT_MSGBUS_CTRL_REG 0xD0
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#define PCI_ROOT_MSGBUS_DATA_REG 0xD4
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#define PCI_ROOT_MSGBUS_CTRL_EXT_REG 0xD8
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#define PCI_ROOT_MSGBUS_READ 0x10
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#define PCI_ROOT_MSGBUS_WRITE 0x11
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#define PCI_ROOT_MSGBUS_DWORD_ENABLE 0xf0
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u32 intel_mid_msgbus_read32(u8 port, u32 addr);
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void intel_mid_msgbus_write32(u8 port, u32 addr, u32 data);
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@ -30,7 +30,6 @@
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#include <linux/idr.h>
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#include <asm/intel-mid.h>
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#include "../../include/asm/intel_mid_pcihelpers.h"
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#include <media/media-device.h>
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#include <media/v4l2-subdev.h>
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@ -1,5 +1,4 @@
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#
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# Makefile for intel-mid devices.
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#
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obj-$(CONFIG_INTEL_ATOMISP) += intel_mid_pcihelpers.o
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obj-$(CONFIG_INTEL_ATOMISP) += atomisp_gmin_platform.o
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@ -1,98 +0,0 @@
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#include <linux/export.h>
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#include <linux/pci.h>
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#include <linux/pm_qos.h>
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#include <linux/delay.h>
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/* G-Min addition: "platform_is()" lives in intel_mid_pm.h in the MCG
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* tree, but it's just platform ID info and we don't want to pull in
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* the whole SFI-based PM architecture.
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*/
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#define INTEL_ATOM_MRST 0x26
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#define INTEL_ATOM_MFLD 0x27
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#define INTEL_ATOM_CLV 0x35
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#define INTEL_ATOM_MRFLD 0x4a
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#define INTEL_ATOM_BYT 0x37
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#define INTEL_ATOM_MOORFLD 0x5a
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#define INTEL_ATOM_CHT 0x4c
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static inline int platform_is(u8 model)
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{
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return (boot_cpu_data.x86_model == model);
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}
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#include "../../include/asm/intel_mid_pcihelpers.h"
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/* Unified message bus read/write operation */
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static DEFINE_SPINLOCK(msgbus_lock);
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static struct pci_dev *pci_root;
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static struct pm_qos_request pm_qos;
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#define DW_I2C_NEED_QOS (platform_is(INTEL_ATOM_BYT))
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static int intel_mid_msgbus_init(void)
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{
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pci_root = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
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if (!pci_root) {
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pr_err("%s: Error: msgbus PCI handle NULL\n", __func__);
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return -ENODEV;
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}
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if (DW_I2C_NEED_QOS) {
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pm_qos_add_request(&pm_qos,
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PM_QOS_CPU_DMA_LATENCY,
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PM_QOS_DEFAULT_VALUE);
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}
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return 0;
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}
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fs_initcall(intel_mid_msgbus_init);
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u32 intel_mid_msgbus_read32(u8 port, u32 addr)
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{
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unsigned long irq_flags;
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u32 data;
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u32 cmd;
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u32 cmdext;
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cmd = (PCI_ROOT_MSGBUS_READ << 24) | (port << 16) |
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((addr & 0xff) << 8) | PCI_ROOT_MSGBUS_DWORD_ENABLE;
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cmdext = addr & 0xffffff00;
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spin_lock_irqsave(&msgbus_lock, irq_flags);
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if (cmdext) {
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/* This resets to 0 automatically, no need to write 0 */
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pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_EXT_REG,
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cmdext);
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}
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pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_REG, cmd);
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pci_read_config_dword(pci_root, PCI_ROOT_MSGBUS_DATA_REG, &data);
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spin_unlock_irqrestore(&msgbus_lock, irq_flags);
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return data;
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}
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EXPORT_SYMBOL(intel_mid_msgbus_read32);
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void intel_mid_msgbus_write32(u8 port, u32 addr, u32 data)
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{
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unsigned long irq_flags;
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u32 cmd;
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u32 cmdext;
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cmd = (PCI_ROOT_MSGBUS_WRITE << 24) | (port << 16) |
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((addr & 0xFF) << 8) | PCI_ROOT_MSGBUS_DWORD_ENABLE;
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cmdext = addr & 0xffffff00;
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spin_lock_irqsave(&msgbus_lock, irq_flags);
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pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_DATA_REG, data);
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if (cmdext) {
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/* This resets to 0 automatically, no need to write 0 */
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pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_EXT_REG,
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cmdext);
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}
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pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_REG, cmd);
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spin_unlock_irqrestore(&msgbus_lock, irq_flags);
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}
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EXPORT_SYMBOL(intel_mid_msgbus_write32);
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