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mtd: fsl_ifc_nand: set NAND_NO_SUBPAGE_WRITE
This controller only does ECC on full-page accesses, even though the ECC consists of multiple steps. fsl_elbc_nand can get away with this because the ECC of an all-0xff region will be all-0xff, but this is not true with the ECC algorithms used by IFC. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -823,7 +823,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
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/* set up nand options */
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chip->bbt_options = NAND_BBT_USE_FLASH;
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chip->options = NAND_NO_SUBPAGE_WRITE;
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if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
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chip->read_byte = fsl_ifc_read_byte16;
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