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powerpc/perf: Fix SDAR_MODE value for continous sampling on Power9
In case of continous sampling (non-marked), the code currently
sets MMCRA[SDAR_MODE] to 0b01 (Update on TLB miss) for Power9 DD1.
On DD2 and later it copies the sdar_mode value from the event code,
which for most events is 0b00 (No updates).
However we must set a non-zero value for SDAR_MODE when doing
continuous sampling, so honor the event code, unless it's zero, in
which case we use use 0b01 (Update on TLB miss).
Fixes: 78b4416aa2
("powerpc/perf: Handle sdar_mode for marked event in power9")
Cc: stable@vger.kernel.org # v4.11+
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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parent
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commit
20dd4c624d
1 changed files with 4 additions and 2 deletions
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@ -90,13 +90,15 @@ static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
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* MMCRA[SDAR_MODE] will be set to 0b01
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* For rest
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* MMCRA[SDAR_MODE] will be set from event code.
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* If sdar_mode from event is zero, default to 0b01. Hardware
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* requires that we set a non-zero value.
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*/
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if (cpu_has_feature(CPU_FTR_ARCH_300)) {
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if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
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*mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
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else if (!cpu_has_feature(CPU_FTR_POWER9_DD1))
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else if (!cpu_has_feature(CPU_FTR_POWER9_DD1) && p9_SDAR_MODE(event))
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*mmcra |= p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT;
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else if (cpu_has_feature(CPU_FTR_POWER9_DD1))
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else
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*mmcra |= MMCRA_SDAR_MODE_TLB;
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} else
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*mmcra |= MMCRA_SDAR_MODE_TLB;
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