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arm64: dts: renesas: r9a07g043: Add SDHI nodes

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Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402081328.26292-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2022-04-02 09:13:24 +01:00 committed by Geert Uytterhoeven
parent 4e44055440
commit 20e63d3948
1 changed files with 24 additions and 2 deletions
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26
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
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@ -334,13 +334,35 @@ gic: interrupt-controller@11900000 {
};
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
/* place holder */
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
<&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
<&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A07G043_SDHI0_IXRST>;
power-domains = <&cpg>;
status = "disabled";
};
sdhi1: mmc@11c10000 {
compatible = "renesas,sdhi-r9a07g043",
"renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c10000 0 0x10000>;
/* place holder */
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
<&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
<&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A07G043_SDHI1_IXRST>;
power-domains = <&cpg>;
status = "disabled";
};
phyrst: usbphy-ctrl@11c40000 {