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arm64: dts: qcom: sm8450: Add SDHCI2

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Add and configure the SDHCI host responsible for (mostly) SD Card and
its corresponding pins' sleep states.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220714123406.1919836-4-konrad.dybcio@somainline.org
This commit is contained in:
Konrad Dybcio 2022-07-14 14:34:05 +02:00 committed by Bjorn Andersson
parent 2fb1926344
commit 20e8f1ee8d
1 changed files with 59 additions and 0 deletions
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59
arch/arm64/boot/dts/qcom/sm8450.dtsi
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@ -2384,6 +2384,26 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 211>;
wakeup-parent = <&pdc>;
sdc2_sleep_state: sdc2-sleep {
clk {
pins = "sdc2_clk";
drive-strength = <2>;
bias-disable;
};
cmd {
pins = "sdc2_cmd";
drive-strength = <2>;
bias-pull-up;
};
data {
pins = "sdc2_data";
drive-strength = <2>;
bias-pull-up;
};
};
pcie0_default_state: pcie0-default-state {
perst {
pins = "gpio94";
@ -3145,6 +3165,45 @@ ufs_mem_phy_lanes: phy@1d87400 {
};
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo";
resets = <&gcc GCC_SDCC2_BCR>;
interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
iommus = <&apps_smmu 0x4a0 0x0>;
power-domains = <&rpmhpd SM8450_CX>;
operating-points-v2 = <&sdhc2_opp_table>;
bus-width = <4>;
dma-coherent;
status = "disabled";
sdhc2_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
usb_1: usb@a6f8800 {
compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;