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habanalabs: add uapi to flush inbound HBM transactions
When doing p2p with a NIC device, the NIC needs to make sure all the writes to the HBM (through the PCI bar of the Gaudi device) were flushed. It can be done by either the NIC or the host reading through the PCI bar. To support the host side, we supply a simple uapi to perform this flush through the driver, because the user can't create such a transaction by itself (the PCI bar isn't exposed to normal users). Signed-off-by: Ohad Sharabi <osharabi@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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parent
e65e175b07
commit
20faaeec37
6 changed files with 41 additions and 2 deletions
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@ -13,7 +13,8 @@
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#define HL_CS_FLAGS_TYPE_MASK (HL_CS_FLAGS_SIGNAL | HL_CS_FLAGS_WAIT | \
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HL_CS_FLAGS_COLLECTIVE_WAIT | HL_CS_FLAGS_RESERVE_SIGNALS_ONLY | \
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HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY | HL_CS_FLAGS_ENGINE_CORE_COMMAND)
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HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY | HL_CS_FLAGS_ENGINE_CORE_COMMAND | \
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HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES)
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#define MAX_TS_ITER_NUM 10
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@ -1295,6 +1296,8 @@ static enum hl_cs_type hl_cs_get_cs_type(u32 cs_type_flags)
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return CS_UNRESERVE_SIGNALS;
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else if (cs_type_flags & HL_CS_FLAGS_ENGINE_CORE_COMMAND)
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return CS_TYPE_ENGINE_CORE;
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else if (cs_type_flags & HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES)
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return CS_TYPE_FLUSH_PCI_HBW_WRITES;
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else
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return CS_TYPE_DEFAULT;
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}
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@ -2443,6 +2446,21 @@ static int cs_ioctl_engine_cores(struct hl_fpriv *hpriv, u64 engine_cores,
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return rc;
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}
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static int cs_ioctl_flush_pci_hbw_writes(struct hl_fpriv *hpriv)
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{
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struct hl_device *hdev = hpriv->hdev;
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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if (!prop->hbw_flush_reg) {
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dev_dbg(hdev->dev, "HBW flush is not supported\n");
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return -EOPNOTSUPP;
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}
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RREG32(prop->hbw_flush_reg);
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return 0;
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}
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int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data)
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{
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union hl_cs_args *args = data;
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@ -2499,6 +2517,9 @@ int hl_cs_ioctl(struct hl_fpriv *hpriv, void *data)
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rc = cs_ioctl_engine_cores(hpriv, args->in.engine_cores,
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args->in.num_engine_cores, args->in.core_command);
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break;
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case CS_TYPE_FLUSH_PCI_HBW_WRITES:
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rc = cs_ioctl_flush_pci_hbw_writes(hpriv);
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break;
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default:
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rc = cs_ioctl_default(hpriv, chunks, num_chunks, &cs_seq,
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args->in.cs_flags,
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@ -375,7 +375,8 @@ enum hl_cs_type {
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CS_TYPE_COLLECTIVE_WAIT,
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CS_RESERVE_SIGNALS,
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CS_UNRESERVE_SIGNALS,
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CS_TYPE_ENGINE_CORE
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CS_TYPE_ENGINE_CORE,
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CS_TYPE_FLUSH_PCI_HBW_WRITES,
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};
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/*
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@ -644,6 +645,8 @@ struct hl_hints_range {
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* (i.e. the DRAM supports multiple page sizes), otherwise
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* it will shall be equal to dram_page_size.
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* @num_engine_cores: number of engine cpu cores
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* @hbw_flush_reg: register to read to generate HBW flush. value of 0 means HBW flush is
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* not supported.
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* @collective_first_sob: first sync object available for collective use
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* @collective_first_mon: first monitor available for collective use
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* @sync_stream_first_sob: first sync object available for sync stream use
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@ -764,6 +767,7 @@ struct asic_fixed_properties {
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u32 xbar_edge_enabled_mask;
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u32 device_mem_alloc_default_page_size;
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u32 num_engine_cores;
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u32 hbw_flush_reg;
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u16 collective_first_sob;
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u16 collective_first_mon;
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u16 sync_stream_first_sob;
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@ -701,6 +701,8 @@ static int gaudi_set_fixed_properties(struct hl_device *hdev)
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prop->dma_mask = 48;
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prop->hbw_flush_reg = mmPCIE_WRAP_RR_ELBI_RD_SEC_REG_CTRL;
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return 0;
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}
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@ -2071,6 +2071,8 @@ static int gaudi2_set_fixed_properties(struct hl_device *hdev)
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prop->dma_mask = 64;
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prop->hbw_flush_reg = mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0;
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return 0;
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}
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@ -320,4 +320,6 @@
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#define mmPSOC_TPC_PLL_NR 0xC73100
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#define mmIF_W_PLL_NR 0x488100
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#define mmPCIE_WRAP_RR_ELBI_RD_SEC_REG_CTRL 0xC01208
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#endif /* ASIC_REG_GAUDI_REGS_H_ */
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@ -1478,6 +1478,14 @@ struct hl_cs_chunk {
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*/
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#define HL_CS_FLAGS_ENGINE_CORE_COMMAND 0x4000
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/*
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* The flush HBW PCI writes is merged into the existing CS ioctls.
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* Used to flush all HBW PCI writes.
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* This is a blocking operation and for this reason the user shall not use
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* the return sequence number (which will be invalid anyway)
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*/
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#define HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES 0x8000
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#define HL_CS_STATUS_SUCCESS 0
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#define HL_MAX_JOBS_PER_CS 512
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