mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-05 10:29:37 +00:00
gma500: use the register map to clean up
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
8512e07487
commit
213a84346f
8 changed files with 473 additions and 783 deletions
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@ -494,6 +494,7 @@ static const struct psb_offset cdv_regmap[2] = {
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.conf = PIPEACONF,
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.src = PIPEASRC,
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.dpll = DPLL_A,
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.dpll_md = DPLL_A_MD,
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.htotal = HTOTAL_A,
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.hblank = HBLANK_A,
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.hsync = HSYNC_A,
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@ -518,6 +519,7 @@ static const struct psb_offset cdv_regmap[2] = {
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.conf = PIPEBCONF,
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.src = PIPEBSRC,
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.dpll = DPLL_B,
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.dpll_md = DPLL_B_MD,
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.htotal = HTOTAL_B,
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.hblank = HBLANK_B,
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.hsync = HSYNC_B,
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@ -218,8 +218,7 @@ static int
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cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
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struct cdv_intel_clock_t *clock, bool is_lvds)
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{
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struct psb_intel_crtc *psb_crtc =
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to_psb_intel_crtc(crtc);
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struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc);
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int pipe = psb_crtc->pipe;
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u32 m, n_vco, p;
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int ret = 0;
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@ -503,14 +502,12 @@ static int cdv_intel_pipe_set_base(struct drm_crtc *crtc,
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int x, int y, struct drm_framebuffer *old_fb)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
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int pipe = psb_intel_crtc->pipe;
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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unsigned long start, offset;
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int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
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int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
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int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
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int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
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u32 dspcntr;
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int ret = 0;
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@ -532,9 +529,9 @@ static int cdv_intel_pipe_set_base(struct drm_crtc *crtc,
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start = psbfb->gtt->offset;
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offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
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REG_WRITE(dspstride, crtc->fb->pitches[0]);
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REG_WRITE(map->stride, crtc->fb->pitches[0]);
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dspcntr = REG_READ(dspcntr_reg);
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dspcntr = REG_READ(map->cntr);
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dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
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switch (crtc->fb->bits_per_pixel) {
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@ -556,15 +553,15 @@ static int cdv_intel_pipe_set_base(struct drm_crtc *crtc,
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ret = -EINVAL;
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goto psb_intel_pipe_set_base_exit;
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}
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REG_WRITE(dspcntr_reg, dspcntr);
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REG_WRITE(map->cntr, dspcntr);
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dev_dbg(dev->dev,
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"Writing base %08lX %08lX %d %d\n", start, offset, x, y);
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REG_WRITE(dspbase, offset);
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REG_READ(dspbase);
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REG_WRITE(dspsurf, start);
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REG_READ(dspsurf);
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REG_WRITE(map->base, offset);
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REG_READ(map->base);
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REG_WRITE(map->surf, start);
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REG_READ(map->surf);
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psb_intel_pipe_cleaner:
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/* If there was a previous display we can now unpin it */
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@ -721,8 +718,7 @@ static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc
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static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv =
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(struct drm_psb_private *)dev->dev_private;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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int palreg = PALETTE_A;
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int i;
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@ -779,13 +775,10 @@ static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
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static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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int pipe = psb_intel_crtc->pipe;
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int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
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int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
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int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE;
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int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
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int pipestat_reg = (pipe == 0) ? PIPEASTAT : PIPEBSTAT;
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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u32 temp;
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/* XXX: When our outputs are all unaware of DPMS modes other than off
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@ -803,44 +796,44 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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psb_intel_crtc->active = true;
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/* Enable the DPLL */
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temp = REG_READ(dpll_reg);
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temp = REG_READ(map->dpll);
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if ((temp & DPLL_VCO_ENABLE) == 0) {
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REG_WRITE(dpll_reg, temp);
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REG_READ(dpll_reg);
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REG_WRITE(map->dpll, temp);
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REG_READ(map->dpll);
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/* Wait for the clocks to stabilize. */
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udelay(150);
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REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
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REG_READ(dpll_reg);
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REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
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REG_READ(map->dpll);
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/* Wait for the clocks to stabilize. */
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udelay(150);
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REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
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REG_READ(dpll_reg);
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REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
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REG_READ(map->dpll);
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/* Wait for the clocks to stabilize. */
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udelay(150);
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}
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/* Jim Bish - switch plan and pipe per scott */
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/* Enable the plane */
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temp = REG_READ(dspcntr_reg);
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temp = REG_READ(map->cntr);
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if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
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REG_WRITE(dspcntr_reg,
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REG_WRITE(map->cntr,
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temp | DISPLAY_PLANE_ENABLE);
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/* Flush the plane changes */
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REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
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REG_WRITE(map->base, REG_READ(map->base));
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}
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udelay(150);
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/* Enable the pipe */
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temp = REG_READ(pipeconf_reg);
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temp = REG_READ(map->conf);
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if ((temp & PIPEACONF_ENABLE) == 0)
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REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
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REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
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temp = REG_READ(pipestat_reg);
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temp = REG_READ(map->status);
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temp &= ~(0xFFFF);
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temp |= PIPE_FIFO_UNDERRUN;
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REG_WRITE(pipestat_reg, temp);
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REG_READ(pipestat_reg);
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REG_WRITE(map->status, temp);
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REG_READ(map->status);
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cdv_intel_update_watermark(dev, crtc);
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cdv_intel_crtc_load_lut(crtc);
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@ -870,10 +863,10 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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cdv_intel_wait_for_vblank(dev);
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/* Next, disable display pipes */
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temp = REG_READ(pipeconf_reg);
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temp = REG_READ(map->conf);
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if ((temp & PIPEACONF_ENABLE) != 0) {
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REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
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REG_READ(pipeconf_reg);
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REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
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REG_READ(map->conf);
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}
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/* Wait for vblank for the disable to take effect. */
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@ -882,19 +875,19 @@ static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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udelay(150);
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/* Disable display plane */
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temp = REG_READ(dspcntr_reg);
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temp = REG_READ(map->cntr);
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if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
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REG_WRITE(dspcntr_reg,
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REG_WRITE(map->cntr,
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temp & ~DISPLAY_PLANE_ENABLE);
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/* Flush the plane changes */
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REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
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REG_READ(dspbase_reg);
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REG_WRITE(map->base, REG_READ(map->base));
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REG_READ(map->base);
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}
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temp = REG_READ(dpll_reg);
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temp = REG_READ(map->dpll);
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if ((temp & DPLL_VCO_ENABLE) != 0) {
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REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
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REG_READ(dpll_reg);
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REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
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REG_READ(map->dpll);
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}
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/* Wait for the clocks to turn off. */
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@ -953,19 +946,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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int pipe = psb_intel_crtc->pipe;
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int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
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int dpll_md_reg = (psb_intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
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int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
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int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
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int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
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int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
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int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
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int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
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int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
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int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
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int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
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int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
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int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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int refclk;
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struct cdv_intel_clock_t clock;
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u32 dpll = 0, dspcntr, pipeconf;
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@ -1036,7 +1017,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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/* dpll |= (2 << 11); */
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/* setup pipeconf */
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pipeconf = REG_READ(pipeconf_reg);
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pipeconf = REG_READ(map->conf);
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/* Set up the display plane register */
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dspcntr = DISPPLANE_GAMMA_ENABLE;
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@ -1049,8 +1030,8 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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dspcntr |= DISPLAY_PLANE_ENABLE;
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pipeconf |= PIPEACONF_ENABLE;
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REG_WRITE(dpll_reg, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
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REG_READ(dpll_reg);
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REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
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REG_READ(map->dpll);
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cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds);
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@ -1094,48 +1075,48 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
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drm_mode_debug_printmodeline(mode);
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REG_WRITE(dpll_reg,
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(REG_READ(dpll_reg) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
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REG_READ(dpll_reg);
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REG_WRITE(map->dpll,
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(REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
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REG_READ(map->dpll);
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/* Wait for the clocks to stabilize. */
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udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
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if (!(REG_READ(dpll_reg) & DPLL_LOCK)) {
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if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
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dev_err(dev->dev, "Failed to get DPLL lock\n");
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return -EBUSY;
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}
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{
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int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
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REG_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
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REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
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}
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REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
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REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
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((adjusted_mode->crtc_htotal - 1) << 16));
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REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
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REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
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((adjusted_mode->crtc_hblank_end - 1) << 16));
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REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
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REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
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((adjusted_mode->crtc_hsync_end - 1) << 16));
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REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
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REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
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((adjusted_mode->crtc_vtotal - 1) << 16));
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REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
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REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
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((adjusted_mode->crtc_vblank_end - 1) << 16));
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REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
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REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
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((adjusted_mode->crtc_vsync_end - 1) << 16));
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/* pipesrc and dspsize control the size that is scaled from,
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* which should always be the user's requested size.
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*/
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REG_WRITE(dspsize_reg,
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REG_WRITE(map->size,
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((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
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REG_WRITE(dsppos_reg, 0);
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REG_WRITE(pipesrc_reg,
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REG_WRITE(map->pos, 0);
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REG_WRITE(map->src,
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((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
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REG_WRITE(pipeconf_reg, pipeconf);
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REG_READ(pipeconf_reg);
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REG_WRITE(map->conf, pipeconf);
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REG_READ(map->conf);
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cdv_intel_wait_for_vblank(dev);
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REG_WRITE(dspcntr_reg, dspcntr);
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REG_WRITE(map->cntr, dspcntr);
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/* Flush the plane changes */
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{
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@ -1156,11 +1137,10 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
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static void cdv_intel_crtc_save(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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/* struct drm_psb_private *dev_priv =
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(struct drm_psb_private *)dev->dev_private; */
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
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struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
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int pipeA = (psb_intel_crtc->pipe == 0);
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const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
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uint32_t paletteReg;
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int i;
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@ -1169,25 +1149,25 @@ static void cdv_intel_crtc_save(struct drm_crtc *crtc)
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return;
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}
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crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR);
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crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF);
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crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC);
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crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0);
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crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1);
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crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B);
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crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B);
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crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B);
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crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B);
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crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B);
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crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B);
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crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B);
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crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE);
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crtc_state->saveDSPCNTR = REG_READ(map->cntr);
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crtc_state->savePIPECONF = REG_READ(map->conf);
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crtc_state->savePIPESRC = REG_READ(map->src);
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crtc_state->saveFP0 = REG_READ(map->fp0);
|
||||
crtc_state->saveFP1 = REG_READ(map->fp1);
|
||||
crtc_state->saveDPLL = REG_READ(map->dpll);
|
||||
crtc_state->saveHTOTAL = REG_READ(map->htotal);
|
||||
crtc_state->saveHBLANK = REG_READ(map->hblank);
|
||||
crtc_state->saveHSYNC = REG_READ(map->hsync);
|
||||
crtc_state->saveVTOTAL = REG_READ(map->vtotal);
|
||||
crtc_state->saveVBLANK = REG_READ(map->vblank);
|
||||
crtc_state->saveVSYNC = REG_READ(map->vsync);
|
||||
crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
|
||||
|
||||
/*NOTE: DSPSIZE DSPPOS only for psb*/
|
||||
crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE);
|
||||
crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS);
|
||||
crtc_state->saveDSPSIZE = REG_READ(map->size);
|
||||
crtc_state->saveDSPPOS = REG_READ(map->pos);
|
||||
|
||||
crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE);
|
||||
crtc_state->saveDSPBASE = REG_READ(map->base);
|
||||
|
||||
DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
|
||||
crtc_state->saveDSPCNTR,
|
||||
|
@ -1208,7 +1188,7 @@ static void cdv_intel_crtc_save(struct drm_crtc *crtc)
|
|||
crtc_state->saveDSPBASE
|
||||
);
|
||||
|
||||
paletteReg = pipeA ? PALETTE_A : PALETTE_B;
|
||||
paletteReg = map->palette;
|
||||
for (i = 0; i < 256; ++i)
|
||||
crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
|
||||
}
|
||||
|
@ -1219,12 +1199,10 @@ static void cdv_intel_crtc_save(struct drm_crtc *crtc)
|
|||
static void cdv_intel_crtc_restore(struct drm_crtc *crtc)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
/* struct drm_psb_private * dev_priv =
|
||||
(struct drm_psb_private *)dev->dev_private; */
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
|
||||
/* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */
|
||||
int pipeA = (psb_intel_crtc->pipe == 0);
|
||||
const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
|
||||
uint32_t paletteReg;
|
||||
int i;
|
||||
|
||||
|
@ -1235,23 +1213,23 @@ static void cdv_intel_crtc_restore(struct drm_crtc *crtc)
|
|||
|
||||
DRM_DEBUG(
|
||||
"current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
|
||||
REG_READ(pipeA ? DSPACNTR : DSPBCNTR),
|
||||
REG_READ(pipeA ? PIPEACONF : PIPEBCONF),
|
||||
REG_READ(pipeA ? PIPEASRC : PIPEBSRC),
|
||||
REG_READ(pipeA ? FPA0 : FPB0),
|
||||
REG_READ(pipeA ? FPA1 : FPB1),
|
||||
REG_READ(pipeA ? DPLL_A : DPLL_B),
|
||||
REG_READ(pipeA ? HTOTAL_A : HTOTAL_B),
|
||||
REG_READ(pipeA ? HBLANK_A : HBLANK_B),
|
||||
REG_READ(pipeA ? HSYNC_A : HSYNC_B),
|
||||
REG_READ(pipeA ? VTOTAL_A : VTOTAL_B),
|
||||
REG_READ(pipeA ? VBLANK_A : VBLANK_B),
|
||||
REG_READ(pipeA ? VSYNC_A : VSYNC_B),
|
||||
REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE),
|
||||
REG_READ(pipeA ? DSPASIZE : DSPBSIZE),
|
||||
REG_READ(pipeA ? DSPAPOS : DSPBPOS),
|
||||
REG_READ(pipeA ? DSPABASE : DSPBBASE)
|
||||
);
|
||||
REG_READ(map->cntr),
|
||||
REG_READ(map->conf),
|
||||
REG_READ(map->src),
|
||||
REG_READ(map->fp0),
|
||||
REG_READ(map->fp1),
|
||||
REG_READ(map->dpll),
|
||||
REG_READ(map->htotal),
|
||||
REG_READ(map->hblank),
|
||||
REG_READ(map->hsync),
|
||||
REG_READ(map->vtotal),
|
||||
REG_READ(map->vblank),
|
||||
REG_READ(map->vsync),
|
||||
REG_READ(map->stride),
|
||||
REG_READ(map->size),
|
||||
REG_READ(map->pos),
|
||||
REG_READ(map->base)
|
||||
);
|
||||
|
||||
DRM_DEBUG(
|
||||
"saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
|
||||
|
@ -1271,51 +1249,51 @@ static void cdv_intel_crtc_restore(struct drm_crtc *crtc)
|
|||
crtc_state->saveDSPSIZE,
|
||||
crtc_state->saveDSPPOS,
|
||||
crtc_state->saveDSPBASE
|
||||
);
|
||||
);
|
||||
|
||||
|
||||
if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
|
||||
REG_WRITE(pipeA ? DPLL_A : DPLL_B,
|
||||
crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
|
||||
REG_READ(pipeA ? DPLL_A : DPLL_B);
|
||||
REG_WRITE(map->dpll,
|
||||
crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
|
||||
REG_READ(map->dpll);
|
||||
DRM_DEBUG("write dpll: %x\n",
|
||||
REG_READ(pipeA ? DPLL_A : DPLL_B));
|
||||
REG_READ(map->dpll));
|
||||
udelay(150);
|
||||
}
|
||||
|
||||
REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0);
|
||||
REG_READ(pipeA ? FPA0 : FPB0);
|
||||
REG_WRITE(map->fp0, crtc_state->saveFP0);
|
||||
REG_READ(map->fp0);
|
||||
|
||||
REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1);
|
||||
REG_READ(pipeA ? FPA1 : FPB1);
|
||||
REG_WRITE(map->fp1, crtc_state->saveFP1);
|
||||
REG_READ(map->fp1);
|
||||
|
||||
REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL);
|
||||
REG_READ(pipeA ? DPLL_A : DPLL_B);
|
||||
REG_WRITE(map->dpll, crtc_state->saveDPLL);
|
||||
REG_READ(map->dpll);
|
||||
udelay(150);
|
||||
|
||||
REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL);
|
||||
REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK);
|
||||
REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC);
|
||||
REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL);
|
||||
REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK);
|
||||
REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC);
|
||||
REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE);
|
||||
REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
|
||||
REG_WRITE(map->hblank, crtc_state->saveHBLANK);
|
||||
REG_WRITE(map->hsync, crtc_state->saveHSYNC);
|
||||
REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
|
||||
REG_WRITE(map->vblank, crtc_state->saveVBLANK);
|
||||
REG_WRITE(map->vsync, crtc_state->saveVSYNC);
|
||||
REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
|
||||
|
||||
REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE);
|
||||
REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS);
|
||||
REG_WRITE(map->size, crtc_state->saveDSPSIZE);
|
||||
REG_WRITE(map->pos, crtc_state->saveDSPPOS);
|
||||
|
||||
REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC);
|
||||
REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
|
||||
REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF);
|
||||
REG_WRITE(map->src, crtc_state->savePIPESRC);
|
||||
REG_WRITE(map->base, crtc_state->saveDSPBASE);
|
||||
REG_WRITE(map->conf, crtc_state->savePIPECONF);
|
||||
|
||||
cdv_intel_wait_for_vblank(dev);
|
||||
|
||||
REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR);
|
||||
REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
|
||||
REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
|
||||
REG_WRITE(map->base, crtc_state->saveDSPBASE);
|
||||
|
||||
cdv_intel_wait_for_vblank(dev);
|
||||
|
||||
paletteReg = pipeA ? PALETTE_A : PALETTE_B;
|
||||
paletteReg = map->palette;
|
||||
for (i = 0; i < 256; ++i)
|
||||
REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
|
||||
}
|
||||
|
@ -1490,21 +1468,22 @@ static void i8xx_clock(int refclk, struct cdv_intel_clock_t *clock)
|
|||
static int cdv_intel_crtc_clock_get(struct drm_device *dev,
|
||||
struct drm_crtc *crtc)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
u32 dpll;
|
||||
u32 fp;
|
||||
struct cdv_intel_clock_t clock;
|
||||
bool is_lvds;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B);
|
||||
dpll = REG_READ(map->dpll);
|
||||
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
|
||||
fp = REG_READ((pipe == 0) ? FPA0 : FPB0);
|
||||
fp = REG_READ(map->fp0);
|
||||
else
|
||||
fp = REG_READ((pipe == 0) ? FPA1 : FPB1);
|
||||
fp = REG_READ(map->fp1);
|
||||
is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
|
||||
gma_power_end(dev);
|
||||
} else {
|
||||
|
@ -1570,19 +1549,20 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
|
|||
{
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
struct drm_display_mode *mode;
|
||||
int htot;
|
||||
int hsync;
|
||||
int vtot;
|
||||
int vsync;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
|
||||
hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
|
||||
vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
|
||||
vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
|
||||
htot = REG_READ(map->htotal);
|
||||
hsync = REG_READ(map->hsync);
|
||||
vtot = REG_READ(map->vtotal);
|
||||
vsync = REG_READ(map->vsync);
|
||||
gma_power_end(dev);
|
||||
} else {
|
||||
htot = p->htotal;
|
||||
|
|
|
@ -168,30 +168,12 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipenum)
|
|||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct medfield_state *regs = &dev_priv->regs.mdfld;
|
||||
struct psb_pipe *pipe = &dev_priv->regs.pipe[pipenum];
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipenum];
|
||||
int i;
|
||||
u32 *mipi_val;
|
||||
|
||||
/* register */
|
||||
u32 dpll_reg = MRST_DPLL_A;
|
||||
u32 fp_reg = MRST_FPA0;
|
||||
u32 pipeconf_reg = PIPEACONF;
|
||||
u32 htot_reg = HTOTAL_A;
|
||||
u32 hblank_reg = HBLANK_A;
|
||||
u32 hsync_reg = HSYNC_A;
|
||||
u32 vtot_reg = VTOTAL_A;
|
||||
u32 vblank_reg = VBLANK_A;
|
||||
u32 vsync_reg = VSYNC_A;
|
||||
u32 pipesrc_reg = PIPEASRC;
|
||||
u32 dspstride_reg = DSPASTRIDE;
|
||||
u32 dsplinoff_reg = DSPALINOFF;
|
||||
u32 dsptileoff_reg = DSPATILEOFF;
|
||||
u32 dspsize_reg = DSPASIZE;
|
||||
u32 dsppos_reg = DSPAPOS;
|
||||
u32 dspsurf_reg = DSPASURF;
|
||||
u32 mipi_reg = MIPI;
|
||||
u32 dspcntr_reg = DSPACNTR;
|
||||
u32 dspstatus_reg = PIPEASTAT;
|
||||
u32 palette_reg = PALETTE_A;
|
||||
|
||||
switch (pipenum) {
|
||||
case 0:
|
||||
|
@ -199,48 +181,10 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipenum)
|
|||
break;
|
||||
case 1:
|
||||
mipi_val = ®s->saveMIPI;
|
||||
/* register */
|
||||
dpll_reg = MDFLD_DPLL_B;
|
||||
fp_reg = MDFLD_DPLL_DIV0;
|
||||
pipeconf_reg = PIPEBCONF;
|
||||
htot_reg = HTOTAL_B;
|
||||
hblank_reg = HBLANK_B;
|
||||
hsync_reg = HSYNC_B;
|
||||
vtot_reg = VTOTAL_B;
|
||||
vblank_reg = VBLANK_B;
|
||||
vsync_reg = VSYNC_B;
|
||||
pipesrc_reg = PIPEBSRC;
|
||||
dspstride_reg = DSPBSTRIDE;
|
||||
dsplinoff_reg = DSPBLINOFF;
|
||||
dsptileoff_reg = DSPBTILEOFF;
|
||||
dspsize_reg = DSPBSIZE;
|
||||
dsppos_reg = DSPBPOS;
|
||||
dspsurf_reg = DSPBSURF;
|
||||
dspcntr_reg = DSPBCNTR;
|
||||
dspstatus_reg = PIPEBSTAT;
|
||||
palette_reg = PALETTE_B;
|
||||
break;
|
||||
case 2:
|
||||
/* register */
|
||||
pipeconf_reg = PIPECCONF;
|
||||
htot_reg = HTOTAL_C;
|
||||
hblank_reg = HBLANK_C;
|
||||
hsync_reg = HSYNC_C;
|
||||
vtot_reg = VTOTAL_C;
|
||||
vblank_reg = VBLANK_C;
|
||||
vsync_reg = VSYNC_C;
|
||||
pipesrc_reg = PIPECSRC;
|
||||
dspstride_reg = DSPCSTRIDE;
|
||||
dsplinoff_reg = DSPCLINOFF;
|
||||
dsptileoff_reg = DSPCTILEOFF;
|
||||
dspsize_reg = DSPCSIZE;
|
||||
dsppos_reg = DSPCPOS;
|
||||
dspsurf_reg = DSPCSURF;
|
||||
mipi_reg = MIPI_C;
|
||||
dspcntr_reg = DSPCCNTR;
|
||||
dspstatus_reg = PIPECSTAT;
|
||||
palette_reg = PALETTE_C;
|
||||
|
||||
/* pointer to values */
|
||||
mipi_val = ®s->saveMIPI_C;
|
||||
break;
|
||||
|
@ -250,28 +194,28 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipenum)
|
|||
}
|
||||
|
||||
/* Pipe & plane A info */
|
||||
pipe->dpll = PSB_RVDC32(dpll_reg);
|
||||
pipe->fp0 = PSB_RVDC32(fp_reg);
|
||||
pipe->conf = PSB_RVDC32(pipeconf_reg);
|
||||
pipe->htotal = PSB_RVDC32(htot_reg);
|
||||
pipe->hblank = PSB_RVDC32(hblank_reg);
|
||||
pipe->hsync = PSB_RVDC32(hsync_reg);
|
||||
pipe->vtotal = PSB_RVDC32(vtot_reg);
|
||||
pipe->vblank = PSB_RVDC32(vblank_reg);
|
||||
pipe->vsync = PSB_RVDC32(vsync_reg);
|
||||
pipe->src = PSB_RVDC32(pipesrc_reg);
|
||||
pipe->stride = PSB_RVDC32(dspstride_reg);
|
||||
pipe->linoff = PSB_RVDC32(dsplinoff_reg);
|
||||
pipe->tileoff = PSB_RVDC32(dsptileoff_reg);
|
||||
pipe->size = PSB_RVDC32(dspsize_reg);
|
||||
pipe->pos = PSB_RVDC32(dsppos_reg);
|
||||
pipe->surf = PSB_RVDC32(dspsurf_reg);
|
||||
pipe->cntr = PSB_RVDC32(dspcntr_reg);
|
||||
pipe->status = PSB_RVDC32(dspstatus_reg);
|
||||
pipe->dpll = PSB_RVDC32(map->dpll);
|
||||
pipe->fp0 = PSB_RVDC32(map->fp0);
|
||||
pipe->conf = PSB_RVDC32(map->conf);
|
||||
pipe->htotal = PSB_RVDC32(map->htotal);
|
||||
pipe->hblank = PSB_RVDC32(map->hblank);
|
||||
pipe->hsync = PSB_RVDC32(map->hsync);
|
||||
pipe->vtotal = PSB_RVDC32(map->vtotal);
|
||||
pipe->vblank = PSB_RVDC32(map->vblank);
|
||||
pipe->vsync = PSB_RVDC32(map->vsync);
|
||||
pipe->src = PSB_RVDC32(map->src);
|
||||
pipe->stride = PSB_RVDC32(map->stride);
|
||||
pipe->linoff = PSB_RVDC32(map->linoff);
|
||||
pipe->tileoff = PSB_RVDC32(map->tileoff);
|
||||
pipe->size = PSB_RVDC32(map->size);
|
||||
pipe->pos = PSB_RVDC32(map->pos);
|
||||
pipe->surf = PSB_RVDC32(map->surf);
|
||||
pipe->cntr = PSB_RVDC32(map->cntr);
|
||||
pipe->status = PSB_RVDC32(map->status);
|
||||
|
||||
/*save palette (gamma) */
|
||||
for (i = 0; i < 256; i++)
|
||||
pipe->palette[i] = PSB_RVDC32(palette_reg + (i << 2));
|
||||
pipe->palette[i] = PSB_RVDC32(map->palette + (i << 2));
|
||||
|
||||
if (pipenum == 1) {
|
||||
regs->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
|
||||
|
@ -302,31 +246,13 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
|
|||
struct mdfld_dsi_config *dsi_config = NULL;
|
||||
struct medfield_state *regs = &dev_priv->regs.mdfld;
|
||||
struct psb_pipe *pipe = &dev_priv->regs.pipe[pipenum];
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipenum];
|
||||
u32 i;
|
||||
u32 dpll;
|
||||
u32 timeout = 0;
|
||||
|
||||
/* register */
|
||||
u32 dpll_reg = MRST_DPLL_A;
|
||||
u32 fp_reg = MRST_FPA0;
|
||||
u32 pipeconf_reg = PIPEACONF;
|
||||
u32 htot_reg = HTOTAL_A;
|
||||
u32 hblank_reg = HBLANK_A;
|
||||
u32 hsync_reg = HSYNC_A;
|
||||
u32 vtot_reg = VTOTAL_A;
|
||||
u32 vblank_reg = VBLANK_A;
|
||||
u32 vsync_reg = VSYNC_A;
|
||||
u32 pipesrc_reg = PIPEASRC;
|
||||
u32 dspstride_reg = DSPASTRIDE;
|
||||
u32 dsplinoff_reg = DSPALINOFF;
|
||||
u32 dsptileoff_reg = DSPATILEOFF;
|
||||
u32 dspsize_reg = DSPASIZE;
|
||||
u32 dsppos_reg = DSPAPOS;
|
||||
u32 dspsurf_reg = DSPASURF;
|
||||
u32 dspstatus_reg = PIPEASTAT;
|
||||
u32 mipi_reg = MIPI;
|
||||
u32 dspcntr_reg = DSPACNTR;
|
||||
u32 palette_reg = PALETTE_A;
|
||||
|
||||
/* values */
|
||||
u32 dpll_val = pipe->dpll;
|
||||
|
@ -338,52 +264,10 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
|
|||
dsi_config = dev_priv->dsi_configs[0];
|
||||
break;
|
||||
case 1:
|
||||
/* register */
|
||||
dpll_reg = MDFLD_DPLL_B;
|
||||
fp_reg = MDFLD_DPLL_DIV0;
|
||||
pipeconf_reg = PIPEBCONF;
|
||||
htot_reg = HTOTAL_B;
|
||||
hblank_reg = HBLANK_B;
|
||||
hsync_reg = HSYNC_B;
|
||||
vtot_reg = VTOTAL_B;
|
||||
vblank_reg = VBLANK_B;
|
||||
vsync_reg = VSYNC_B;
|
||||
pipesrc_reg = PIPEBSRC;
|
||||
dspstride_reg = DSPBSTRIDE;
|
||||
dsplinoff_reg = DSPBLINOFF;
|
||||
dsptileoff_reg = DSPBTILEOFF;
|
||||
dspsize_reg = DSPBSIZE;
|
||||
dsppos_reg = DSPBPOS;
|
||||
dspsurf_reg = DSPBSURF;
|
||||
dspcntr_reg = DSPBCNTR;
|
||||
dspstatus_reg = PIPEBSTAT;
|
||||
palette_reg = PALETTE_B;
|
||||
|
||||
/* values */
|
||||
dpll_val &= ~DPLL_VCO_ENABLE;
|
||||
break;
|
||||
case 2:
|
||||
/* register */
|
||||
pipeconf_reg = PIPECCONF;
|
||||
htot_reg = HTOTAL_C;
|
||||
hblank_reg = HBLANK_C;
|
||||
hsync_reg = HSYNC_C;
|
||||
vtot_reg = VTOTAL_C;
|
||||
vblank_reg = VBLANK_C;
|
||||
vsync_reg = VSYNC_C;
|
||||
pipesrc_reg = PIPECSRC;
|
||||
dspstride_reg = DSPCSTRIDE;
|
||||
dsplinoff_reg = DSPCLINOFF;
|
||||
dsptileoff_reg = DSPCTILEOFF;
|
||||
dspsize_reg = DSPCSIZE;
|
||||
dsppos_reg = DSPCPOS;
|
||||
dspsurf_reg = DSPCSURF;
|
||||
mipi_reg = MIPI_C;
|
||||
dspcntr_reg = DSPCCNTR;
|
||||
dspstatus_reg = PIPECSTAT;
|
||||
palette_reg = PALETTE_C;
|
||||
|
||||
/* values */
|
||||
mipi_val = regs->saveMIPI_C;
|
||||
dsi_config = dev_priv->dsi_configs[1];
|
||||
break;
|
||||
|
@ -396,13 +280,13 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
|
|||
PSB_WVDC32(0x80000000, VGACNTRL);
|
||||
|
||||
if (pipenum == 1) {
|
||||
PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, dpll_reg);
|
||||
PSB_RVDC32(dpll_reg);
|
||||
PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll);
|
||||
PSB_RVDC32(map->dpll);
|
||||
|
||||
PSB_WVDC32(pipe->fp0, fp_reg);
|
||||
PSB_WVDC32(pipe->fp0, map->fp0);
|
||||
} else {
|
||||
|
||||
dpll = PSB_RVDC32(dpll_reg);
|
||||
dpll = PSB_RVDC32(map->dpll);
|
||||
|
||||
if (!(dpll & DPLL_VCO_ENABLE)) {
|
||||
|
||||
|
@ -410,23 +294,23 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
|
|||
before enable the VCO */
|
||||
if (dpll & MDFLD_PWR_GATE_EN) {
|
||||
dpll &= ~MDFLD_PWR_GATE_EN;
|
||||
PSB_WVDC32(dpll, dpll_reg);
|
||||
PSB_WVDC32(dpll, map->dpll);
|
||||
/* FIXME_MDFLD PO - change 500 to 1 after PO */
|
||||
udelay(500);
|
||||
}
|
||||
|
||||
PSB_WVDC32(pipe->fp0, fp_reg);
|
||||
PSB_WVDC32(dpll_val, dpll_reg);
|
||||
PSB_WVDC32(pipe->fp0, map->fp0);
|
||||
PSB_WVDC32(dpll_val, map->dpll);
|
||||
/* FIXME_MDFLD PO - change 500 to 1 after PO */
|
||||
udelay(500);
|
||||
|
||||
dpll_val |= DPLL_VCO_ENABLE;
|
||||
PSB_WVDC32(dpll_val, dpll_reg);
|
||||
PSB_RVDC32(dpll_reg);
|
||||
PSB_WVDC32(dpll_val, map->dpll);
|
||||
PSB_RVDC32(map->dpll);
|
||||
|
||||
/* wait for DSI PLL to lock */
|
||||
while (timeout < 20000 &&
|
||||
!(PSB_RVDC32(pipeconf_reg) & PIPECONF_DSIPLL_LOCK)) {
|
||||
!(PSB_RVDC32(map->conf) & PIPECONF_DSIPLL_LOCK)) {
|
||||
udelay(150);
|
||||
timeout++;
|
||||
}
|
||||
|
@ -439,28 +323,28 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
|
|||
}
|
||||
}
|
||||
/* Restore mode */
|
||||
PSB_WVDC32(pipe->htotal, htot_reg);
|
||||
PSB_WVDC32(pipe->hblank, hblank_reg);
|
||||
PSB_WVDC32(pipe->hsync, hsync_reg);
|
||||
PSB_WVDC32(pipe->vtotal, vtot_reg);
|
||||
PSB_WVDC32(pipe->vblank, vblank_reg);
|
||||
PSB_WVDC32(pipe->vsync, vsync_reg);
|
||||
PSB_WVDC32(pipe->src, pipesrc_reg);
|
||||
PSB_WVDC32(pipe->status, dspstatus_reg);
|
||||
PSB_WVDC32(pipe->htotal, map->htotal);
|
||||
PSB_WVDC32(pipe->hblank, map->hblank);
|
||||
PSB_WVDC32(pipe->hsync, map->hsync);
|
||||
PSB_WVDC32(pipe->vtotal, map->vtotal);
|
||||
PSB_WVDC32(pipe->vblank, map->vblank);
|
||||
PSB_WVDC32(pipe->vsync, map->vsync);
|
||||
PSB_WVDC32(pipe->src, map->src);
|
||||
PSB_WVDC32(pipe->status, map->status);
|
||||
|
||||
/*set up the plane*/
|
||||
PSB_WVDC32(pipe->stride, dspstride_reg);
|
||||
PSB_WVDC32(pipe->linoff, dsplinoff_reg);
|
||||
PSB_WVDC32(pipe->tileoff, dsptileoff_reg);
|
||||
PSB_WVDC32(pipe->size, dspsize_reg);
|
||||
PSB_WVDC32(pipe->pos, dsppos_reg);
|
||||
PSB_WVDC32(pipe->surf, dspsurf_reg);
|
||||
PSB_WVDC32(pipe->stride, map->stride);
|
||||
PSB_WVDC32(pipe->linoff, map->linoff);
|
||||
PSB_WVDC32(pipe->tileoff, map->tileoff);
|
||||
PSB_WVDC32(pipe->size, map->size);
|
||||
PSB_WVDC32(pipe->pos, map->pos);
|
||||
PSB_WVDC32(pipe->surf, map->surf);
|
||||
|
||||
if (pipenum == 1) {
|
||||
/* restore palette (gamma) */
|
||||
/*DRM_UDELAY(50000); */
|
||||
for (i = 0; i < 256; i++)
|
||||
PSB_WVDC32(pipe->palette[i], palette_reg + (i << 2));
|
||||
PSB_WVDC32(pipe->palette[i], map->palette + (i << 2));
|
||||
|
||||
PSB_WVDC32(regs->savePFIT_CONTROL, PFIT_CONTROL);
|
||||
PSB_WVDC32(regs->savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
|
||||
|
@ -470,7 +354,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
|
|||
/*TODO: resume pipe*/
|
||||
|
||||
/*enable the plane*/
|
||||
PSB_WVDC32(pipe->cntr & ~DISPLAY_PLANE_ENABLE, dspcntr_reg);
|
||||
PSB_WVDC32(pipe->cntr & ~DISPLAY_PLANE_ENABLE, map->cntr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -488,7 +372,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
|
|||
msleep(20);
|
||||
|
||||
/*enable the plane*/
|
||||
PSB_WVDC32(pipe->cntr, dspcntr_reg);
|
||||
PSB_WVDC32(pipe->cntr, map->cntr);
|
||||
|
||||
if (in_atomic() || in_interrupt())
|
||||
mdelay(20);
|
||||
|
@ -517,12 +401,12 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
|
|||
mdelay(1);
|
||||
|
||||
/*enable the pipe*/
|
||||
PSB_WVDC32(pipe->conf, pipeconf_reg);
|
||||
PSB_WVDC32(pipe->conf, map->conf);
|
||||
|
||||
/* restore palette (gamma) */
|
||||
/*DRM_UDELAY(50000); */
|
||||
for (i = 0; i < 256; i++)
|
||||
PSB_WVDC32(pipe->palette[i], palette_reg + (i << 2));
|
||||
PSB_WVDC32(pipe->palette[i], map->palette + (i << 2));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -578,7 +462,7 @@ static const struct psb_offset mdfld_regmap[3] = {
|
|||
.size = DSPASIZE,
|
||||
.pos = DSPAPOS,
|
||||
.surf = DSPASURF,
|
||||
.addr = DSPABASE,
|
||||
.addr = MRST_DSPABASE,
|
||||
.status = PIPEASTAT,
|
||||
.linoff = DSPALINOFF,
|
||||
.tileoff = DSPATILEOFF,
|
||||
|
@ -600,13 +484,14 @@ static const struct psb_offset mdfld_regmap[3] = {
|
|||
.size = DSPBSIZE,
|
||||
.pos = DSPBPOS,
|
||||
.surf = DSPBSURF,
|
||||
.addr = DSPBBASE,
|
||||
.addr = MRST_DSPBBASE,
|
||||
.status = PIPEBSTAT,
|
||||
.linoff = DSPBLINOFF,
|
||||
.tileoff = DSPBTILEOFF,
|
||||
.palette = PALETTE_B,
|
||||
},
|
||||
{
|
||||
.fp0 = MRST_FPA0, /* This is what the old code did ?? */
|
||||
.cntr = DSPCCNTR,
|
||||
.conf = PIPECCONF,
|
||||
.src = PIPECSRC,
|
||||
|
@ -622,7 +507,7 @@ static const struct psb_offset mdfld_regmap[3] = {
|
|||
.size = DSPBSIZE,
|
||||
.pos = DSPCPOS,
|
||||
.surf = DSPCSURF,
|
||||
.addr = DSPCBASE,
|
||||
.addr = MDFLD_DSPCBASE,
|
||||
.status = PIPECSTAT,
|
||||
.linoff = DSPCLINOFF,
|
||||
.tileoff = DSPCTILEOFF,
|
||||
|
|
|
@ -605,6 +605,8 @@ int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector,
|
|||
struct mdfld_dsi_config *dsi_config =
|
||||
mdfld_dsi_get_config(dsi_connector);
|
||||
struct drm_device *dev = dsi_config->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
u32 mipi_val = 0;
|
||||
|
||||
if (!dsi_connector) {
|
||||
|
@ -632,21 +634,13 @@ int mdfld_dsi_pkg_sender_init(struct mdfld_dsi_connector *dsi_connector,
|
|||
pkg_sender->status = MDFLD_DSI_PKG_SENDER_FREE;
|
||||
|
||||
/*init regs*/
|
||||
if (pipe == 0) {
|
||||
pkg_sender->dpll_reg = MRST_DPLL_A;
|
||||
pkg_sender->dspcntr_reg = DSPACNTR;
|
||||
pkg_sender->pipeconf_reg = PIPEACONF;
|
||||
pkg_sender->dsplinoff_reg = DSPALINOFF;
|
||||
pkg_sender->dspsurf_reg = DSPASURF;
|
||||
pkg_sender->pipestat_reg = PIPEASTAT;
|
||||
} else if (pipe == 2) {
|
||||
pkg_sender->dpll_reg = MRST_DPLL_A;
|
||||
pkg_sender->dspcntr_reg = DSPCCNTR;
|
||||
pkg_sender->pipeconf_reg = PIPECCONF;
|
||||
pkg_sender->dsplinoff_reg = DSPCLINOFF;
|
||||
pkg_sender->dspsurf_reg = DSPCSURF;
|
||||
pkg_sender->pipestat_reg = PIPECSTAT;
|
||||
}
|
||||
/* FIXME: should just copy the regmap ptr ? */
|
||||
pkg_sender->dpll_reg = map->dpll;
|
||||
pkg_sender->dspcntr_reg = map->cntr;
|
||||
pkg_sender->pipeconf_reg = map->conf;
|
||||
pkg_sender->dsplinoff_reg = map->linoff;
|
||||
pkg_sender->dspsurf_reg = map->surf;
|
||||
pkg_sender->pipestat_reg = map->status;
|
||||
|
||||
pkg_sender->mipi_intr_stat_reg = MIPI_INTR_STAT_REG(pipe);
|
||||
pkg_sender->mipi_lp_gen_data_reg = MIPI_LP_GEN_DATA_REG(pipe);
|
||||
|
|
|
@ -50,17 +50,14 @@ struct mrst_clock_t {
|
|||
|
||||
void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
int count, temp;
|
||||
u32 pipeconf_reg = PIPEACONF;
|
||||
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
pipeconf_reg = PIPEBCONF;
|
||||
break;
|
||||
case 2:
|
||||
pipeconf_reg = PIPECCONF;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Illegal Pipe Number.\n");
|
||||
|
@ -73,7 +70,7 @@ void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe)
|
|||
|
||||
/* Wait for for the pipe disable to take effect. */
|
||||
for (count = 0; count < COUNT_MAX; count++) {
|
||||
temp = REG_READ(pipeconf_reg);
|
||||
temp = REG_READ(map->conf);
|
||||
if ((temp & PIPEACONF_PIPE_STATE) == 0)
|
||||
break;
|
||||
}
|
||||
|
@ -81,17 +78,14 @@ void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe)
|
|||
|
||||
void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe)
|
||||
{
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
int count, temp;
|
||||
u32 pipeconf_reg = PIPEACONF;
|
||||
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
pipeconf_reg = PIPEBCONF;
|
||||
break;
|
||||
case 2:
|
||||
pipeconf_reg = PIPECCONF;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Illegal Pipe Number.\n");
|
||||
|
@ -104,7 +98,7 @@ void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe)
|
|||
|
||||
/* Wait for for the pipe enable to take effect. */
|
||||
for (count = 0; count < COUNT_MAX; count++) {
|
||||
temp = REG_READ(pipeconf_reg);
|
||||
temp = REG_READ(map->conf);
|
||||
if ((temp & PIPEACONF_PIPE_STATE) == 1)
|
||||
break;
|
||||
}
|
||||
|
@ -189,15 +183,12 @@ static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
|
|||
struct drm_framebuffer *old_fb)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
/* struct drm_i915_master_private *master_priv; */
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
unsigned long start, offset;
|
||||
int dsplinoff = DSPALINOFF;
|
||||
int dspsurf = DSPASURF;
|
||||
int dspstride = DSPASTRIDE;
|
||||
int dspcntr_reg = DSPACNTR;
|
||||
u32 dspcntr;
|
||||
int ret;
|
||||
|
||||
|
@ -215,23 +206,7 @@ static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
dsplinoff = DSPALINOFF;
|
||||
break;
|
||||
case 1:
|
||||
dsplinoff = DSPBLINOFF;
|
||||
dspsurf = DSPBSURF;
|
||||
dspstride = DSPBSTRIDE;
|
||||
dspcntr_reg = DSPBCNTR;
|
||||
break;
|
||||
case 2:
|
||||
dsplinoff = DSPCLINOFF;
|
||||
dspsurf = DSPCSURF;
|
||||
dspstride = DSPCSTRIDE;
|
||||
dspcntr_reg = DSPCCNTR;
|
||||
break;
|
||||
default:
|
||||
if (pipe > 2) {
|
||||
DRM_ERROR("Illegal Pipe Number.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
@ -242,8 +217,8 @@ static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
|
|||
start = psbfb->gtt->offset;
|
||||
offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
|
||||
|
||||
REG_WRITE(dspstride, crtc->fb->pitches[0]);
|
||||
dspcntr = REG_READ(dspcntr_reg);
|
||||
REG_WRITE(map->stride, crtc->fb->pitches[0]);
|
||||
dspcntr = REG_READ(map->cntr);
|
||||
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
|
||||
|
||||
switch (crtc->fb->bits_per_pixel) {
|
||||
|
@ -261,14 +236,14 @@ static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
|
|||
dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
|
||||
break;
|
||||
}
|
||||
REG_WRITE(dspcntr_reg, dspcntr);
|
||||
REG_WRITE(map->cntr, dspcntr);
|
||||
|
||||
dev_dbg(dev->dev, "Writing base %08lX %08lX %d %d\n",
|
||||
start, offset, x, y);
|
||||
REG_WRITE(dsplinoff, offset);
|
||||
REG_READ(dsplinoff);
|
||||
REG_WRITE(dspsurf, start);
|
||||
REG_READ(dspsurf);
|
||||
REG_WRITE(map->linoff, offset);
|
||||
REG_READ(map->linoff);
|
||||
REG_WRITE(map->surf, start);
|
||||
REG_READ(map->surf);
|
||||
|
||||
gma_power_end(dev);
|
||||
|
||||
|
@ -281,78 +256,56 @@ static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
|
|||
*/
|
||||
void mdfld_disable_crtc(struct drm_device *dev, int pipe)
|
||||
{
|
||||
int dpll_reg = MRST_DPLL_A;
|
||||
int dspcntr_reg = DSPACNTR;
|
||||
int dspbase_reg = MRST_DSPABASE;
|
||||
int pipeconf_reg = PIPEACONF;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
u32 temp;
|
||||
|
||||
dev_dbg(dev->dev, "pipe = %d\n", pipe);
|
||||
|
||||
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
dpll_reg = MDFLD_DPLL_B;
|
||||
dspcntr_reg = DSPBCNTR;
|
||||
dspbase_reg = DSPBSURF;
|
||||
pipeconf_reg = PIPEBCONF;
|
||||
break;
|
||||
case 2:
|
||||
dpll_reg = MRST_DPLL_A;
|
||||
dspcntr_reg = DSPCCNTR;
|
||||
dspbase_reg = MDFLD_DSPCBASE;
|
||||
pipeconf_reg = PIPECCONF;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Illegal Pipe Number.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (pipe != 1)
|
||||
mdfld_dsi_gen_fifo_ready(dev, MIPI_GEN_FIFO_STAT_REG(pipe),
|
||||
HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
|
||||
|
||||
/* Disable display plane */
|
||||
temp = REG_READ(dspcntr_reg);
|
||||
temp = REG_READ(map->cntr);
|
||||
if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
|
||||
REG_WRITE(dspcntr_reg,
|
||||
REG_WRITE(map->cntr,
|
||||
temp & ~DISPLAY_PLANE_ENABLE);
|
||||
/* Flush the plane changes */
|
||||
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
|
||||
REG_READ(dspbase_reg);
|
||||
REG_WRITE(map->base, REG_READ(map->base));
|
||||
REG_READ(map->base);
|
||||
}
|
||||
|
||||
/* FIXME_JLIU7 MDFLD_PO revisit */
|
||||
|
||||
/* Next, disable display pipes */
|
||||
temp = REG_READ(pipeconf_reg);
|
||||
temp = REG_READ(map->conf);
|
||||
if ((temp & PIPEACONF_ENABLE) != 0) {
|
||||
temp &= ~PIPEACONF_ENABLE;
|
||||
temp |= PIPECONF_PLANE_OFF | PIPECONF_CURSOR_OFF;
|
||||
REG_WRITE(pipeconf_reg, temp);
|
||||
REG_READ(pipeconf_reg);
|
||||
REG_WRITE(map->conf, temp);
|
||||
REG_READ(map->conf);
|
||||
|
||||
/* Wait for for the pipe disable to take effect. */
|
||||
mdfldWaitForPipeDisable(dev, pipe);
|
||||
}
|
||||
|
||||
temp = REG_READ(dpll_reg);
|
||||
temp = REG_READ(map->dpll);
|
||||
if (temp & DPLL_VCO_ENABLE) {
|
||||
if ((pipe != 1 &&
|
||||
!((REG_READ(PIPEACONF) | REG_READ(PIPECCONF))
|
||||
& PIPEACONF_ENABLE)) || pipe == 1) {
|
||||
temp &= ~(DPLL_VCO_ENABLE);
|
||||
REG_WRITE(dpll_reg, temp);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, temp);
|
||||
REG_READ(map->dpll);
|
||||
/* Wait for the clocks to turn off. */
|
||||
/* FIXME_MDFLD PO may need more delay */
|
||||
udelay(500);
|
||||
|
||||
if (!(temp & MDFLD_PWR_GATE_EN)) {
|
||||
/* gating power of DPLL */
|
||||
REG_WRITE(dpll_reg, temp | MDFLD_PWR_GATE_EN);
|
||||
REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN);
|
||||
/* FIXME_MDFLD PO - change 500 to 1 after PO */
|
||||
udelay(5000);
|
||||
}
|
||||
|
@ -373,41 +326,15 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
int dpll_reg = MRST_DPLL_A;
|
||||
int dspcntr_reg = DSPACNTR;
|
||||
int dspbase_reg = MRST_DSPABASE;
|
||||
int pipeconf_reg = PIPEACONF;
|
||||
u32 pipestat_reg = PIPEASTAT;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
u32 pipeconf = dev_priv->pipeconf[pipe];
|
||||
u32 temp;
|
||||
int timeout = 0;
|
||||
|
||||
dev_dbg(dev->dev, "mode = %d, pipe = %d\n", mode, pipe);
|
||||
|
||||
/* FIXME_JLIU7 MDFLD_PO replaced w/ the following function */
|
||||
/* mdfld_dbi_dpms (struct drm_device *dev, int pipe, bool enabled) */
|
||||
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
dpll_reg = DPLL_B;
|
||||
dspcntr_reg = DSPBCNTR;
|
||||
dspbase_reg = MRST_DSPBBASE;
|
||||
pipeconf_reg = PIPEBCONF;
|
||||
dpll_reg = MDFLD_DPLL_B;
|
||||
break;
|
||||
case 2:
|
||||
dpll_reg = MRST_DPLL_A;
|
||||
dspcntr_reg = DSPCCNTR;
|
||||
dspbase_reg = MDFLD_DSPCBASE;
|
||||
pipeconf_reg = PIPECCONF;
|
||||
pipestat_reg = PIPECSTAT;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Illegal Pipe Number.\n");
|
||||
return;
|
||||
}
|
||||
/* Note: Old code uses pipe a stat for pipe b but that appears
|
||||
to be a bug */
|
||||
|
||||
if (!gma_power_begin(dev, true))
|
||||
return;
|
||||
|
@ -420,25 +347,25 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|||
case DRM_MODE_DPMS_STANDBY:
|
||||
case DRM_MODE_DPMS_SUSPEND:
|
||||
/* Enable the DPLL */
|
||||
temp = REG_READ(dpll_reg);
|
||||
temp = REG_READ(map->dpll);
|
||||
|
||||
if ((temp & DPLL_VCO_ENABLE) == 0) {
|
||||
/* When ungating power of DPLL, needs to wait 0.5us
|
||||
before enable the VCO */
|
||||
if (temp & MDFLD_PWR_GATE_EN) {
|
||||
temp &= ~MDFLD_PWR_GATE_EN;
|
||||
REG_WRITE(dpll_reg, temp);
|
||||
REG_WRITE(map->dpll, temp);
|
||||
/* FIXME_MDFLD PO - change 500 to 1 after PO */
|
||||
udelay(500);
|
||||
}
|
||||
|
||||
REG_WRITE(dpll_reg, temp);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, temp);
|
||||
REG_READ(map->dpll);
|
||||
/* FIXME_MDFLD PO - change 500 to 1 after PO */
|
||||
udelay(500);
|
||||
|
||||
REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
|
||||
REG_READ(map->dpll);
|
||||
|
||||
/**
|
||||
* wait for DSI PLL to lock
|
||||
|
@ -446,25 +373,25 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|||
* since both MIPI pipes share the same PLL.
|
||||
*/
|
||||
while ((pipe != 2) && (timeout < 20000) &&
|
||||
!(REG_READ(pipeconf_reg) & PIPECONF_DSIPLL_LOCK)) {
|
||||
!(REG_READ(map->conf) & PIPECONF_DSIPLL_LOCK)) {
|
||||
udelay(150);
|
||||
timeout++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable the plane */
|
||||
temp = REG_READ(dspcntr_reg);
|
||||
temp = REG_READ(map->cntr);
|
||||
if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
|
||||
REG_WRITE(dspcntr_reg,
|
||||
REG_WRITE(map->cntr,
|
||||
temp | DISPLAY_PLANE_ENABLE);
|
||||
/* Flush the plane changes */
|
||||
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
|
||||
REG_WRITE(map->base, REG_READ(map->base));
|
||||
}
|
||||
|
||||
/* Enable the pipe */
|
||||
temp = REG_READ(pipeconf_reg);
|
||||
temp = REG_READ(map->conf);
|
||||
if ((temp & PIPEACONF_ENABLE) == 0) {
|
||||
REG_WRITE(pipeconf_reg, pipeconf);
|
||||
REG_WRITE(map->conf, pipeconf);
|
||||
|
||||
/* Wait for for the pipe enable to take effect. */
|
||||
mdfldWaitForPipeEnable(dev, pipe);
|
||||
|
@ -473,39 +400,39 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|||
/*workaround for sighting 3741701 Random X blank display*/
|
||||
/*perform w/a in video mode only on pipe A or C*/
|
||||
if (pipe == 0 || pipe == 2) {
|
||||
REG_WRITE(pipestat_reg, REG_READ(pipestat_reg));
|
||||
REG_WRITE(map->status, REG_READ(map->status));
|
||||
msleep(100);
|
||||
if (PIPE_VBLANK_STATUS & REG_READ(pipestat_reg))
|
||||
if (PIPE_VBLANK_STATUS & REG_READ(map->status))
|
||||
dev_dbg(dev->dev, "OK");
|
||||
else {
|
||||
dev_dbg(dev->dev, "STUCK!!!!");
|
||||
/*shutdown controller*/
|
||||
temp = REG_READ(dspcntr_reg);
|
||||
REG_WRITE(dspcntr_reg,
|
||||
temp = REG_READ(map->cntr);
|
||||
REG_WRITE(map->cntr,
|
||||
temp & ~DISPLAY_PLANE_ENABLE);
|
||||
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
|
||||
REG_WRITE(map->base, REG_READ(map->base));
|
||||
/*mdfld_dsi_dpi_shut_down(dev, pipe);*/
|
||||
REG_WRITE(0xb048, 1);
|
||||
msleep(100);
|
||||
temp = REG_READ(pipeconf_reg);
|
||||
temp = REG_READ(map->conf);
|
||||
temp &= ~PIPEACONF_ENABLE;
|
||||
REG_WRITE(pipeconf_reg, temp);
|
||||
REG_WRITE(map->conf, temp);
|
||||
msleep(100); /*wait for pipe disable*/
|
||||
REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 0);
|
||||
msleep(100);
|
||||
REG_WRITE(0xb004, REG_READ(0xb004));
|
||||
/* try to bring the controller back up again*/
|
||||
REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 1);
|
||||
temp = REG_READ(dspcntr_reg);
|
||||
REG_WRITE(dspcntr_reg,
|
||||
temp = REG_READ(map->cntr);
|
||||
REG_WRITE(map->cntr,
|
||||
temp | DISPLAY_PLANE_ENABLE);
|
||||
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
|
||||
REG_WRITE(map->base, REG_READ(map->base));
|
||||
/*mdfld_dsi_dpi_turn_on(dev, pipe);*/
|
||||
REG_WRITE(0xb048, 2);
|
||||
msleep(100);
|
||||
temp = REG_READ(pipeconf_reg);
|
||||
temp = REG_READ(map->conf);
|
||||
temp |= PIPEACONF_ENABLE;
|
||||
REG_WRITE(pipeconf_reg, temp);
|
||||
REG_WRITE(map->conf, temp);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -529,35 +456,35 @@ static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|||
REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
|
||||
|
||||
/* Disable display plane */
|
||||
temp = REG_READ(dspcntr_reg);
|
||||
temp = REG_READ(map->cntr);
|
||||
if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
|
||||
REG_WRITE(dspcntr_reg,
|
||||
REG_WRITE(map->cntr,
|
||||
temp & ~DISPLAY_PLANE_ENABLE);
|
||||
/* Flush the plane changes */
|
||||
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
|
||||
REG_READ(dspbase_reg);
|
||||
REG_WRITE(map->base, REG_READ(map->base));
|
||||
REG_READ(map->base);
|
||||
}
|
||||
|
||||
/* Next, disable display pipes */
|
||||
temp = REG_READ(pipeconf_reg);
|
||||
temp = REG_READ(map->conf);
|
||||
if ((temp & PIPEACONF_ENABLE) != 0) {
|
||||
temp &= ~PIPEACONF_ENABLE;
|
||||
temp |= PIPECONF_PLANE_OFF | PIPECONF_CURSOR_OFF;
|
||||
REG_WRITE(pipeconf_reg, temp);
|
||||
REG_READ(pipeconf_reg);
|
||||
REG_WRITE(map->conf, temp);
|
||||
REG_READ(map->conf);
|
||||
|
||||
/* Wait for for the pipe disable to take effect. */
|
||||
mdfldWaitForPipeDisable(dev, pipe);
|
||||
}
|
||||
|
||||
temp = REG_READ(dpll_reg);
|
||||
temp = REG_READ(map->dpll);
|
||||
if (temp & DPLL_VCO_ENABLE) {
|
||||
if ((pipe != 1 && !((REG_READ(PIPEACONF)
|
||||
| REG_READ(PIPECCONF)) & PIPEACONF_ENABLE))
|
||||
|| pipe == 1) {
|
||||
temp &= ~(DPLL_VCO_ENABLE);
|
||||
REG_WRITE(dpll_reg, temp);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, temp);
|
||||
REG_READ(map->dpll);
|
||||
/* Wait for the clocks to turn off. */
|
||||
/* FIXME_MDFLD PO may need more delay */
|
||||
udelay(500);
|
||||
|
@ -764,21 +691,7 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
|
|||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
int fp_reg = MRST_FPA0;
|
||||
int dpll_reg = MRST_DPLL_A;
|
||||
int dspcntr_reg = DSPACNTR;
|
||||
int pipeconf_reg = PIPEACONF;
|
||||
int htot_reg = HTOTAL_A;
|
||||
int hblank_reg = HBLANK_A;
|
||||
int hsync_reg = HSYNC_A;
|
||||
int vtot_reg = VTOTAL_A;
|
||||
int vblank_reg = VBLANK_A;
|
||||
int vsync_reg = VSYNC_A;
|
||||
int dspsize_reg = DSPASIZE;
|
||||
int dsppos_reg = DSPAPOS;
|
||||
int pipesrc_reg = PIPEASRC;
|
||||
u32 *pipeconf = &dev_priv->pipeconf[pipe];
|
||||
u32 *dspcntr = &dev_priv->dspcntr[pipe];
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
int refclk = 0;
|
||||
int clk_n = 0, clk_p2 = 0, clk_byte = 1, clk = 0, m_conv = 0,
|
||||
clk_tmp = 0;
|
||||
|
@ -806,45 +719,6 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
|
|||
}
|
||||
#endif
|
||||
|
||||
switch (pipe) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
fp_reg = FPB0;
|
||||
dpll_reg = DPLL_B;
|
||||
dspcntr_reg = DSPBCNTR;
|
||||
pipeconf_reg = PIPEBCONF;
|
||||
htot_reg = HTOTAL_B;
|
||||
hblank_reg = HBLANK_B;
|
||||
hsync_reg = HSYNC_B;
|
||||
vtot_reg = VTOTAL_B;
|
||||
vblank_reg = VBLANK_B;
|
||||
vsync_reg = VSYNC_B;
|
||||
dspsize_reg = DSPBSIZE;
|
||||
dsppos_reg = DSPBPOS;
|
||||
pipesrc_reg = PIPEBSRC;
|
||||
fp_reg = MDFLD_DPLL_DIV0;
|
||||
dpll_reg = MDFLD_DPLL_B;
|
||||
break;
|
||||
case 2:
|
||||
dpll_reg = MRST_DPLL_A;
|
||||
dspcntr_reg = DSPCCNTR;
|
||||
pipeconf_reg = PIPECCONF;
|
||||
htot_reg = HTOTAL_C;
|
||||
hblank_reg = HBLANK_C;
|
||||
hsync_reg = HSYNC_C;
|
||||
vtot_reg = VTOTAL_C;
|
||||
vblank_reg = VBLANK_C;
|
||||
vsync_reg = VSYNC_C;
|
||||
dspsize_reg = DSPCSIZE;
|
||||
dsppos_reg = DSPCPOS;
|
||||
pipesrc_reg = PIPECSRC;
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Illegal Pipe Number.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
ret = check_fb(crtc->fb);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
@ -929,21 +803,21 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
|
|||
* contained within the displayable area of the screen image
|
||||
* (frame buffer).
|
||||
*/
|
||||
REG_WRITE(dspsize_reg, ((min(mode->crtc_vdisplay, adjusted_mode->crtc_vdisplay) - 1) << 16)
|
||||
REG_WRITE(map->size, ((min(mode->crtc_vdisplay, adjusted_mode->crtc_vdisplay) - 1) << 16)
|
||||
| (min(mode->crtc_hdisplay, adjusted_mode->crtc_hdisplay) - 1));
|
||||
/* Set the CRTC with encoder mode. */
|
||||
REG_WRITE(pipesrc_reg, ((mode->crtc_hdisplay - 1) << 16)
|
||||
REG_WRITE(map->src, ((mode->crtc_hdisplay - 1) << 16)
|
||||
| (mode->crtc_vdisplay - 1));
|
||||
} else {
|
||||
REG_WRITE(dspsize_reg,
|
||||
REG_WRITE(map->size,
|
||||
((mode->crtc_vdisplay - 1) << 16) |
|
||||
(mode->crtc_hdisplay - 1));
|
||||
REG_WRITE(pipesrc_reg,
|
||||
REG_WRITE(map->src,
|
||||
((mode->crtc_hdisplay - 1) << 16) |
|
||||
(mode->crtc_vdisplay - 1));
|
||||
}
|
||||
|
||||
REG_WRITE(dsppos_reg, 0);
|
||||
REG_WRITE(map->pos, 0);
|
||||
|
||||
if (psb_intel_encoder)
|
||||
drm_connector_property_get_value(connector,
|
||||
|
@ -961,34 +835,34 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
|
|||
offsetY = (adjusted_mode->crtc_vdisplay -
|
||||
mode->crtc_vdisplay) / 2;
|
||||
|
||||
REG_WRITE(htot_reg, (mode->crtc_hdisplay - 1) |
|
||||
REG_WRITE(map->htotal, (mode->crtc_hdisplay - 1) |
|
||||
((adjusted_mode->crtc_htotal - 1) << 16));
|
||||
REG_WRITE(vtot_reg, (mode->crtc_vdisplay - 1) |
|
||||
REG_WRITE(map->vtotal, (mode->crtc_vdisplay - 1) |
|
||||
((adjusted_mode->crtc_vtotal - 1) << 16));
|
||||
REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start -
|
||||
REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start -
|
||||
offsetX - 1) |
|
||||
((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16));
|
||||
REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start -
|
||||
REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start -
|
||||
offsetX - 1) |
|
||||
((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16));
|
||||
REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start -
|
||||
REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start -
|
||||
offsetY - 1) |
|
||||
((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16));
|
||||
REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start -
|
||||
REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start -
|
||||
offsetY - 1) |
|
||||
((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16));
|
||||
} else {
|
||||
REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
|
||||
REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
|
||||
((adjusted_mode->crtc_htotal - 1) << 16));
|
||||
REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
|
||||
REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
|
||||
((adjusted_mode->crtc_vtotal - 1) << 16));
|
||||
REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
|
||||
REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
|
||||
((adjusted_mode->crtc_hblank_end - 1) << 16));
|
||||
REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
|
||||
REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
|
||||
((adjusted_mode->crtc_hsync_end - 1) << 16));
|
||||
REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
|
||||
REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
|
||||
((adjusted_mode->crtc_vblank_end - 1) << 16));
|
||||
REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
|
||||
REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
|
||||
((adjusted_mode->crtc_vsync_end - 1) << 16));
|
||||
}
|
||||
|
||||
|
@ -1000,12 +874,12 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
|
|||
}
|
||||
|
||||
/* setup pipeconf */
|
||||
*pipeconf = PIPEACONF_ENABLE; /* FIXME_JLIU7 REG_READ(pipeconf_reg); */
|
||||
dev_priv->pipeconf[pipe] = PIPEACONF_ENABLE; /* FIXME_JLIU7 REG_READ(pipeconf_reg); */
|
||||
|
||||
/* Set up the display plane register */
|
||||
*dspcntr = REG_READ(dspcntr_reg);
|
||||
*dspcntr |= pipe << DISPPLANE_SEL_PIPE_POS;
|
||||
*dspcntr |= DISPLAY_PLANE_ENABLE;
|
||||
dev_priv->dspcntr[pipe] = REG_READ(map->cntr);
|
||||
dev_priv->dspcntr[pipe] |= pipe << DISPPLANE_SEL_PIPE_POS;
|
||||
dev_priv->dspcntr[pipe] |= DISPLAY_PLANE_ENABLE;
|
||||
|
||||
if (is_mipi2)
|
||||
goto mrst_crtc_mode_set_exit;
|
||||
|
@ -1070,21 +944,21 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
|
|||
clock.p1, m_conv);
|
||||
}
|
||||
|
||||
dpll = REG_READ(dpll_reg);
|
||||
dpll = REG_READ(map->dpll);
|
||||
|
||||
if (dpll & DPLL_VCO_ENABLE) {
|
||||
dpll &= ~DPLL_VCO_ENABLE;
|
||||
REG_WRITE(dpll_reg, dpll);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, dpll);
|
||||
REG_READ(map->dpll);
|
||||
|
||||
/* FIXME jliu7 check the DPLL lock bit PIPEACONF[29] */
|
||||
/* FIXME_MDFLD PO - change 500 to 1 after PO */
|
||||
udelay(500);
|
||||
|
||||
/* reset M1, N1 & P1 */
|
||||
REG_WRITE(fp_reg, 0);
|
||||
REG_WRITE(map->fp0, 0);
|
||||
dpll &= ~MDFLD_P1_MASK;
|
||||
REG_WRITE(dpll_reg, dpll);
|
||||
REG_WRITE(map->dpll, dpll);
|
||||
/* FIXME_MDFLD PO - change 500 to 1 after PO */
|
||||
udelay(500);
|
||||
}
|
||||
|
@ -1093,7 +967,7 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
|
|||
* enable the VCO */
|
||||
if (dpll & MDFLD_PWR_GATE_EN) {
|
||||
dpll &= ~MDFLD_PWR_GATE_EN;
|
||||
REG_WRITE(dpll_reg, dpll);
|
||||
REG_WRITE(map->dpll, dpll);
|
||||
/* FIXME_MDFLD PO - change 500 to 1 after PO */
|
||||
udelay(500);
|
||||
}
|
||||
|
@ -1134,18 +1008,18 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
|
|||
fp = 0x000000c1;
|
||||
}
|
||||
|
||||
REG_WRITE(fp_reg, fp);
|
||||
REG_WRITE(dpll_reg, dpll);
|
||||
REG_WRITE(map->fp0, fp);
|
||||
REG_WRITE(map->dpll, dpll);
|
||||
/* FIXME_MDFLD PO - change 500 to 1 after PO */
|
||||
udelay(500);
|
||||
|
||||
dpll |= DPLL_VCO_ENABLE;
|
||||
REG_WRITE(dpll_reg, dpll);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, dpll);
|
||||
REG_READ(map->dpll);
|
||||
|
||||
/* wait for DSI PLL to lock */
|
||||
while (timeout < 20000 &&
|
||||
!(REG_READ(pipeconf_reg) & PIPECONF_DSIPLL_LOCK)) {
|
||||
!(REG_READ(map->conf) & PIPECONF_DSIPLL_LOCK)) {
|
||||
udelay(150);
|
||||
timeout++;
|
||||
}
|
||||
|
@ -1155,11 +1029,11 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
|
|||
|
||||
dev_dbg(dev->dev, "is_mipi = 0x%x\n", is_mipi);
|
||||
|
||||
REG_WRITE(pipeconf_reg, *pipeconf);
|
||||
REG_READ(pipeconf_reg);
|
||||
REG_WRITE(map->conf, dev_priv->pipeconf[pipe]);
|
||||
REG_READ(map->conf);
|
||||
|
||||
/* Wait for for the pipe enable to take effect. */
|
||||
REG_WRITE(dspcntr_reg, *dspcntr);
|
||||
REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]);
|
||||
psb_intel_wait_for_vblank(dev);
|
||||
|
||||
mrst_crtc_mode_set_exit:
|
||||
|
|
|
@ -162,12 +162,10 @@ mrstFindBestPLL(struct drm_crtc *crtc, int target, int refclk,
|
|||
static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B;
|
||||
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
|
||||
int dspbase_reg = (pipe == 0) ? MRST_DSPABASE : DSPBBASE;
|
||||
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
u32 temp;
|
||||
|
||||
if (!gma_power_begin(dev, true))
|
||||
|
@ -181,32 +179,32 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|||
case DRM_MODE_DPMS_STANDBY:
|
||||
case DRM_MODE_DPMS_SUSPEND:
|
||||
/* Enable the DPLL */
|
||||
temp = REG_READ(dpll_reg);
|
||||
temp = REG_READ(map->dpll);
|
||||
if ((temp & DPLL_VCO_ENABLE) == 0) {
|
||||
REG_WRITE(dpll_reg, temp);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, temp);
|
||||
REG_READ(map->dpll);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
|
||||
REG_READ(map->dpll);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
|
||||
REG_READ(map->dpll);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
}
|
||||
/* Enable the pipe */
|
||||
temp = REG_READ(pipeconf_reg);
|
||||
temp = REG_READ(map->conf);
|
||||
if ((temp & PIPEACONF_ENABLE) == 0)
|
||||
REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
|
||||
REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
|
||||
/* Enable the plane */
|
||||
temp = REG_READ(dspcntr_reg);
|
||||
temp = REG_READ(map->cntr);
|
||||
if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
|
||||
REG_WRITE(dspcntr_reg,
|
||||
REG_WRITE(map->cntr,
|
||||
temp | DISPLAY_PLANE_ENABLE);
|
||||
/* Flush the plane changes */
|
||||
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
|
||||
REG_WRITE(map->base, REG_READ(map->base));
|
||||
}
|
||||
|
||||
psb_intel_crtc_load_lut(crtc);
|
||||
|
@ -223,28 +221,28 @@ static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|||
/* Disable the VGA plane that we never use */
|
||||
REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
|
||||
/* Disable display plane */
|
||||
temp = REG_READ(dspcntr_reg);
|
||||
temp = REG_READ(map->cntr);
|
||||
if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
|
||||
REG_WRITE(dspcntr_reg,
|
||||
REG_WRITE(map->cntr,
|
||||
temp & ~DISPLAY_PLANE_ENABLE);
|
||||
/* Flush the plane changes */
|
||||
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
|
||||
REG_READ(dspbase_reg);
|
||||
REG_WRITE(map->base, REG_READ(map->base));
|
||||
REG_READ(map->base);
|
||||
}
|
||||
|
||||
/* Next, disable display pipes */
|
||||
temp = REG_READ(pipeconf_reg);
|
||||
temp = REG_READ(map->conf);
|
||||
if ((temp & PIPEACONF_ENABLE) != 0) {
|
||||
REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
|
||||
REG_READ(pipeconf_reg);
|
||||
REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
|
||||
REG_READ(map->conf);
|
||||
}
|
||||
/* Wait for for the pipe disable to take effect. */
|
||||
psb_intel_wait_for_vblank(dev);
|
||||
|
||||
temp = REG_READ(dpll_reg);
|
||||
temp = REG_READ(map->dpll);
|
||||
if ((temp & DPLL_VCO_ENABLE) != 0) {
|
||||
REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
|
||||
REG_READ(map->dpll);
|
||||
}
|
||||
|
||||
/* Wait for the clocks to turn off. */
|
||||
|
@ -292,17 +290,7 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
|
|||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
int fp_reg = (pipe == 0) ? MRST_FPA0 : FPB0;
|
||||
int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B;
|
||||
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
|
||||
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
|
||||
int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
|
||||
int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
|
||||
int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
|
||||
int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
|
||||
int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
|
||||
int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
|
||||
int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
int refclk = 0;
|
||||
struct oaktrail_clock_t clock;
|
||||
u32 dpll = 0, fp = 0, dspcntr, pipeconf;
|
||||
|
@ -350,7 +338,7 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
|
|||
if (oaktrail_panel_fitter_pipe(dev) == pipe)
|
||||
REG_WRITE(PFIT_CONTROL, 0);
|
||||
|
||||
REG_WRITE(pipesrc_reg,
|
||||
REG_WRITE(map->src,
|
||||
((mode->crtc_hdisplay - 1) << 16) |
|
||||
(mode->crtc_vdisplay - 1));
|
||||
|
||||
|
@ -369,34 +357,34 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
|
|||
offsetY = (adjusted_mode->crtc_vdisplay -
|
||||
mode->crtc_vdisplay) / 2;
|
||||
|
||||
REG_WRITE(htot_reg, (mode->crtc_hdisplay - 1) |
|
||||
REG_WRITE(map->htotal, (mode->crtc_hdisplay - 1) |
|
||||
((adjusted_mode->crtc_htotal - 1) << 16));
|
||||
REG_WRITE(vtot_reg, (mode->crtc_vdisplay - 1) |
|
||||
REG_WRITE(map->vtotal, (mode->crtc_vdisplay - 1) |
|
||||
((adjusted_mode->crtc_vtotal - 1) << 16));
|
||||
REG_WRITE(hblank_reg,
|
||||
REG_WRITE(map->hblank,
|
||||
(adjusted_mode->crtc_hblank_start - offsetX - 1) |
|
||||
((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16));
|
||||
REG_WRITE(hsync_reg,
|
||||
REG_WRITE(map->hsync,
|
||||
(adjusted_mode->crtc_hsync_start - offsetX - 1) |
|
||||
((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16));
|
||||
REG_WRITE(vblank_reg,
|
||||
REG_WRITE(map->vblank,
|
||||
(adjusted_mode->crtc_vblank_start - offsetY - 1) |
|
||||
((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16));
|
||||
REG_WRITE(vsync_reg,
|
||||
REG_WRITE(map->vsync,
|
||||
(adjusted_mode->crtc_vsync_start - offsetY - 1) |
|
||||
((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16));
|
||||
} else {
|
||||
REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
|
||||
REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
|
||||
((adjusted_mode->crtc_htotal - 1) << 16));
|
||||
REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
|
||||
REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
|
||||
((adjusted_mode->crtc_vtotal - 1) << 16));
|
||||
REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
|
||||
REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
|
||||
((adjusted_mode->crtc_hblank_end - 1) << 16));
|
||||
REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
|
||||
REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
|
||||
((adjusted_mode->crtc_hsync_end - 1) << 16));
|
||||
REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
|
||||
REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
|
||||
((adjusted_mode->crtc_vblank_end - 1) << 16));
|
||||
REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
|
||||
REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
|
||||
((adjusted_mode->crtc_vsync_end - 1) << 16));
|
||||
}
|
||||
|
||||
|
@ -408,10 +396,10 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
|
|||
}
|
||||
|
||||
/* setup pipeconf */
|
||||
pipeconf = REG_READ(pipeconf_reg);
|
||||
pipeconf = REG_READ(map->conf);
|
||||
|
||||
/* Set up the display plane register */
|
||||
dspcntr = REG_READ(dspcntr_reg);
|
||||
dspcntr = REG_READ(map->cntr);
|
||||
dspcntr |= DISPPLANE_GAMMA_ENABLE;
|
||||
|
||||
if (pipe == 0)
|
||||
|
@ -467,30 +455,30 @@ static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
|
|||
mrstPrintPll("chosen", &clock);
|
||||
|
||||
if (dpll & DPLL_VCO_ENABLE) {
|
||||
REG_WRITE(fp_reg, fp);
|
||||
REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->fp0, fp);
|
||||
REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
|
||||
REG_READ(map->dpll);
|
||||
/* Check the DPLLA lock bit PIPEACONF[29] */
|
||||
udelay(150);
|
||||
}
|
||||
|
||||
REG_WRITE(fp_reg, fp);
|
||||
REG_WRITE(dpll_reg, dpll);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->fp0, fp);
|
||||
REG_WRITE(map->dpll, dpll);
|
||||
REG_READ(map->dpll);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
|
||||
/* write it again -- the BIOS does, after all */
|
||||
REG_WRITE(dpll_reg, dpll);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, dpll);
|
||||
REG_READ(map->dpll);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
|
||||
REG_WRITE(pipeconf_reg, pipeconf);
|
||||
REG_READ(pipeconf_reg);
|
||||
REG_WRITE(map->conf, pipeconf);
|
||||
REG_READ(map->conf);
|
||||
psb_intel_wait_for_vblank(dev);
|
||||
|
||||
REG_WRITE(dspcntr_reg, dspcntr);
|
||||
REG_WRITE(map->cntr, dspcntr);
|
||||
psb_intel_wait_for_vblank(dev);
|
||||
|
||||
oaktrail_crtc_mode_set_exit:
|
||||
|
@ -509,15 +497,13 @@ static int oaktrail_pipe_set_base(struct drm_crtc *crtc,
|
|||
int x, int y, struct drm_framebuffer *old_fb)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
unsigned long start, offset;
|
||||
|
||||
int dspbase = (pipe == 0 ? DSPALINOFF : DSPBBASE);
|
||||
int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
|
||||
int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
|
||||
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
|
||||
u32 dspcntr;
|
||||
int ret = 0;
|
||||
|
||||
|
@ -533,9 +519,9 @@ static int oaktrail_pipe_set_base(struct drm_crtc *crtc,
|
|||
start = psbfb->gtt->offset;
|
||||
offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
|
||||
|
||||
REG_WRITE(dspstride, crtc->fb->pitches[0]);
|
||||
REG_WRITE(map->stride, crtc->fb->pitches[0]);
|
||||
|
||||
dspcntr = REG_READ(dspcntr_reg);
|
||||
dspcntr = REG_READ(map->cntr);
|
||||
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
|
||||
|
||||
switch (crtc->fb->bits_per_pixel) {
|
||||
|
@ -557,12 +543,12 @@ static int oaktrail_pipe_set_base(struct drm_crtc *crtc,
|
|||
ret = -EINVAL;
|
||||
goto pipe_set_base_exit;
|
||||
}
|
||||
REG_WRITE(dspcntr_reg, dspcntr);
|
||||
REG_WRITE(map->cntr, dspcntr);
|
||||
|
||||
REG_WRITE(dspbase, offset);
|
||||
REG_READ(dspbase);
|
||||
REG_WRITE(dspsurf, start);
|
||||
REG_READ(dspsurf);
|
||||
REG_WRITE(map->base, offset);
|
||||
REG_READ(map->base);
|
||||
REG_WRITE(map->surf, start);
|
||||
REG_READ(map->surf);
|
||||
|
||||
pipe_set_base_exit:
|
||||
gma_power_end(dev);
|
||||
|
|
|
@ -475,7 +475,7 @@ static const struct psb_offset oaktrail_regmap[2] = {
|
|||
.size = DSPASIZE,
|
||||
.pos = DSPAPOS,
|
||||
.surf = DSPASURF,
|
||||
.addr = DSPABASE,
|
||||
.addr = MRST_DSPABASE,
|
||||
.status = PIPEASTAT,
|
||||
.linoff = DSPALINOFF,
|
||||
.tileoff = DSPATILEOFF,
|
||||
|
|
|
@ -337,15 +337,12 @@ static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
|
|||
int x, int y, struct drm_framebuffer *old_fb)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
/* struct drm_i915_master_private *master_priv; */
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
unsigned long start, offset;
|
||||
int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
|
||||
int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
|
||||
int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
|
||||
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
|
||||
u32 dspcntr;
|
||||
int ret = 0;
|
||||
|
||||
|
@ -367,9 +364,9 @@ static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
|
|||
|
||||
offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
|
||||
|
||||
REG_WRITE(dspstride, crtc->fb->pitches[0]);
|
||||
REG_WRITE(map->stride, crtc->fb->pitches[0]);
|
||||
|
||||
dspcntr = REG_READ(dspcntr_reg);
|
||||
dspcntr = REG_READ(map->cntr);
|
||||
dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
|
||||
|
||||
switch (crtc->fb->bits_per_pixel) {
|
||||
|
@ -392,18 +389,10 @@ static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
|
|||
psb_gtt_unpin(psbfb->gtt);
|
||||
goto psb_intel_pipe_set_base_exit;
|
||||
}
|
||||
REG_WRITE(dspcntr_reg, dspcntr);
|
||||
REG_WRITE(map->cntr, dspcntr);
|
||||
|
||||
|
||||
if (0 /* FIXMEAC - check what PSB needs */) {
|
||||
REG_WRITE(dspbase, offset);
|
||||
REG_READ(dspbase);
|
||||
REG_WRITE(dspsurf, start);
|
||||
REG_READ(dspsurf);
|
||||
} else {
|
||||
REG_WRITE(dspbase, start + offset);
|
||||
REG_READ(dspbase);
|
||||
}
|
||||
REG_WRITE(map->base, start + offset);
|
||||
REG_READ(map->base);
|
||||
|
||||
psb_intel_pipe_cleaner:
|
||||
/* If there was a previous display we can now unpin it */
|
||||
|
@ -424,14 +413,10 @@ static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
|
|||
static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
/* struct drm_i915_master_private *master_priv; */
|
||||
/* struct drm_i915_private *dev_priv = dev->dev_private; */
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
|
||||
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
|
||||
int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE;
|
||||
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
u32 temp;
|
||||
|
||||
/* XXX: When our outputs are all unaware of DPMS modes other than off
|
||||
|
@ -442,34 +427,34 @@ static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|||
case DRM_MODE_DPMS_STANDBY:
|
||||
case DRM_MODE_DPMS_SUSPEND:
|
||||
/* Enable the DPLL */
|
||||
temp = REG_READ(dpll_reg);
|
||||
temp = REG_READ(map->dpll);
|
||||
if ((temp & DPLL_VCO_ENABLE) == 0) {
|
||||
REG_WRITE(dpll_reg, temp);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, temp);
|
||||
REG_READ(map->dpll);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
|
||||
REG_READ(map->dpll);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
|
||||
REG_READ(map->dpll);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
}
|
||||
|
||||
/* Enable the pipe */
|
||||
temp = REG_READ(pipeconf_reg);
|
||||
temp = REG_READ(map->conf);
|
||||
if ((temp & PIPEACONF_ENABLE) == 0)
|
||||
REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
|
||||
REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
|
||||
|
||||
/* Enable the plane */
|
||||
temp = REG_READ(dspcntr_reg);
|
||||
temp = REG_READ(map->cntr);
|
||||
if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
|
||||
REG_WRITE(dspcntr_reg,
|
||||
REG_WRITE(map->cntr,
|
||||
temp | DISPLAY_PLANE_ENABLE);
|
||||
/* Flush the plane changes */
|
||||
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
|
||||
REG_WRITE(map->base, REG_READ(map->base));
|
||||
}
|
||||
|
||||
psb_intel_crtc_load_lut(crtc);
|
||||
|
@ -487,29 +472,29 @@ static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|||
REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
|
||||
|
||||
/* Disable display plane */
|
||||
temp = REG_READ(dspcntr_reg);
|
||||
temp = REG_READ(map->cntr);
|
||||
if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
|
||||
REG_WRITE(dspcntr_reg,
|
||||
REG_WRITE(map->cntr,
|
||||
temp & ~DISPLAY_PLANE_ENABLE);
|
||||
/* Flush the plane changes */
|
||||
REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
|
||||
REG_READ(dspbase_reg);
|
||||
REG_WRITE(map->base, REG_READ(map->base));
|
||||
REG_READ(map->base);
|
||||
}
|
||||
|
||||
/* Next, disable display pipes */
|
||||
temp = REG_READ(pipeconf_reg);
|
||||
temp = REG_READ(map->conf);
|
||||
if ((temp & PIPEACONF_ENABLE) != 0) {
|
||||
REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
|
||||
REG_READ(pipeconf_reg);
|
||||
REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
|
||||
REG_READ(map->conf);
|
||||
}
|
||||
|
||||
/* Wait for vblank for the disable to take effect. */
|
||||
psb_intel_wait_for_vblank(dev);
|
||||
|
||||
temp = REG_READ(dpll_reg);
|
||||
temp = REG_READ(map->dpll);
|
||||
if ((temp & DPLL_VCO_ENABLE) != 0) {
|
||||
REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
|
||||
REG_READ(map->dpll);
|
||||
}
|
||||
|
||||
/* Wait for the clocks to turn off. */
|
||||
|
@ -589,22 +574,11 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
struct drm_framebuffer *old_fb)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
int fp_reg = (pipe == 0) ? FPA0 : FPB0;
|
||||
int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
|
||||
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
|
||||
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
|
||||
int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
|
||||
int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
|
||||
int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
|
||||
int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
|
||||
int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
|
||||
int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
|
||||
int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
|
||||
int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
|
||||
int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
int refclk;
|
||||
struct psb_intel_clock_t clock;
|
||||
u32 dpll = 0, fp = 0, dspcntr, pipeconf;
|
||||
|
@ -690,7 +664,7 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
dpll |= PLL_REF_INPUT_DREFCLK;
|
||||
|
||||
/* setup pipeconf */
|
||||
pipeconf = REG_READ(pipeconf_reg);
|
||||
pipeconf = REG_READ(map->conf);
|
||||
|
||||
/* Set up the display plane register */
|
||||
dspcntr = DISPPLANE_GAMMA_ENABLE;
|
||||
|
@ -712,9 +686,9 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
drm_mode_debug_printmodeline(mode);
|
||||
|
||||
if (dpll & DPLL_VCO_ENABLE) {
|
||||
REG_WRITE(fp_reg, fp);
|
||||
REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->fp0, fp);
|
||||
REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
|
||||
REG_READ(map->dpll);
|
||||
udelay(150);
|
||||
}
|
||||
|
||||
|
@ -747,45 +721,45 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
REG_READ(LVDS);
|
||||
}
|
||||
|
||||
REG_WRITE(fp_reg, fp);
|
||||
REG_WRITE(dpll_reg, dpll);
|
||||
REG_READ(dpll_reg);
|
||||
REG_WRITE(map->fp0, fp);
|
||||
REG_WRITE(map->dpll, dpll);
|
||||
REG_READ(map->dpll);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
|
||||
/* write it again -- the BIOS does, after all */
|
||||
REG_WRITE(dpll_reg, dpll);
|
||||
REG_WRITE(map->dpll, dpll);
|
||||
|
||||
REG_READ(dpll_reg);
|
||||
REG_READ(map->dpll);
|
||||
/* Wait for the clocks to stabilize. */
|
||||
udelay(150);
|
||||
|
||||
REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
|
||||
REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
|
||||
((adjusted_mode->crtc_htotal - 1) << 16));
|
||||
REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
|
||||
REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
|
||||
((adjusted_mode->crtc_hblank_end - 1) << 16));
|
||||
REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
|
||||
REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
|
||||
((adjusted_mode->crtc_hsync_end - 1) << 16));
|
||||
REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
|
||||
REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
|
||||
((adjusted_mode->crtc_vtotal - 1) << 16));
|
||||
REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
|
||||
REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
|
||||
((adjusted_mode->crtc_vblank_end - 1) << 16));
|
||||
REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
|
||||
REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
|
||||
((adjusted_mode->crtc_vsync_end - 1) << 16));
|
||||
/* pipesrc and dspsize control the size that is scaled from,
|
||||
* which should always be the user's requested size.
|
||||
*/
|
||||
REG_WRITE(dspsize_reg,
|
||||
REG_WRITE(map->size,
|
||||
((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
|
||||
REG_WRITE(dsppos_reg, 0);
|
||||
REG_WRITE(pipesrc_reg,
|
||||
REG_WRITE(map->pos, 0);
|
||||
REG_WRITE(map->src,
|
||||
((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
|
||||
REG_WRITE(pipeconf_reg, pipeconf);
|
||||
REG_READ(pipeconf_reg);
|
||||
REG_WRITE(map->conf, pipeconf);
|
||||
REG_READ(map->conf);
|
||||
|
||||
psb_intel_wait_for_vblank(dev);
|
||||
|
||||
REG_WRITE(dspcntr_reg, dspcntr);
|
||||
REG_WRITE(map->cntr, dspcntr);
|
||||
|
||||
/* Flush the plane changes */
|
||||
crtc_funcs->mode_set_base(crtc, x, y, old_fb);
|
||||
|
@ -801,7 +775,8 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
|
|||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
int palreg = PALETTE_A;
|
||||
const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
|
||||
int palreg = map->palette;
|
||||
int i;
|
||||
|
||||
/* The clocks have to be on to load the palette. */
|
||||
|
@ -810,12 +785,7 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
|
|||
|
||||
switch (psb_intel_crtc->pipe) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
palreg = PALETTE_B;
|
||||
break;
|
||||
case 2:
|
||||
palreg = PALETTE_C;
|
||||
break;
|
||||
default:
|
||||
dev_err(dev->dev, "Illegal Pipe Number.\n");
|
||||
|
@ -853,11 +823,10 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
|
|||
static void psb_intel_crtc_save(struct drm_crtc *crtc)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
/* struct drm_psb_private *dev_priv =
|
||||
(struct drm_psb_private *)dev->dev_private; */
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
|
||||
int pipeA = (psb_intel_crtc->pipe == 0);
|
||||
const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
|
||||
uint32_t paletteReg;
|
||||
int i;
|
||||
|
||||
|
@ -866,27 +835,27 @@ static void psb_intel_crtc_save(struct drm_crtc *crtc)
|
|||
return;
|
||||
}
|
||||
|
||||
crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR);
|
||||
crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF);
|
||||
crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC);
|
||||
crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0);
|
||||
crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1);
|
||||
crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B);
|
||||
crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B);
|
||||
crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B);
|
||||
crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B);
|
||||
crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B);
|
||||
crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B);
|
||||
crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B);
|
||||
crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE);
|
||||
crtc_state->saveDSPCNTR = REG_READ(map->cntr);
|
||||
crtc_state->savePIPECONF = REG_READ(map->conf);
|
||||
crtc_state->savePIPESRC = REG_READ(map->src);
|
||||
crtc_state->saveFP0 = REG_READ(map->fp0);
|
||||
crtc_state->saveFP1 = REG_READ(map->fp1);
|
||||
crtc_state->saveDPLL = REG_READ(map->dpll);
|
||||
crtc_state->saveHTOTAL = REG_READ(map->htotal);
|
||||
crtc_state->saveHBLANK = REG_READ(map->hblank);
|
||||
crtc_state->saveHSYNC = REG_READ(map->hsync);
|
||||
crtc_state->saveVTOTAL = REG_READ(map->vtotal);
|
||||
crtc_state->saveVBLANK = REG_READ(map->vblank);
|
||||
crtc_state->saveVSYNC = REG_READ(map->vsync);
|
||||
crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
|
||||
|
||||
/*NOTE: DSPSIZE DSPPOS only for psb*/
|
||||
crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE);
|
||||
crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS);
|
||||
crtc_state->saveDSPSIZE = REG_READ(map->size);
|
||||
crtc_state->saveDSPPOS = REG_READ(map->pos);
|
||||
|
||||
crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE);
|
||||
crtc_state->saveDSPBASE = REG_READ(map->base);
|
||||
|
||||
paletteReg = pipeA ? PALETTE_A : PALETTE_B;
|
||||
paletteReg = map->palette;
|
||||
for (i = 0; i < 256; ++i)
|
||||
crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
|
||||
}
|
||||
|
@ -897,12 +866,10 @@ static void psb_intel_crtc_save(struct drm_crtc *crtc)
|
|||
static void psb_intel_crtc_restore(struct drm_crtc *crtc)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
/* struct drm_psb_private * dev_priv =
|
||||
(struct drm_psb_private *)dev->dev_private; */
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
|
||||
/* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */
|
||||
int pipeA = (psb_intel_crtc->pipe == 0);
|
||||
const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
|
||||
uint32_t paletteReg;
|
||||
int i;
|
||||
|
||||
|
@ -912,45 +879,45 @@ static void psb_intel_crtc_restore(struct drm_crtc *crtc)
|
|||
}
|
||||
|
||||
if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
|
||||
REG_WRITE(pipeA ? DPLL_A : DPLL_B,
|
||||
REG_WRITE(map->dpll,
|
||||
crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
|
||||
REG_READ(pipeA ? DPLL_A : DPLL_B);
|
||||
REG_READ(map->dpll);
|
||||
udelay(150);
|
||||
}
|
||||
|
||||
REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0);
|
||||
REG_READ(pipeA ? FPA0 : FPB0);
|
||||
REG_WRITE(map->fp0, crtc_state->saveFP0);
|
||||
REG_READ(map->fp0);
|
||||
|
||||
REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1);
|
||||
REG_READ(pipeA ? FPA1 : FPB1);
|
||||
REG_WRITE(map->fp1, crtc_state->saveFP1);
|
||||
REG_READ(map->fp1);
|
||||
|
||||
REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL);
|
||||
REG_READ(pipeA ? DPLL_A : DPLL_B);
|
||||
REG_WRITE(map->dpll, crtc_state->saveDPLL);
|
||||
REG_READ(map->dpll);
|
||||
udelay(150);
|
||||
|
||||
REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL);
|
||||
REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK);
|
||||
REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC);
|
||||
REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL);
|
||||
REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK);
|
||||
REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC);
|
||||
REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE);
|
||||
REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
|
||||
REG_WRITE(map->hblank, crtc_state->saveHBLANK);
|
||||
REG_WRITE(map->hsync, crtc_state->saveHSYNC);
|
||||
REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
|
||||
REG_WRITE(map->vblank, crtc_state->saveVBLANK);
|
||||
REG_WRITE(map->vsync, crtc_state->saveVSYNC);
|
||||
REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
|
||||
|
||||
REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE);
|
||||
REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS);
|
||||
REG_WRITE(map->size, crtc_state->saveDSPSIZE);
|
||||
REG_WRITE(map->pos, crtc_state->saveDSPPOS);
|
||||
|
||||
REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC);
|
||||
REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
|
||||
REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF);
|
||||
REG_WRITE(map->src, crtc_state->savePIPESRC);
|
||||
REG_WRITE(map->base, crtc_state->saveDSPBASE);
|
||||
REG_WRITE(map->conf, crtc_state->savePIPECONF);
|
||||
|
||||
psb_intel_wait_for_vblank(dev);
|
||||
|
||||
REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR);
|
||||
REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
|
||||
REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
|
||||
REG_WRITE(map->base, crtc_state->saveDSPBASE);
|
||||
|
||||
psb_intel_wait_for_vblank(dev);
|
||||
|
||||
paletteReg = pipeA ? PALETTE_A : PALETTE_B;
|
||||
paletteReg = map->palette;
|
||||
for (i = 0; i < 256; ++i)
|
||||
REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
|
||||
}
|
||||
|
@ -1114,20 +1081,21 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev,
|
|||
struct drm_crtc *crtc)
|
||||
{
|
||||
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
int pipe = psb_intel_crtc->pipe;
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
u32 dpll;
|
||||
u32 fp;
|
||||
struct psb_intel_clock_t clock;
|
||||
bool is_lvds;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B);
|
||||
dpll = REG_READ(map->dpll);
|
||||
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
|
||||
fp = REG_READ((pipe == 0) ? FPA0 : FPB0);
|
||||
fp = REG_READ(map->fp0);
|
||||
else
|
||||
fp = REG_READ((pipe == 0) ? FPA1 : FPB1);
|
||||
fp = REG_READ(map->fp1);
|
||||
is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
|
||||
gma_power_end(dev);
|
||||
} else {
|
||||
|
@ -1197,12 +1165,13 @@ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
|
|||
int vsync;
|
||||
struct drm_psb_private *dev_priv = dev->dev_private;
|
||||
struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
|
||||
const struct psb_offset *map = &dev_priv->regmap[pipe];
|
||||
|
||||
if (gma_power_begin(dev, false)) {
|
||||
htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
|
||||
hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
|
||||
vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
|
||||
vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
|
||||
htot = REG_READ(map->htotal);
|
||||
hsync = REG_READ(map->hsync);
|
||||
vtot = REG_READ(map->vtotal);
|
||||
vsync = REG_READ(map->vsync);
|
||||
gma_power_end(dev);
|
||||
} else {
|
||||
htot = p->htotal;
|
||||
|
|
Loading…
Reference in a new issue