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mtd: nand: spansion S30MLxxxP support
Some Spansion chips have a method for determining eraseblock size that is incompatible with similar ID chips of other sizes. This implements some heuristic detection of these differences. This patch checks for a 5-byte ID with trailing zeros as well as a 512-byte page size to ensure that chips are not misdetected as the S30MLxxxP ORNAND series. [Tweaked by Artem a bit] Signed-off-by: Brian Norris <norris@broadcom.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -2900,6 +2900,19 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
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mtd->writesize = type->pagesize;
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mtd->oobsize = mtd->writesize / 32;
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busw = type->options & NAND_BUSWIDTH_16;
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/*
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* Check for Spansion/AMD ID + repeating 5th, 6th byte since
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* some Spansion chips have erasesize that conflicts with size
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* listed in nand_ids table
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* Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
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*/
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if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
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id_data[5] == 0x00 && id_data[6] == 0x00 &&
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id_data[7] == 0x00 && mtd->writesize == 512) {
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mtd->erasesize = 128 * 1024;
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mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
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}
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}
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/* Try to identify manufacturer */
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