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[ARM] 2940/1: Fix BTB entry flush in arch/arm/mm/cache-v6.S

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Patch from Gen FUKATSU

Invalidate BTB entry instruction flushes two instruction
at a time. Therefore this instruction should be done four
times after invalidate instruction cache line.

Signed-off-by: Gen Fukatsu
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Gen FUKATSU 2005-09-30 16:09:17 +01:00 committed by Russell King
parent a06f5466c4
commit 217874feed
1 changed files with 8 additions and 1 deletions
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9
arch/arm/mm/cache-v6.S
View file

@ -18,6 +18,7 @@
#define HARVARD_CACHE
#define CACHE_LINE_SIZE 32
#define D_CACHE_LINE_SIZE 32
#define BTB_FLUSH_SIZE 8
/*
* v6_flush_cache_all()
@ -98,7 +99,13 @@ ENTRY(v6_coherent_user_range)
mcr p15, 0, r0, c7, c5, 1 @ invalidate I line
#endif
mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
add r0, r0, #CACHE_LINE_SIZE
add r0, r0, #BTB_FLUSH_SIZE
mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
add r0, r0, #BTB_FLUSH_SIZE
mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
add r0, r0, #BTB_FLUSH_SIZE
mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry
add r0, r0, #BTB_FLUSH_SIZE
cmp r0, r1
blo 1b
#ifdef HARVARD_CACHE