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net/mlx5: Expose IP-in-IP TX and RX capability bits

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Expose FW indication that it supports stateless offloads for IP over IP
tunneled packets per direction. In some HW like ConnectX-4 IP-in-IP
support is not symmetric, it supports steering on the inner header but
it doesn't TX-Checksum and TSO. Add IP-in-IP capability per direction to
cover this case as well.

Note: only if both indications are turned on, the global
tunnel_stateless_ip_over_ip is on too.

Signed-off-by: Aya Levin <ayal@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Aya Levin 2020-11-20 15:03:32 -08:00 committed by Saeed Mahameed
parent 349125ba23
commit 21adf05d45
1 changed files with 4 additions and 1 deletions
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5
include/linux/mlx5/mlx5_ifc.h
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@ -913,7 +913,10 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
u8 tunnel_stateless_ipv4_over_vxlan[0x1];
u8 tunnel_stateless_ip_over_ip[0x1];
u8 insert_trailer[0x1];
u8 reserved_at_2b[0x5];
u8 reserved_at_2b[0x1];
u8 tunnel_stateless_ip_over_ip_rx[0x1];
u8 tunnel_stateless_ip_over_ip_tx[0x1];
u8 reserved_at_2e[0x2];
u8 max_vxlan_udp_ports[0x8];
u8 reserved_at_38[0x6];
u8 max_geneve_opt_len[0x1];