spi: pxa2xx: Drop linux/spi/pxa2xx_spi.h
Merge series from Andy Shevchenko <andriy.shevchenko@linux.intel.com>: As Arnd suggested we may drop linux/spi/pxa2xx_spi.h as most of its content is being used solely internally to SPI subsystem (PXA2xx drivers). Hence this refactoring series with the additional win of getting rid of legacy documentation. Note, that we have the only user of a single plain integer field in the entire kernel for that. Switching to software nodes does not diminish any of type checking as we only pass an integer.
This commit is contained in:
Mark Brown
commit
21ae190e46
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@ -1,208 +0,0 @@
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==============================
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PXA2xx SPI on SSP driver HOWTO
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==============================
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This a mini HOWTO on the pxa2xx_spi driver. The driver turns a PXA2xx
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synchronous serial port into an SPI host controller
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(see Documentation/spi/spi-summary.rst). The driver has the following features
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- Support for any PXA2xx and compatible SSP.
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- SSP PIO and SSP DMA data transfers.
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- External and Internal (SSPFRM) chip selects.
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- Per peripheral device (chip) configuration.
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- Full suspend, freeze, resume support.
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The driver is built around a &struct spi_message FIFO serviced by kernel
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thread. The kernel thread, spi_pump_messages(), drives message FIFO and
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is responsible for queuing SPI transactions and setting up and launching
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the DMA or interrupt driven transfers.
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Declaring PXA2xx host controllers
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---------------------------------
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Typically, for a legacy platform, an SPI host controller is defined in the
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arch/.../mach-*/board-*.c as a "platform device". The host controller configuration
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is passed to the driver via a table found in include/linux/spi/pxa2xx_spi.h::
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struct pxa2xx_spi_controller {
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u8 num_chipselect;
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u8 enable_dma;
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...
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};
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The "pxa2xx_spi_controller.num_chipselect" field is used to determine the number of
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peripheral devices (chips) attached to this SPI host controller.
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The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP DMA should
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be used. This caused the driver to acquire two DMA channels: Rx channel and
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Tx channel. The Rx channel has a higher DMA service priority than the Tx channel.
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See the "PXA2xx Developer Manual" section "DMA Controller".
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For the new platforms the description of the controller and peripheral devices
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comes from Device Tree or ACPI.
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NSSP HOST SAMPLE
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----------------
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Below is a sample configuration using the PXA255 NSSP for a legacy platform::
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static struct resource pxa_spi_nssp_resources[] = {
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[0] = {
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.start = __PREG(SSCR0_P(2)), /* Start address of NSSP */
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.end = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_NSSP, /* NSSP IRQ */
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.end = IRQ_NSSP,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct pxa2xx_spi_controller pxa_nssp_controller_info = {
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.num_chipselect = 1, /* Matches the number of chips attached to NSSP */
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.enable_dma = 1, /* Enables NSSP DMA */
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};
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static struct platform_device pxa_spi_nssp = {
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.name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */
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.id = 2, /* Bus number, MUST MATCH SSP number 1..n */
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.resource = pxa_spi_nssp_resources,
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.num_resources = ARRAY_SIZE(pxa_spi_nssp_resources),
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.dev = {
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.platform_data = &pxa_nssp_controller_info, /* Passed to driver */
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},
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};
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static struct platform_device *devices[] __initdata = {
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&pxa_spi_nssp,
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};
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static void __init board_init(void)
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{
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(void)platform_add_device(devices, ARRAY_SIZE(devices));
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}
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Declaring peripheral devices
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----------------------------
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Typically, for a legacy platform, each SPI peripheral device (chip) is defined in the
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arch/.../mach-*/board-*.c using the "spi_board_info" structure found in
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"linux/spi/spi.h". See "Documentation/spi/spi-summary.rst" for additional
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information.
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Each peripheral device (chip) attached to the PXA2xx must provide specific chip configuration
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information via the structure "pxa2xx_spi_chip" found in
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"include/linux/spi/pxa2xx_spi.h". The PXA2xx host controller driver will use
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the configuration whenever the driver communicates with the peripheral
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device. All fields are optional.
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::
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struct pxa2xx_spi_chip {
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u8 tx_threshold;
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u8 rx_threshold;
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u8 dma_burst_size;
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u32 timeout;
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};
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The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
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used to configure the SSP hardware FIFO. These fields are critical to the
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performance of pxa2xx_spi driver and misconfiguration will result in rx
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FIFO overruns (especially in PIO mode transfers). Good default values are::
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.tx_threshold = 8,
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.rx_threshold = 8,
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The range is 1 to 16 where zero indicates "use default".
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The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA
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engine and is related the "spi_device.bits_per_word" field. Read and understand
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the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
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to determine the correct value. An SSP configured for byte-wide transfers would
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use a value of 8. The driver will determine a reasonable default if
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dma_burst_size == 0.
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The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle
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trailing bytes in the SSP receiver FIFO. The correct value for this field is
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dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
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peripheral device. Please note that the PXA2xx SSP 1 does not support trailing byte
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timeouts and must busy-wait any trailing bytes.
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NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the
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chipselect is dropped after each spi_transfer. Most devices need chip select
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asserted around the complete message. Use SSPFRM as a GPIO (through a descriptor)
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to accommodate these chips.
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NSSP PERIPHERAL SAMPLE
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----------------------
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For a legacy platform or in some other cases, the pxa2xx_spi_chip structure
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is passed to the pxa2xx_spi driver in the "spi_board_info.controller_data"
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field. Below is a sample configuration using the PXA255 NSSP.
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::
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static struct pxa2xx_spi_chip cs8415a_chip_info = {
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.tx_threshold = 8, /* SSP hardware FIFO threshold */
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.rx_threshold = 8, /* SSP hardware FIFO threshold */
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.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
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.timeout = 235, /* See Intel documentation */
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};
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static struct pxa2xx_spi_chip cs8405a_chip_info = {
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.tx_threshold = 8, /* SSP hardware FIFO threshold */
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.rx_threshold = 8, /* SSP hardware FIFO threshold */
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.dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
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.timeout = 235, /* See Intel documentation */
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};
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static struct spi_board_info streetracer_spi_board_info[] __initdata = {
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{
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.modalias = "cs8415a", /* Name of spi_driver for this device */
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.max_speed_hz = 3686400, /* Run SSP as fast a possible */
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.bus_num = 2, /* Framework bus number */
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.chip_select = 0, /* Framework chip select */
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.platform_data = NULL; /* No spi_driver specific config */
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.controller_data = &cs8415a_chip_info, /* Host controller config */
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.irq = STREETRACER_APCI_IRQ, /* Peripheral device interrupt */
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},
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{
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.modalias = "cs8405a", /* Name of spi_driver for this device */
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.max_speed_hz = 3686400, /* Run SSP as fast a possible */
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.bus_num = 2, /* Framework bus number */
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.chip_select = 1, /* Framework chip select */
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.controller_data = &cs8405a_chip_info, /* Host controller config */
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.irq = STREETRACER_APCI_IRQ, /* Peripheral device interrupt */
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},
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};
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static void __init streetracer_init(void)
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{
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spi_register_board_info(streetracer_spi_board_info,
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ARRAY_SIZE(streetracer_spi_board_info));
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}
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DMA and PIO I/O Support
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-----------------------
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The pxa2xx_spi driver supports both DMA and interrupt driven PIO message
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transfers. The driver defaults to PIO mode and DMA transfers must be enabled
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by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure.
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For the newer platforms, that are known to support DMA, the driver will enable
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it automatically and try it first with a possible fallback to PIO. The DMA
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mode supports both coherent and stream based DMA mappings.
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The following logic is used to determine the type of I/O to be used on
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a per "spi_transfer" basis::
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if spi_message.len > 65536 then
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print "rate limited" warning
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use PIO transfers
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if enable_dma and the size is in the range [DMA burst size..65536] then
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use streaming DMA mode
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otherwise
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use PIO transfer
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THANKS TO
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---------
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David Brownell and others for mentoring the development of this driver.
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@ -18,10 +18,10 @@
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#include <linux/i2c.h>
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#include <linux/platform_data/i2c-pxa.h>
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#include <linux/platform_data/pca953x.h>
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#include <linux/property.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/ads7846.h>
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#include <linux/spi/corgi_lcd.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include <linux/mtd/sharpsl.h>
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#include <linux/mtd/physmap.h>
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#include <linux/input-event-codes.h>
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@ -569,10 +569,6 @@ static struct spi_board_info spitz_spi_devices[] = {
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},
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};
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static struct pxa2xx_spi_controller spitz_spi_info = {
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.num_chipselect = 3,
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};
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static struct gpiod_lookup_table spitz_spi_gpio_table = {
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.dev_id = "spi2",
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.table = {
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@ -583,10 +579,20 @@ static struct gpiod_lookup_table spitz_spi_gpio_table = {
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},
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};
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static const struct property_entry spitz_spi_properties[] = {
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PROPERTY_ENTRY_U32("num-cs", 3),
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{ }
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};
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static const struct software_node spitz_spi_node = {
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.properties = spitz_spi_properties,
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};
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static void __init spitz_spi_init(void)
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{
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struct platform_device *pd;
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int id = 2;
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int err;
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if (machine_is_akita())
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gpiod_add_lookup_table(&akita_lcdcon_gpio_table);
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@ -601,8 +607,13 @@ static void __init spitz_spi_init(void)
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if (pd == NULL) {
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pr_err("pxa2xx-spi: failed to allocate device id %d\n", id);
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} else {
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pd->dev.platform_data = &spitz_spi_info;
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platform_device_add(pd);
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err = device_add_software_node(&pd->dev, &spitz_spi_node);
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if (err) {
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platform_device_put(pd);
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pr_err("pxa2xx-spi: failed to add software node\n");
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} else {
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platform_device_add(pd);
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}
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}
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spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
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@ -832,8 +832,7 @@ config SPI_PXA2XX
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select PXA_SSP if ARCH_PXA || ARCH_MMP
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help
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This enables using a PXA2xx or Sodaville SSP port as a SPI master
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controller. The driver can be configured to use any SSP port and
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additional documentation can be found a Documentation/spi/pxa2xx.rst.
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controller. The driver can be configured to use any SSP port.
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config SPI_PXA2XX_PCI
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def_tristate SPI_PXA2XX && PCI && COMMON_CLK
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@ -6,17 +6,22 @@
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* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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*/
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#include <linux/device.h>
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#include <linux/atomic.h>
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#include <linux/dev_printk.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/errno.h>
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#include <linux/irqreturn.h>
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#include <linux/scatterlist.h>
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#include <linux/sizes.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include <linux/spi/spi.h>
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#include "spi-pxa2xx.h"
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struct device;
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static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
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bool error)
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{
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@ -63,8 +68,6 @@ pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
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enum dma_transfer_direction dir,
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struct spi_transfer *xfer)
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{
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struct chip_data *chip =
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spi_get_ctldata(drv_data->controller->cur_msg->spi);
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enum dma_slave_buswidth width;
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struct dma_slave_config cfg;
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struct dma_chan *chan;
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@ -89,14 +92,14 @@ pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
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if (dir == DMA_MEM_TO_DEV) {
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cfg.dst_addr = drv_data->ssp->phys_base + SSDR;
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cfg.dst_addr_width = width;
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cfg.dst_maxburst = chip->dma_burst_size;
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cfg.dst_maxburst = drv_data->controller_info->dma_burst_size;
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sgt = &xfer->tx_sg;
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chan = drv_data->controller->dma_tx;
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} else {
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cfg.src_addr = drv_data->ssp->phys_base + SSDR;
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cfg.src_addr_width = width;
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cfg.src_maxburst = chip->dma_burst_size;
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cfg.src_maxburst = drv_data->controller_info->dma_burst_size;
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sgt = &xfer->rx_sg;
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chan = drv_data->controller->dma_rx;
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@ -220,24 +223,3 @@ void pxa2xx_spi_dma_release(struct driver_data *drv_data)
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controller->dma_tx = NULL;
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}
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}
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int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
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struct spi_device *spi,
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u8 bits_per_word, u32 *burst_code,
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u32 *threshold)
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{
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struct pxa2xx_spi_chip *chip_info = spi->controller_data;
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struct driver_data *drv_data = spi_controller_get_devdata(spi->controller);
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u32 dma_burst_size = drv_data->controller_info->dma_burst_size;
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/*
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* If the DMA burst size is given in chip_info we use that,
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* otherwise we use the default. Also we use the default FIFO
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* thresholds for now.
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*/
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*burst_code = chip_info ? chip_info->dma_burst_size : dma_burst_size;
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*threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
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| SSCR1_TxTresh(TX_THRESH_DFLT);
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return 0;
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}
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|
|
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|
|
@ -6,15 +6,21 @@
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* Copyright (C) 2016, 2021 Intel Corporation
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include <linux/property.h>
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#include <linux/sprintf.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/dmaengine.h>
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#include <linux/platform_data/dma-dw.h>
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#include "spi-pxa2xx.h"
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#define PCI_DEVICE_ID_INTEL_QUARK_X1000 0x0935
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#define PCI_DEVICE_ID_INTEL_BYT 0x0f0e
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#define PCI_DEVICE_ID_INTEL_MRFLD 0x1194
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|
|
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|
|
@ -5,26 +5,29 @@
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*/
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#include <linux/acpi.h>
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#include <linux/atomic.h>
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#include <linux/bitops.h>
|
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#include <linux/bug.h>
|
||||
#include <linux/clk.h>
|
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#include <linux/delay.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/dmaengine.h>
|
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#include <linux/err.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
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#include <linux/io.h>
|
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#include <linux/ioport.h>
|
||||
#include <linux/kernel.h>
|
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#include <linux/module.h>
|
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#include <linux/math64.h>
|
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#include <linux/minmax.h>
|
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#include <linux/mod_devicetable.h>
|
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#include <linux/module.h>
|
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#include <linux/platform_device.h>
|
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#include <linux/pm_runtime.h>
|
||||
#include <linux/property.h>
|
||||
#include <linux/slab.h>
|
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#include <linux/types.h>
|
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|
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#include <linux/spi/pxa2xx_spi.h>
|
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#include <linux/spi/spi.h>
|
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|
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#include "spi-pxa2xx.h"
|
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|
|
@ -63,6 +66,14 @@ MODULE_ALIAS("platform:pxa2xx-spi");
|
|||
| CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \
|
||||
| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
|
||||
|
||||
struct chip_data {
|
||||
u32 cr1;
|
||||
u32 dds_rate;
|
||||
u32 threshold;
|
||||
u16 lpss_rx_threshold;
|
||||
u16 lpss_tx_threshold;
|
||||
};
|
||||
|
||||
#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
|
||||
#define LPSS_CS_CONTROL_SW_MODE BIT(0)
|
||||
#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
|
||||
|
|
@ -931,11 +942,11 @@ static bool pxa2xx_spi_can_dma(struct spi_controller *controller,
|
|||
struct spi_device *spi,
|
||||
struct spi_transfer *xfer)
|
||||
{
|
||||
struct chip_data *chip = spi_get_ctldata(spi);
|
||||
struct driver_data *drv_data = spi_controller_get_devdata(controller);
|
||||
|
||||
return chip->enable_dma &&
|
||||
return drv_data->controller_info->enable_dma &&
|
||||
xfer->len <= MAX_DMA_LEN &&
|
||||
xfer->len >= chip->dma_burst_size;
|
||||
xfer->len >= drv_data->controller_info->dma_burst_size;
|
||||
}
|
||||
|
||||
static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
|
||||
|
|
@ -944,9 +955,8 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
|
|||
{
|
||||
struct driver_data *drv_data = spi_controller_get_devdata(controller);
|
||||
struct chip_data *chip = spi_get_ctldata(spi);
|
||||
u32 dma_thresh = chip->dma_threshold;
|
||||
u32 dma_burst = chip->dma_burst_size;
|
||||
u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
|
||||
u32 dma_thresh;
|
||||
u32 clk_div;
|
||||
u8 bits;
|
||||
u32 speed;
|
||||
|
|
@ -956,7 +966,7 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
|
|||
int dma_mapped;
|
||||
|
||||
/* Check if we can DMA this transfer */
|
||||
if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
|
||||
if (transfer->len > MAX_DMA_LEN && drv_data->controller_info->enable_dma) {
|
||||
/* Warn ... we force this to PIO mode */
|
||||
dev_warn_ratelimited(&spi->dev,
|
||||
"DMA disabled for transfer length %u greater than %d\n",
|
||||
|
|
@ -992,19 +1002,8 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
|
|||
drv_data->read = drv_data->rx ? u32_reader : null_reader;
|
||||
drv_data->write = drv_data->tx ? u32_writer : null_writer;
|
||||
}
|
||||
/*
|
||||
* If bits per word is changed in DMA mode, then must check
|
||||
* the thresholds and burst also.
|
||||
*/
|
||||
if (chip->enable_dma) {
|
||||
if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
|
||||
spi,
|
||||
bits, &dma_burst,
|
||||
&dma_thresh))
|
||||
dev_warn_ratelimited(&spi->dev,
|
||||
"DMA burst size reduced to match bits_per_word\n");
|
||||
}
|
||||
|
||||
dma_thresh = SSCR1_RxTresh(RX_THRESH_DFLT) | SSCR1_TxTresh(TX_THRESH_DFLT);
|
||||
dma_mapped = controller->can_dma &&
|
||||
controller->can_dma(controller, spi, transfer) &&
|
||||
controller->cur_msg_mapped;
|
||||
|
|
@ -1067,7 +1066,7 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller,
|
|||
pxa_ssp_disable(drv_data->ssp);
|
||||
|
||||
if (!pxa25x_ssp_comp(drv_data))
|
||||
pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
|
||||
pxa2xx_spi_write(drv_data, SSTO, TIMOUT_DFLT);
|
||||
|
||||
/* First set CR1 without interrupt and service enables */
|
||||
pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1);
|
||||
|
|
@ -1151,7 +1150,6 @@ static int pxa2xx_spi_unprepare_transfer(struct spi_controller *controller)
|
|||
|
||||
static int setup(struct spi_device *spi)
|
||||
{
|
||||
struct pxa2xx_spi_chip *chip_info;
|
||||
struct chip_data *chip;
|
||||
const struct lpss_config *config;
|
||||
struct driver_data *drv_data =
|
||||
|
|
@ -1210,28 +1208,6 @@ static int setup(struct spi_device *spi)
|
|||
chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
|
||||
if (!chip)
|
||||
return -ENOMEM;
|
||||
|
||||
chip->enable_dma = drv_data->controller_info->enable_dma;
|
||||
chip->timeout = TIMOUT_DFLT;
|
||||
}
|
||||
|
||||
/*
|
||||
* Protocol drivers may change the chip settings, so...
|
||||
* if chip_info exists, use it.
|
||||
*/
|
||||
chip_info = spi->controller_data;
|
||||
|
||||
/* chip_info isn't always needed */
|
||||
if (chip_info) {
|
||||
if (chip_info->timeout)
|
||||
chip->timeout = chip_info->timeout;
|
||||
if (chip_info->tx_threshold)
|
||||
tx_thres = chip_info->tx_threshold;
|
||||
if (chip_info->tx_hi_threshold)
|
||||
tx_hi_thres = chip_info->tx_hi_threshold;
|
||||
if (chip_info->rx_threshold)
|
||||
rx_thres = chip_info->rx_threshold;
|
||||
chip->dma_threshold = 0;
|
||||
}
|
||||
|
||||
chip->cr1 = 0;
|
||||
|
|
@ -1253,25 +1229,6 @@ static int setup(struct spi_device *spi)
|
|||
chip->lpss_tx_threshold = tx_thres;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set DMA burst and threshold outside of chip_info path so that if
|
||||
* chip_info goes away after setting chip->enable_dma, the burst and
|
||||
* threshold can still respond to changes in bits_per_word.
|
||||
*/
|
||||
if (chip->enable_dma) {
|
||||
/* Set up legal burst and threshold for DMA */
|
||||
if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
|
||||
spi->bits_per_word,
|
||||
&chip->dma_burst_size,
|
||||
&chip->dma_threshold)) {
|
||||
dev_warn(&spi->dev,
|
||||
"in setup: DMA burst size reduced to match bits_per_word\n");
|
||||
}
|
||||
dev_dbg(&spi->dev,
|
||||
"in setup: DMA burst size set to %u\n",
|
||||
chip->dma_burst_size);
|
||||
}
|
||||
|
||||
switch (drv_data->ssp_type) {
|
||||
case QUARK_X1000_SSP:
|
||||
chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
|
||||
|
|
@ -1357,6 +1314,7 @@ pxa2xx_spi_init_pdata(struct platform_device *pdev)
|
|||
struct ssp_device *ssp = NULL;
|
||||
const void *match;
|
||||
bool is_lpss_priv;
|
||||
u32 num_cs = 1;
|
||||
int status;
|
||||
|
||||
is_lpss_priv = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpss_priv");
|
||||
|
|
@ -1395,8 +1353,11 @@ pxa2xx_spi_init_pdata(struct platform_device *pdev)
|
|||
pdata->dma_filter = pxa2xx_spi_idma_filter;
|
||||
}
|
||||
|
||||
/* Read number of chip select pins, if provided */
|
||||
device_property_read_u32(dev, "num-cs", &num_cs);
|
||||
|
||||
pdata->num_chipselect = num_cs;
|
||||
pdata->is_target = device_property_read_bool(dev, "spi-slave");
|
||||
pdata->num_chipselect = 1;
|
||||
pdata->enable_dma = true;
|
||||
pdata->dma_burst_size = 1;
|
||||
|
||||
|
|
@ -1457,6 +1418,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(platform_info))
|
||||
return dev_err_probe(dev, PTR_ERR(platform_info), "missing platform data\n");
|
||||
}
|
||||
dev_dbg(dev, "DMA burst size set to %u\n", platform_info->dma_burst_size);
|
||||
|
||||
ssp = pxa_ssp_request(pdev->id, pdev->name);
|
||||
if (!ssp)
|
||||
|
|
|
|||
|
|
@ -7,15 +7,34 @@
|
|||
#ifndef SPI_PXA2XX_H
|
||||
#define SPI_PXA2XX_H
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/irqreturn.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#include <linux/pxa2xx_ssp.h>
|
||||
|
||||
struct gpio_desc;
|
||||
struct pxa2xx_spi_controller;
|
||||
|
||||
/*
|
||||
* The platform data for SSP controller devices
|
||||
* (resides in device.platform_data).
|
||||
*/
|
||||
struct pxa2xx_spi_controller {
|
||||
u8 num_chipselect;
|
||||
u8 enable_dma;
|
||||
u8 dma_burst_size;
|
||||
bool is_target;
|
||||
|
||||
/* DMA engine specific config */
|
||||
dma_filter_fn dma_filter;
|
||||
void *tx_param;
|
||||
void *rx_param;
|
||||
|
||||
/* For non-PXA arches */
|
||||
struct ssp_device ssp;
|
||||
};
|
||||
|
||||
struct spi_controller;
|
||||
struct spi_device;
|
||||
struct spi_transfer;
|
||||
|
|
@ -56,18 +75,6 @@ struct driver_data {
|
|||
struct gpio_desc *gpiod_ready;
|
||||
};
|
||||
|
||||
struct chip_data {
|
||||
u32 cr1;
|
||||
u32 dds_rate;
|
||||
u32 timeout;
|
||||
u8 enable_dma;
|
||||
u32 dma_burst_size;
|
||||
u32 dma_threshold;
|
||||
u32 threshold;
|
||||
u16 lpss_rx_threshold;
|
||||
u16 lpss_tx_threshold;
|
||||
};
|
||||
|
||||
static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, u32 reg)
|
||||
{
|
||||
return pxa_ssp_read_reg(drv_data->ssp, reg);
|
||||
|
|
@ -123,10 +130,5 @@ extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
|
|||
extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
|
||||
extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
|
||||
extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
|
||||
extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
|
||||
struct spi_device *spi,
|
||||
u8 bits_per_word,
|
||||
u32 *burst_code,
|
||||
u32 *threshold);
|
||||
|
||||
#endif /* SPI_PXA2XX_H */
|
||||
|
|
|
|||
|
|
@ -1,48 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
|
||||
*/
|
||||
#ifndef __LINUX_SPI_PXA2XX_SPI_H
|
||||
#define __LINUX_SPI_PXA2XX_SPI_H
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <linux/pxa2xx_ssp.h>
|
||||
|
||||
struct dma_chan;
|
||||
|
||||
/*
|
||||
* The platform data for SSP controller devices
|
||||
* (resides in device.platform_data).
|
||||
*/
|
||||
struct pxa2xx_spi_controller {
|
||||
u8 num_chipselect;
|
||||
u8 enable_dma;
|
||||
u8 dma_burst_size;
|
||||
bool is_target;
|
||||
|
||||
/* DMA engine specific config */
|
||||
dma_filter_fn dma_filter;
|
||||
void *tx_param;
|
||||
void *rx_param;
|
||||
|
||||
/* For non-PXA arches */
|
||||
struct ssp_device ssp;
|
||||
};
|
||||
|
||||
/*
|
||||
* The controller specific data for SPI target devices
|
||||
* (resides in spi_board_info.controller_data),
|
||||
* copied to spi_device.platform_data ... mostly for
|
||||
* DMA tuning.
|
||||
*/
|
||||
struct pxa2xx_spi_chip {
|
||||
u8 tx_threshold;
|
||||
u8 tx_hi_threshold;
|
||||
u8 rx_threshold;
|
||||
u8 dma_burst_size;
|
||||
u32 timeout;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_SPI_PXA2XX_SPI_H */
|
||||
Loading…
Reference in New Issue