From 2224de9d152b6fd9faa0df49cf55ca97eab772fa Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Wed, 18 Sep 2013 13:32:59 +0200 Subject: [PATCH] MIPS: BCM47XX: Fix clock detection for BCM5354 with 200MHz clock Some BCM5354 SoCs are running at 200MHz, but it is not possible to read the clock from a register like it is done on some other SoC in ssb and bcma. These devices should have a clkfreq nvram configuration value set to 200, read it and set the clock to the correct value. Signed-off-by: Hauke Mehrtens Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5842/ Signed-off-by: Ralf Baechle --- arch/mips/bcm47xx/time.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c index 536374dcba78..5e5d797fa90a 100644 --- a/arch/mips/bcm47xx/time.c +++ b/arch/mips/bcm47xx/time.c @@ -27,10 +27,14 @@ #include #include #include +#include void __init plat_time_init(void) { unsigned long hz = 0; + u16 chip_id = 0; + char buf[10]; + int len; /* * Use deterministic values for initial counter interrupt @@ -43,15 +47,23 @@ void __init plat_time_init(void) #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2; + chip_id = bcm47xx_bus.ssb.chip_id; break; #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2; + chip_id = bcm47xx_bus.bcma.bus.chipinfo.id; break; #endif } + if (chip_id == 0x5354) { + len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf)); + if (len >= 0 && !strncmp(buf, "200", 4)) + hz = 100000000; + } + if (!hz) hz = 100000000;