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PCI: aardvark: Implement re-issuing config requests on CRS response
Commit 43f5c77bcb
("PCI: aardvark: Fix reporting CRS value") fixed
handling of CRS response and when CRSSVE flag was not enabled it marked CRS
response as failed transaction (due to simplicity).
But pci-aardvark.c driver is already waiting up to the PIO_RETRY_CNT count
for PIO config response and so we can with a small change implement
re-issuing of config requests as described in PCIe base specification.
This change implements re-issuing of config requests when response is CRS.
Set upper bound of wait cycles to around PIO_RETRY_CNT, afterwards the
transaction is marked as failed and an all-ones value is returned as
before.
We do this by returning appropriate error codes from function
advk_pcie_check_pio_status(). On CRS we return -EAGAIN and caller then
reissues transaction.
Link: https://lore.kernel.org/r/20211005180952.6812-10-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
This commit is contained in:
parent
67cb2a4c93
commit
223dec14a0
1 changed files with 43 additions and 24 deletions
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@ -603,6 +603,7 @@ static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u3
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u32 reg;
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unsigned int status;
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char *strcomp_status, *str_posted;
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int ret;
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reg = advk_readl(pcie, PIO_STAT);
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status = (reg & PIO_COMPLETION_STATUS_MASK) >>
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@ -627,6 +628,7 @@ static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u3
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case PIO_COMPLETION_STATUS_OK:
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if (reg & PIO_ERR_STATUS) {
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strcomp_status = "COMP_ERR";
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ret = -EFAULT;
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break;
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}
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/* Get the read result */
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@ -634,9 +636,11 @@ static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u3
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*val = advk_readl(pcie, PIO_RD_DATA);
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/* No error */
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strcomp_status = NULL;
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ret = 0;
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break;
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case PIO_COMPLETION_STATUS_UR:
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strcomp_status = "UR";
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ret = -EOPNOTSUPP;
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break;
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case PIO_COMPLETION_STATUS_CRS:
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if (allow_crs && val) {
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@ -654,6 +658,7 @@ static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u3
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*/
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*val = CFG_RD_CRS_VAL;
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strcomp_status = NULL;
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ret = 0;
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break;
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}
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/* PCIe r4.0, sec 2.3.2, says:
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@ -669,21 +674,24 @@ static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u3
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* Request and taking appropriate action, e.g., complete the
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* Request to the host as a failed transaction.
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*
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* To simplify implementation do not re-issue the Configuration
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* Request and complete the Request as a failed transaction.
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* So return -EAGAIN and caller (pci-aardvark.c driver) will
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* re-issue request again up to the PIO_RETRY_CNT retries.
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*/
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strcomp_status = "CRS";
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ret = -EAGAIN;
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break;
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case PIO_COMPLETION_STATUS_CA:
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strcomp_status = "CA";
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ret = -ECANCELED;
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break;
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default:
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strcomp_status = "Unknown";
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ret = -EINVAL;
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break;
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}
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if (!strcomp_status)
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return 0;
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return ret;
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if (reg & PIO_NON_POSTED_REQ)
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str_posted = "Non-posted";
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@ -693,7 +701,7 @@ static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u3
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dev_dbg(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
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str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
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return -EFAULT;
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return ret;
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}
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static int advk_pcie_wait_pio(struct advk_pcie *pcie)
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@ -701,13 +709,13 @@ static int advk_pcie_wait_pio(struct advk_pcie *pcie)
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struct device *dev = &pcie->pdev->dev;
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int i;
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for (i = 0; i < PIO_RETRY_CNT; i++) {
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for (i = 1; i <= PIO_RETRY_CNT; i++) {
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u32 start, isr;
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start = advk_readl(pcie, PIO_START);
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isr = advk_readl(pcie, PIO_ISR);
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if (!start && isr)
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return 0;
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return i;
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udelay(PIO_RETRY_DELAY);
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}
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@ -898,6 +906,7 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 *val)
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{
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struct advk_pcie *pcie = bus->sysdata;
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int retry_count;
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bool allow_crs;
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u32 reg;
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int ret;
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@ -940,16 +949,22 @@ static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
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/* Program the data strobe */
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advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
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/* Clear PIO DONE ISR and start the transfer */
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advk_writel(pcie, 1, PIO_ISR);
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advk_writel(pcie, 1, PIO_START);
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retry_count = 0;
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do {
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/* Clear PIO DONE ISR and start the transfer */
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advk_writel(pcie, 1, PIO_ISR);
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advk_writel(pcie, 1, PIO_START);
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ret = advk_pcie_wait_pio(pcie);
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if (ret < 0)
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goto try_crs;
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ret = advk_pcie_wait_pio(pcie);
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if (ret < 0)
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goto try_crs;
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retry_count += ret;
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/* Check PIO status and get the read result */
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ret = advk_pcie_check_pio_status(pcie, allow_crs, val);
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} while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT);
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/* Check PIO status and get the read result */
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ret = advk_pcie_check_pio_status(pcie, allow_crs, val);
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if (ret < 0)
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goto fail;
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@ -981,6 +996,7 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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struct advk_pcie *pcie = bus->sysdata;
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u32 reg;
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u32 data_strobe = 0x0;
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int retry_count;
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int offset;
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int ret;
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@ -1022,19 +1038,22 @@ static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
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/* Program the data strobe */
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advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
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/* Clear PIO DONE ISR and start the transfer */
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advk_writel(pcie, 1, PIO_ISR);
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advk_writel(pcie, 1, PIO_START);
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retry_count = 0;
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do {
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/* Clear PIO DONE ISR and start the transfer */
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advk_writel(pcie, 1, PIO_ISR);
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advk_writel(pcie, 1, PIO_START);
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ret = advk_pcie_wait_pio(pcie);
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if (ret < 0)
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return PCIBIOS_SET_FAILED;
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ret = advk_pcie_wait_pio(pcie);
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if (ret < 0)
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return PCIBIOS_SET_FAILED;
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ret = advk_pcie_check_pio_status(pcie, false, NULL);
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if (ret < 0)
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return PCIBIOS_SET_FAILED;
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retry_count += ret;
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return PCIBIOS_SUCCESSFUL;
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ret = advk_pcie_check_pio_status(pcie, false, NULL);
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} while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT);
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return ret < 0 ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops advk_pcie_ops = {
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