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drm/amdkfd: Fix leftover errors and warnings 

A bunch of errors and warnings are leftover KFD over the years, attempt
to fix the errors and most warnings reported by checkpatch tool. Still a
few warnings remain which may be false positives so ignore them for now.

Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rajneesh Bhardwaj 2022-02-10 19:26:04 -05:00 committed by Alex Deucher
parent d87f36a063
commit 2243f4937a
17 changed files with 37 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
View File

@ -37,7 +37,7 @@
#include <linux/ptrace.h>
#include <linux/dma-buf.h>
#include <linux/fdtable.h>
#include <asm/processor.h>
#include <linux/processor.h>
#include "kfd_priv.h"
#include "kfd_device_queue_manager.h"
#include "kfd_svm.h"
@ -1133,11 +1133,12 @@ err_pdd:
return ret;
}
static bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev) {
static bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev)
{
return KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2) ||
(KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) &&
dev->adev->sdma.instance[0].fw_version >= 18) ||
KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0);
(KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) &&
dev->adev->sdma.instance[0].fw_version >= 18) ||
KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0);
}
static int kfd_ioctl_map_memory_to_gpu(struct file *filep,

2
drivers/gpu/drm/amd/amdkfd/kfd_crat.c
View File

@ -1382,7 +1382,7 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
num_of_cache_types = ARRAY_SIZE(vegam_cache_info);
break;
default:
switch(KFD_GC_VERSION(kdev)) {
switch (KFD_GC_VERSION(kdev)) {
case IP_VERSION(9, 0, 1):
pcache_info = vega10_cache_info;
num_of_cache_types = ARRAY_SIZE(vega10_cache_info);

2
drivers/gpu/drm/amd/amdkfd/kfd_crat.h
View File

@ -233,7 +233,7 @@ struct crat_subtype_ccompute {
#define CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT (1 << 2)
#define CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT (1 << 3)
#define CRAT_IOLINK_FLAGS_NO_PEER_TO_PEER_DMA (1 << 4)
#define CRAT_IOLINK_FLAGS_BI_DIRECTIONAL (1 << 31)
#define CRAT_IOLINK_FLAGS_BI_DIRECTIONAL (1 << 31)
#define CRAT_IOLINK_FLAGS_RESERVED_MASK 0x7fffffe0
/*

2
drivers/gpu/drm/amd/amdkfd/kfd_debugfs.c
View File

@ -36,7 +36,7 @@ static int kfd_debugfs_open(struct inode *inode, struct file *file)
}
static int kfd_debugfs_hang_hws_read(struct seq_file *m, void *data)
{
seq_printf(m, "echo gpu_id > hang_hws\n");
seq_puts(m, "echo gpu_id > hang_hws\n");
return 0;
}

5
drivers/gpu/drm/amd/amdkfd/kfd_device.c
View File

@ -439,7 +439,8 @@ static int kfd_gws_init(struct kfd_dev *kfd)
return ret;
}
static void kfd_smi_init(struct kfd_dev *dev) {
static void kfd_smi_init(struct kfd_dev *dev)
{
INIT_LIST_HEAD(&dev->smi_clients);
spin_lock_init(&dev->smi_lock);
}
@ -572,7 +573,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd,
svm_migrate_init(kfd->adev);
if(kgd2kfd_resume_iommu(kfd))
if (kgd2kfd_resume_iommu(kfd))
goto device_iommu_error;
if (kfd_resume(kfd))

17
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
View File

@ -677,9 +677,9 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q,
}
retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
(dqm->dev->cwsr_enabled?
KFD_PREEMPT_TYPE_WAVEFRONT_SAVE:
KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
(dqm->dev->cwsr_enabled ?
KFD_PREEMPT_TYPE_WAVEFRONT_SAVE :
KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
if (retval) {
pr_err("destroy mqd failed\n");
@ -772,9 +772,9 @@ static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
continue;
retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd,
(dqm->dev->cwsr_enabled?
KFD_PREEMPT_TYPE_WAVEFRONT_SAVE:
KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
(dqm->dev->cwsr_enabled ?
KFD_PREEMPT_TYPE_WAVEFRONT_SAVE :
KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN),
KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
if (retval && !ret)
/* Return the first error, but keep going to
@ -1099,7 +1099,7 @@ static int start_nocpsch(struct device_queue_manager *dqm)
pr_info("SW scheduler is used");
init_interrupts(dqm);
if (dqm->dev->adev->asic_type == CHIP_HAWAII)
r = pm_init(&dqm->packet_mgr, dqm);
if (!r)
@ -2235,8 +2235,7 @@ int dqm_debugfs_hqds(struct seq_file *m, void *data)
int r = 0;
if (!dqm->sched_running) {
seq_printf(m, " Device is stopped\n");
seq_puts(m, " Device is stopped\n");
return 0;
}

8
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
View File

@ -92,7 +92,7 @@ union GRBM_GFX_INDEX_BITS {
*
* @initialize: Initializes the pipelines and memory module for that device.
*
* @start: Initializes the resources/modules the the device needs for queues
* @start: Initializes the resources/modules the device needs for queues
* execution. This function is called on device initialization and after the
* system woke up after suspension.
*
@ -113,7 +113,7 @@ union GRBM_GFX_INDEX_BITS {
*
* @evict_process_queues: Evict all active queues of a process
*
* @restore_process_queues: Restore all evicted queues queues of a process
* @restore_process_queues: Restore all evicted queues of a process
*
* @get_wave_state: Retrieves context save state and optionally copies the
* control stack, if kept in the MQD, to the given userspace address.
@ -303,9 +303,7 @@ static inline void dqm_unlock(struct device_queue_manager *dqm)
static inline int read_sdma_queue_counter(uint64_t __user *q_rptr, uint64_t *val)
{
/*
* SDMA activity counter is stored at queue's RPTR + 0x8 location.
*/
/* SDMA activity counter is stored at queue's RPTR + 0x8 location. */
return get_user(*val, q_rptr + 1);
}
#endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */

9
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v10.c
View File

@ -62,15 +62,6 @@ static int update_qpd_v10(struct device_queue_manager *dqm,
(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) |
(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT);
#if 0
/* TODO:
* This shouldn't be an issue with Navi10. Verify.
*/
if (vega10_noretry)
qpd->sh_mem_config |=
1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
#endif
qpd->sh_mem_ape1_limit = 0;
qpd->sh_mem_ape1_base = 0;
}

2
drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
View File

@ -35,7 +35,7 @@
#include "kfd_priv.h"
#include <linux/mm.h>
#include <linux/mman.h>
#include <asm/processor.h>
#include <linux/processor.h>
/*
* The primary memory I/O features being added for revisions of gfxip

3
drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c
View File

@ -120,7 +120,8 @@ static void event_interrupt_poison_consumption(struct kfd_dev *dev,
kfd_signal_poison_consumed_event(dev, pasid);
/* resetting queue passes, do page retirement without gpu reset
resetting queue fails, fallback to gpu reset solution */
* resetting queue fails, fallback to gpu reset solution
*/
if (!ret)
amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, false);
else

2
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
View File

@ -363,7 +363,7 @@ svm_migrate_copy_to_vram(struct amdgpu_device *adev, struct svm_range *prange,
if (r)
goto out_free_vram_pages;
amdgpu_res_next(&cursor, (j + 1) * PAGE_SIZE);
j= 0;
j = 0;
} else {
j++;
}

1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c
View File

@ -101,6 +101,7 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
struct kfd_cu_info cu_info;
uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0};
int i, se, sh, cu;
amdgpu_amdkfd_get_cu_info(mm->dev->adev, &cu_info);
if (cu_mask_count > cu_info.cu_active_number)

2
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
View File

@ -206,7 +206,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd,
/* GC 10 removed WPP_CLAMP from PQ Control */
m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT |
1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT ;
1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT;
m->cp_hqd_pq_doorbell_control |=
1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT;
}

1
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
View File

@ -329,6 +329,7 @@ static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
struct queue_properties *q)
{
struct vi_mqd *m;
init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
m = get_mqd(*mqd);

4
drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h
View File

@ -102,8 +102,8 @@ struct pm4_mes_set_resources {
struct pm4_mes_runlist {
union {
union PM4_MES_TYPE_3_HEADER header; /* header */
uint32_t ordinal1;
union PM4_MES_TYPE_3_HEADER header; /* header */
uint32_t ordinal1;
};
union {

4
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
View File

@ -794,7 +794,7 @@ struct svm_range_list {
atomic_t drain_pagefaults;
struct delayed_work restore_work;
DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE);
struct task_struct *faulting_task;
struct task_struct *faulting_task;
};
/* Process data */
@ -915,7 +915,7 @@ bool kfd_dev_is_large_bar(struct kfd_dev *dev);
int kfd_process_create_wq(void);
void kfd_process_destroy_wq(void);
struct kfd_process *kfd_create_process(struct file *filep);
struct kfd_process *kfd_get_process(const struct task_struct *);
struct kfd_process *kfd_get_process(const struct task_struct *task);
struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid);
struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm);

6
drivers/gpu/drm/amd/amdkfd/kfd_topology.c
View File

@ -1442,9 +1442,9 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
}
/*
* Overwrite ATS capability according to needs_iommu_device to fix
* potential missing corresponding bit in CRAT of BIOS.
*/
* Overwrite ATS capability according to needs_iommu_device to fix
* potential missing corresponding bit in CRAT of BIOS.
*/
if (dev->gpu->use_iommu_v2)
dev->node_props.capability |= HSA_CAP_ATS_PRESENT;
else