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MIPS: OCTEON: octeon-usb: introduce dwc3_octeon_{read,write}q
Move all register access code into separate functions and provide their no-op version for non Octeon platforms. Later it might be possible to replace them with standard Linux functions, however datasheets are not publicly available and I have only one Octeon board to test, so lets stay on safe side for now. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Ladislav Michl
Thomas Bogendoerfer
parent
793bef5709
commit
2257c6c90e
1 changed files with 59 additions and 40 deletions
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@ -17,8 +17,6 @@
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#include <linux/mutex.h>
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#include <linux/of_platform.h>
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#include <asm/octeon/octeon.h>
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/*
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* USB Control Register
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*/
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@ -196,6 +194,17 @@
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static DEFINE_MUTEX(dwc3_octeon_clocks_mutex);
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static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
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#ifdef CONFIG_CAVIUM_OCTEON_SOC
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#include <asm/octeon/octeon.h>
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static inline uint64_t dwc3_octeon_readq(void __iomem *addr)
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{
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return cvmx_readq_csr(addr);
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}
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static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val)
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{
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cvmx_writeq_csr(base, val);
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}
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static void dwc3_octeon_config_gpio(int index, int gpio)
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{
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@ -220,14 +229,24 @@ static void dwc3_octeon_config_gpio(int index, int gpio)
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cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);
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}
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}
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#else
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static inline uint64_t dwc3_octeon_readq(void __iomem *addr)
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{
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return 0;
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}
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static int dwc3_octeon_config_power(struct device *dev, u64 base)
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static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { }
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static inline void dwc3_octeon_config_gpio(int index, int gpio) { }
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#endif
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static int dwc3_octeon_config_power(struct device *dev, void __iomem *base)
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{
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uint32_t gpio_pwr[3];
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int gpio, len, power_active_low;
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struct device_node *node = dev->of_node;
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u64 val;
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u64 uctl_host_cfg_reg = base + USBDRD_UCTL_HOST_CFG;
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void __iomem *uctl_host_cfg_reg = base + USBDRD_UCTL_HOST_CFG;
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if (of_find_property(node, "power", &len) != NULL) {
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if (len == 12) {
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@ -242,33 +261,33 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base)
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dev_err(dev, "invalid power configuration\n");
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return -EINVAL;
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}
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dwc3_octeon_config_gpio((base >> 24) & 1, gpio);
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dwc3_octeon_config_gpio(((u64)base >> 24) & 1, gpio);
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/* Enable XHCI power control and set if active high or low. */
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val = cvmx_read_csr(uctl_host_cfg_reg);
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val = dwc3_octeon_readq(uctl_host_cfg_reg);
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val |= USBDRD_UCTL_HOST_PPC_EN;
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if (power_active_low)
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val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
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else
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val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
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cvmx_write_csr(uctl_host_cfg_reg, val);
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dwc3_octeon_writeq(uctl_host_cfg_reg, val);
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} else {
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/* Disable XHCI power control and set if active high. */
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val = cvmx_read_csr(uctl_host_cfg_reg);
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val = dwc3_octeon_readq(uctl_host_cfg_reg);
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val &= ~USBDRD_UCTL_HOST_PPC_EN;
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val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN;
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cvmx_write_csr(uctl_host_cfg_reg, val);
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dwc3_octeon_writeq(uctl_host_cfg_reg, val);
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dev_info(dev, "power control disabled\n");
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}
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return 0;
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}
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static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base)
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{
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int i, mpll_mul, ref_clk_fsel, ref_clk_sel = 2;
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u32 clock_rate;
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u64 div, h_clk_rate, val;
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u64 uctl_ctl_reg = base + USBDRD_UCTL_CTL;
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void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL;
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if (dev->of_node) {
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const char *ss_clock_type;
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@ -332,16 +351,16 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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/* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
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/* Step 3: Assert all resets. */
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val = cvmx_read_csr(uctl_ctl_reg);
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val |= USBDRD_UCTL_CTL_UPHY_RST |
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USBDRD_UCTL_CTL_UAHC_RST |
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USBDRD_UCTL_CTL_UCTL_RST;
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cvmx_write_csr(uctl_ctl_reg, val);
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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/* Step 4a: Reset the clock dividers. */
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val = cvmx_read_csr(uctl_ctl_reg);
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val |= USBDRD_UCTL_CTL_H_CLKDIV_RST;
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cvmx_write_csr(uctl_ctl_reg, val);
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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/* Step 4b: Select controller clock frequency. */
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for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) {
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@ -350,12 +369,12 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
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break;
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}
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val = cvmx_read_csr(uctl_ctl_reg);
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL;
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val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div);
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val |= USBDRD_UCTL_CTL_H_CLK_EN;
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cvmx_write_csr(uctl_ctl_reg, val);
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val = cvmx_read_csr(uctl_ctl_reg);
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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val = dwc3_octeon_readq(uctl_ctl_reg);
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if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) ||
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(!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) {
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dev_err(dev, "dwc3 controller clock init failure.\n");
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@ -364,10 +383,10 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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/* Step 4c: Deassert the controller clock divider reset. */
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val &= ~USBDRD_UCTL_CTL_H_CLKDIV_RST;
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cvmx_write_csr(uctl_ctl_reg, val);
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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/* Step 5a: Reference clock configuration. */
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val = cvmx_read_csr(uctl_ctl_reg);
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val &= ~USBDRD_UCTL_CTL_REF_CLK_DIV2;
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val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL;
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val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel);
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@ -407,15 +426,15 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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/* Step 6a & 6b: Power up PHYs. */
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val |= USBDRD_UCTL_CTL_HS_POWER_EN;
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val |= USBDRD_UCTL_CTL_SS_POWER_EN;
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cvmx_write_csr(uctl_ctl_reg, val);
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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/* Step 7: Wait 10 controller-clock cycles to take effect. */
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udelay(10);
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/* Step 8a: Deassert UCTL reset signal. */
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val = cvmx_read_csr(uctl_ctl_reg);
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val &= ~USBDRD_UCTL_CTL_UCTL_RST;
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cvmx_write_csr(uctl_ctl_reg, val);
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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/* Step 8b: Wait 10 controller-clock cycles. */
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udelay(10);
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@ -425,49 +444,49 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
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return -EINVAL;
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/* Step 8d: Deassert UAHC reset signal. */
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val = cvmx_read_csr(uctl_ctl_reg);
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val &= ~USBDRD_UCTL_CTL_UAHC_RST;
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cvmx_write_csr(uctl_ctl_reg, val);
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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/* Step 8e: Wait 10 controller-clock cycles. */
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udelay(10);
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/* Step 9: Enable conditional coprocessor clock of UCTL. */
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val = cvmx_read_csr(uctl_ctl_reg);
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val |= USBDRD_UCTL_CTL_CSCLK_EN;
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cvmx_write_csr(uctl_ctl_reg, val);
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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/*Step 10: Set for host mode only. */
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val = cvmx_read_csr(uctl_ctl_reg);
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val &= ~USBDRD_UCTL_CTL_DRD_MODE;
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cvmx_write_csr(uctl_ctl_reg, val);
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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return 0;
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}
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static void __init dwc3_octeon_set_endian_mode(u64 base)
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static void __init dwc3_octeon_set_endian_mode(void __iomem *base)
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{
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u64 val;
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u64 uctl_shim_cfg_reg = base + USBDRD_UCTL_SHIM_CFG;
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void __iomem *uctl_shim_cfg_reg = base + USBDRD_UCTL_SHIM_CFG;
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val = cvmx_read_csr(uctl_shim_cfg_reg);
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val = dwc3_octeon_readq(uctl_shim_cfg_reg);
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val &= ~USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE;
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val &= ~USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE;
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#ifdef __BIG_ENDIAN
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val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1);
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val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1);
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#endif
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cvmx_write_csr(uctl_shim_cfg_reg, val);
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dwc3_octeon_writeq(uctl_shim_cfg_reg, val);
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}
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static void __init dwc3_octeon_phy_reset(u64 base)
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static void __init dwc3_octeon_phy_reset(void __iomem *base)
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{
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u64 val;
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u64 uctl_ctl_reg = base + USBDRD_UCTL_CTL;
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void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL;
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val = cvmx_read_csr(uctl_ctl_reg);
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val = dwc3_octeon_readq(uctl_ctl_reg);
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val &= ~USBDRD_UCTL_CTL_UPHY_RST;
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cvmx_write_csr(uctl_ctl_reg, val);
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dwc3_octeon_writeq(uctl_ctl_reg, val);
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}
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static int __init dwc3_octeon_device_init(void)
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@ -506,10 +525,10 @@ static int __init dwc3_octeon_device_init(void)
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}
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mutex_lock(&dwc3_octeon_clocks_mutex);
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if (dwc3_octeon_clocks_start(&pdev->dev, (u64)base) == 0)
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if (dwc3_octeon_clocks_start(&pdev->dev, base) == 0)
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dev_info(&pdev->dev, "clocks initialized.\n");
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dwc3_octeon_set_endian_mode((u64)base);
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dwc3_octeon_phy_reset((u64)base);
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dwc3_octeon_set_endian_mode(base);
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dwc3_octeon_phy_reset(base);
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mutex_unlock(&dwc3_octeon_clocks_mutex);
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devm_iounmap(&pdev->dev, base);
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devm_release_mem_region(&pdev->dev, res->start,
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