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clk: at91: clk-generated: add mux_table option
Add mux table option. This is necessary for IP versions that has gaps in the range of available clock sources (e.g. SAMA7G5). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-12-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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64c9247b9e
commit
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5 changed files with 16 additions and 8 deletions
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@ -23,6 +23,7 @@ struct clk_generated {
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struct regmap *regmap;
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struct regmap *regmap;
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struct clk_range range;
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struct clk_range range;
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spinlock_t *lock;
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spinlock_t *lock;
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u32 *mux_table;
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u32 id;
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u32 id;
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u32 gckdiv;
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u32 gckdiv;
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const struct clk_pcr_layout *layout;
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const struct clk_pcr_layout *layout;
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@ -201,7 +202,11 @@ static int clk_generated_set_parent(struct clk_hw *hw, u8 index)
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if (index >= clk_hw_get_num_parents(hw))
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if (index >= clk_hw_get_num_parents(hw))
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return -EINVAL;
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return -EINVAL;
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gck->parent_id = index;
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if (gck->mux_table)
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gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);
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else
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gck->parent_id = index;
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return 0;
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return 0;
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}
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}
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@ -273,8 +278,9 @@ struct clk_hw * __init
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at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
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at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
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const struct clk_pcr_layout *layout,
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const struct clk_pcr_layout *layout,
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const char *name, const char **parent_names,
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const char *name, const char **parent_names,
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u8 num_parents, u8 id,
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u32 *mux_table, u8 num_parents, u8 id,
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const struct clk_range *range, int chg_pid)
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const struct clk_range *range,
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int chg_pid)
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{
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{
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struct clk_generated *gck;
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struct clk_generated *gck;
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struct clk_init_data init;
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struct clk_init_data init;
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@ -300,6 +306,7 @@ at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
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gck->range = *range;
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gck->range = *range;
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gck->chg_pid = chg_pid;
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gck->chg_pid = chg_pid;
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gck->layout = layout;
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gck->layout = layout;
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gck->mux_table = mux_table;
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clk_generated_startup(gck);
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clk_generated_startup(gck);
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hw = &gck->hw;
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hw = &gck->hw;
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@ -158,8 +158,9 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
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hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
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hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
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&dt_pcr_layout, name,
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&dt_pcr_layout, name,
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parent_names, num_parents,
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parent_names, NULL,
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id, &range, chg_pid);
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num_parents, id, &range,
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chg_pid);
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if (IS_ERR(hw))
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if (IS_ERR(hw))
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continue;
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continue;
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@ -122,7 +122,7 @@ struct clk_hw * __init
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at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
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at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
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const struct clk_pcr_layout *layout,
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const struct clk_pcr_layout *layout,
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const char *name, const char **parent_names,
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const char *name, const char **parent_names,
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u8 num_parents, u8 id,
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u32 *mux_table, u8 num_parents, u8 id,
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const struct clk_range *range, int chg_pid);
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const struct clk_range *range, int chg_pid);
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struct clk_hw * __init
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struct clk_hw * __init
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@ -288,7 +288,7 @@ static void __init sam9x60_pmc_setup(struct device_node *np)
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hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
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hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
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&sam9x60_pcr_layout,
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&sam9x60_pcr_layout,
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sam9x60_gck[i].n,
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sam9x60_gck[i].n,
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parent_names, 6,
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parent_names, NULL, 6,
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sam9x60_gck[i].id,
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sam9x60_gck[i].id,
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&sam9x60_gck[i].r, INT_MIN);
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&sam9x60_gck[i].r, INT_MIN);
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if (IS_ERR(hw))
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if (IS_ERR(hw))
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@ -321,7 +321,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
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hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
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hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
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&sama5d2_pcr_layout,
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&sama5d2_pcr_layout,
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sama5d2_gck[i].n,
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sama5d2_gck[i].n,
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parent_names, 6,
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parent_names, NULL, 6,
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sama5d2_gck[i].id,
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sama5d2_gck[i].id,
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&sama5d2_gck[i].r,
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&sama5d2_gck[i].r,
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sama5d2_gck[i].chg_pid);
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sama5d2_gck[i].chg_pid);
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