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ARM: arm-soc pinctrl changes for Renesas for 3.10

Browse source 
This is yet another driver change, which is split out just because
 of its size. As already in 3.9, a lot of changes are going on here,
 as the shmobile platform gets converted from its own pin control
 API to the generic drivers/pinctrl subsystem.
 
 Based on agreements with Paul Mundt, we are merging the sh-arch-side
 changes here as well.
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Merge tag 'renesas-pinctrl-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC pinctrl changes for Renesas from Olof Johansson:
 "This is yet another driver change, which is split out just because of
  its size.  As already in 3.9, a lot of changes are going on here, as
  the shmobile platform gets converted from its own pin control API to
  the generic drivers/pinctrl subsystem.

  Based on agreements with Paul Mundt, we are merging the sh-arch-side
  changes here as well"

* tag 'renesas-pinctrl-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (142 commits)
  ARM: shmobile: r8a7779: Remove INTC function GPIOs
  ARM: shmobile: r8a7779: Remove LBSC function GPIOs
  ARM: shmobile: r8a7779: Remove USB function GPIOs
  ARM: shmobile: r8a7779: Remove HSPI function GPIOs
  ARM: shmobile: r8a7779: Remove SCIF function GPIOs
  ARM: shmobile: r8a7779: Remove SDHI and MMCIF function GPIOs
  ARM: shmobile: r8a7779: Remove DU function GPIOs
  ARM: shmobile: r8a7779: Remove DU1_DOTCLKOUT1 GPIO
  ARM: shmobile: r8a7740: Remove SDHI and MMCIF function GPIOs
  ARM: shmobile: r8a7740: Remove LCD0 and LCD1 function GPIOs
  ARM: shmobile: sh73a0: Remove IrDA function GPIOs
  ARM: shmobile: sh73a0: Remove USB function GPIOs
  ARM: shmobile: sh73a0: Remove BSC function GPIOs
  ARM: shmobile: sh73a0: Remove KEYSC function GPIOs
  ARM: shmobile: sh73a0: Remove pull-up function GPIOS
  ARM: shmobile: sh73a0: Remove FSI function GPIOs
  ARM: shmobile: sh73a0: Remove I2C function GPIOs
  ARM: shmobile: sh73a0: Remove SCIFA and SCIFB function GPIOs
  ARM: shmobile: sh73a0: Remove LCDC and LCDC2 function GPIOs
  ARM: shmobile: sh7372: Remove SDHI and MMCIF function GPIOs
  ...
This commit is contained in:
Linus Torvalds 2013-05-04 12:32:41 -07:00
commit 22b154365f
45 changed files with 8671 additions and 5644 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

172
arch/arm/mach-shmobile/board-ag5evm.c
View file

@ -23,6 +23,8 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
@ -304,9 +306,9 @@ static int lcd_backlight_set_brightness(int brightness)
if (brightness == 0) {
/* Reset the chip */
gpio_set_value(GPIO_PORT235, 0);
gpio_set_value(235, 0);
mdelay(24);
gpio_set_value(GPIO_PORT235, 1);
gpio_set_value(235, 1);
return 0;
}
@ -406,7 +408,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
.cd_gpio = GPIO_PORT251,
.cd_gpio = 251,
};
static struct resource sdhi0_resources[] = {
@ -461,7 +463,7 @@ static struct regulator_init_data cn4_power_init_data = {
static struct fixed_voltage_config cn4_power_info = {
.supply_name = "CN4 SD/MMC Vdd",
.microvolts = 3300000,
.gpio = GPIO_PORT114,
.gpio = 114,
.enable_high = 1,
.init_data = &cn4_power_init_data,
};
@ -479,10 +481,10 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
static int power_gpio = -EINVAL;
if (power_gpio < 0) {
int ret = gpio_request_one(GPIO_PORT114, GPIOF_OUT_INIT_LOW,
int ret = gpio_request_one(114, GPIOF_OUT_INIT_LOW,
"sdhi1_power");
if (!ret)
power_gpio = GPIO_PORT114;
power_gpio = 114;
}
/*
@ -493,7 +495,7 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
* regulator driver. We have to live with the race in case the driver
* gets unloaded and the GPIO freed between these two steps.
*/
gpio_set_value(GPIO_PORT114, state);
gpio_set_value(114, state);
}
static struct sh_mobile_sdhi_info sh_sdhi1_info = {
@ -550,6 +552,77 @@ static struct platform_device *ag5evm_devices[] __initdata = {
&sdhi1_device,
};
static unsigned long pin_pullup_conf[] = {
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
};
static const struct pinctrl_map ag5evm_pinctrl_map[] = {
/* FSIA */
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_mclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_sclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_data_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_data_out", "fsia"),
/* I2C2 & I2C3 */
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0",
"i2c2_0", "i2c2"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
"i2c3_0", "i2c3"),
/* IrDA */
PIN_MAP_MUX_GROUP_DEFAULT("sh_irda.0", "pfc-sh73a0",
"irda_0", "irda"),
/* KEYSC */
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_in8", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out04", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out5", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out6_0", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out7_0", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out8_0", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out9_2", "keysc"),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_in8", pin_pullup_conf),
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_ctrl_0", "mmc0"),
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"PORT279", pin_pullup_conf),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", pin_pullup_conf),
/* SCIFA2 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
"scifa2_data_0", "scifa2"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
"scifa2_ctrl_0", "scifa2"),
/* SDHI0 (CN15 [SD I/F]) */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_wp", "sdhi0"),
/* SDHI1 (CN4 [WLAN I/F]) */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
"sdhi1_data4", "sdhi1"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
"sdhi1_ctrl", "sdhi1"),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
"sdhi1_data4", pin_pullup_conf),
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
"PORT263", pin_pullup_conf),
};
static void __init ag5evm_init(void)
{
regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@ -558,96 +631,27 @@ static void __init ag5evm_init(void)
ARRAY_SIZE(fixed2v8_power_consumers), 3300000);
regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
pinctrl_register_mappings(ag5evm_pinctrl_map,
ARRAY_SIZE(ag5evm_pinctrl_map));
sh73a0_pinmux_init();
/* enable SCIFA2 */
gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
/* enable KEYSC */
gpio_request(GPIO_FN_KEYIN0_PU, NULL);
gpio_request(GPIO_FN_KEYIN1_PU, NULL);
gpio_request(GPIO_FN_KEYIN2_PU, NULL);
gpio_request(GPIO_FN_KEYIN3_PU, NULL);
gpio_request(GPIO_FN_KEYIN4_PU, NULL);
gpio_request(GPIO_FN_KEYIN5_PU, NULL);
gpio_request(GPIO_FN_KEYIN6_PU, NULL);
gpio_request(GPIO_FN_KEYIN7_PU, NULL);
gpio_request(GPIO_FN_KEYOUT0, NULL);
gpio_request(GPIO_FN_KEYOUT1, NULL);
gpio_request(GPIO_FN_KEYOUT2, NULL);
gpio_request(GPIO_FN_KEYOUT3, NULL);
gpio_request(GPIO_FN_KEYOUT4, NULL);
gpio_request(GPIO_FN_KEYOUT5, NULL);
gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
gpio_request(GPIO_FN_KEYOUT8, NULL);
gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
/* enable I2C channel 2 and 3 */
gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
/* enable MMCIF */
gpio_request(GPIO_FN_MMCCLK0, NULL);
gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
/* enable SMSC911X */
gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
/* FSI A */
gpio_request(GPIO_FN_FSIACK, NULL);
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAIBT, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
/* IrDA */
gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL);
gpio_request(GPIO_FN_PORT242_IRDA_IN, NULL);
gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
/* LCD panel */
gpio_request_one(GPIO_PORT217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
mdelay(1);
gpio_set_value(GPIO_PORT217, 1);
gpio_set_value(217, 1);
mdelay(100);
/* LCD backlight controller */
gpio_request_one(GPIO_PORT235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
lcd_backlight_set_brightness(0);
/* enable SDHI0 on CN15 [SD I/F] */
gpio_request(GPIO_FN_SDHIWP0, NULL);
gpio_request(GPIO_FN_SDHICMD0, NULL);
gpio_request(GPIO_FN_SDHICLK0, NULL);
gpio_request(GPIO_FN_SDHID0_3, NULL);
gpio_request(GPIO_FN_SDHID0_2, NULL);
gpio_request(GPIO_FN_SDHID0_1, NULL);
gpio_request(GPIO_FN_SDHID0_0, NULL);
/* enable SDHI1 on CN4 [WLAN I/F] */
gpio_request(GPIO_FN_SDHICLK1, NULL);
gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
#ifdef CONFIG_CACHE_L2X0
/* Shared attribute override enable, 64K*8way */
l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);

91
arch/arm/mach-shmobile/board-ap4evb.c
View file

@ -34,6 +34,7 @@
#include <linux/i2c.h>
#include <linux/i2c/tsc2007.h>
#include <linux/io.h>
#include <linux/pinctrl/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
@ -273,11 +274,11 @@ static struct platform_device smc911x_device = {
/*
* The card detect pin of the top SD/MMC slot (CN7) is active low and is
* connected to GPIO A22 of SH7372 (GPIO_PORT41).
* connected to GPIO A22 of SH7372 (GPIO 41).
*/
static int slot_cn7_get_cd(struct platform_device *pdev)
{
return !gpio_get_value(GPIO_PORT41);
return !gpio_get_value(41);
}
/* MERAM */
static struct sh_mobile_meram_info meram_info = {
@ -838,22 +839,22 @@ static struct platform_device fsi_hdmi_device = {
static struct gpio_led ap4evb_leds[] = {
{
.name = "led4",
.gpio = GPIO_PORT185,
.gpio = 185,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led2",
.gpio = GPIO_PORT186,
.gpio = 186,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led3",
.gpio = GPIO_PORT187,
.gpio = 187,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led1",
.gpio = GPIO_PORT188,
.gpio = 188,
.default_state = LEDS_GPIO_DEFSTATE_ON,
}
};
@ -1026,10 +1027,10 @@ static void __init hdmi_init_pm_clock(void)
/* TouchScreen */
#ifdef CONFIG_AP4EVB_QHD
# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
# define GPIO_TSC_PORT GPIO_PORT123
# define GPIO_TSC_PORT 123
#else /* WVGA */
# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
# define GPIO_TSC_PORT GPIO_PORT40
# define GPIO_TSC_PORT 40
#endif
#define IRQ28 evt2irq(0x3380) /* IRQ28A */
@ -1084,6 +1085,28 @@ static struct i2c_board_info i2c1_devices[] = {
};
static const struct pinctrl_map ap4evb_pinctrl_map[] = {
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
"mmc0_data8_0", "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
"mmc0_ctrl_0", "mmc0"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_cd", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_wp", "sdhi0"),
/* SDHI1 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
"sdhi1_data4", "sdhi1"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
"sdhi1_ctrl", "sdhi1"),
};
#define GPIO_PORT9CR IOMEM(0xE6051009)
#define GPIO_PORT10CR IOMEM(0xE605100A)
#define USCCR1 IOMEM(0xE6058144)
@ -1110,6 +1133,8 @@ static void __init ap4evb_init(void)
/* External clock source */
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
pinctrl_register_mappings(ap4evb_pinctrl_map,
ARRAY_SIZE(ap4evb_pinctrl_map));
sh7372_pinmux_init();
/* enable SCIFA0 */
@ -1121,40 +1146,10 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_IRQ6_39, NULL);
/* enable Debug switch (S6) */
gpio_request_one(GPIO_PORT32, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(GPIO_PORT33, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(GPIO_PORT34, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(GPIO_PORT35, GPIOF_IN | GPIOF_EXPORT, NULL);
/* SDHI0 */
gpio_request(GPIO_FN_SDHICD0, NULL);
gpio_request(GPIO_FN_SDHIWP0, NULL);
gpio_request(GPIO_FN_SDHICMD0, NULL);
gpio_request(GPIO_FN_SDHICLK0, NULL);
gpio_request(GPIO_FN_SDHID0_3, NULL);
gpio_request(GPIO_FN_SDHID0_2, NULL);
gpio_request(GPIO_FN_SDHID0_1, NULL);
gpio_request(GPIO_FN_SDHID0_0, NULL);
/* SDHI1 */
gpio_request(GPIO_FN_SDHICMD1, NULL);
gpio_request(GPIO_FN_SDHICLK1, NULL);
gpio_request(GPIO_FN_SDHID1_3, NULL);
gpio_request(GPIO_FN_SDHID1_2, NULL);
gpio_request(GPIO_FN_SDHID1_1, NULL);
gpio_request(GPIO_FN_SDHID1_0, NULL);
/* MMCIF */
gpio_request(GPIO_FN_MMCD0_0, NULL);
gpio_request(GPIO_FN_MMCD0_1, NULL);
gpio_request(GPIO_FN_MMCD0_2, NULL);
gpio_request(GPIO_FN_MMCD0_3, NULL);
gpio_request(GPIO_FN_MMCD0_4, NULL);
gpio_request(GPIO_FN_MMCD0_5, NULL);
gpio_request(GPIO_FN_MMCD0_6, NULL);
gpio_request(GPIO_FN_MMCD0_7, NULL);
gpio_request(GPIO_FN_MMCCMD0, NULL);
gpio_request(GPIO_FN_MMCCLK0, NULL);
gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
/* USB enable */
gpio_request(GPIO_FN_VBUS0_1, NULL);
@ -1172,15 +1167,15 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
gpio_request(GPIO_PORT9, NULL);
gpio_request(GPIO_PORT10, NULL);
gpio_request(9, NULL);
gpio_request(10, NULL);
gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
/* card detect pin for MMC slot (CN7) */
gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
gpio_request_one(41, GPIOF_IN, NULL);
/* setup FSI2 port B (HDMI) */
gpio_request(GPIO_FN_FSIBCK, NULL);
@ -1268,8 +1263,8 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
gpio_request_one(GPIO_PORT189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
lcdc_info.clock_source = LCDC_CLK_BUS;
lcdc_info.ch[0].interface_type = RGB18;

156
arch/arm/mach-shmobile/board-armadillo800eva.c
View file

@ -29,6 +29,7 @@
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/pinctrl/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/sh_eth.h>
@ -230,7 +231,7 @@ static int usbhsf_power_ctrl(struct platform_device *pdev,
static int usbhsf_get_vbus(struct platform_device *pdev)
{
return gpio_get_value(GPIO_PORT209);
return gpio_get_value(209);
}
static irqreturn_t usbhsf_interrupt(int irq, void *data)
@ -540,10 +541,10 @@ static struct platform_device hdmi_lcdc_device = {
{ .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ }
static struct gpio_keys_button gpio_buttons[] = {
GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW3", .wakeup = 1),
GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW4"),
GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW5"),
GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW6"),
GPIO_KEY(KEY_POWER, 99, "SW3", .wakeup = 1),
GPIO_KEY(KEY_BACK, 100, "SW4"),
GPIO_KEY(KEY_MENU, 97, "SW5"),
GPIO_KEY(KEY_HOME, 98, "SW6"),
};
static struct gpio_keys_platform_data gpio_key_info = {
@ -661,6 +662,17 @@ static struct platform_device sdhi1_device = {
.resource = sdhi1_resources,
};
static const struct pinctrl_map eva_sdhi1_pinctrl_map[] = {
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
"sdhi1_data4", "sdhi1"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
"sdhi1_ctrl", "sdhi1"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
"sdhi1_cd", "sdhi1"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
"sdhi1_wp", "sdhi1"),
};
/* MMCIF */
static struct sh_mmcif_plat_data sh_mmcif_plat = {
.sup_pclk = 0,
@ -713,9 +725,9 @@ static int mt9t111_power(struct device *dev, int mode)
/* video1 (= CON1 camera) expect 24MHz */
clk_set_rate(mclk, clk_round_rate(mclk, 24000000));
clk_enable(mclk);
gpio_set_value(GPIO_PORT158, 1);
gpio_set_value(158, 1);
} else {
gpio_set_value(GPIO_PORT158, 0);
gpio_set_value(158, 0);
clk_disable(mclk);
}
@ -869,8 +881,8 @@ static struct platform_device fsi_hdmi_device = {
/* RTC: RTC connects i2c-gpio. */
static struct i2c_gpio_platform_data i2c_gpio_data = {
.sda_pin = GPIO_PORT208,
.scl_pin = GPIO_PORT91,
.sda_pin = 208,
.scl_pin = 91,
.udelay = 5, /* 100 kHz */
};
@ -924,6 +936,28 @@ static struct platform_device *eva_devices[] __initdata = {
&i2c_gpio_device,
};
static const struct pinctrl_map eva_pinctrl_map[] = {
/* LCD0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
"lcd0_data24_0", "lcd0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
"lcd0_lclk_1", "lcd0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
"lcd0_sync", "lcd0"),
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
"mmc0_data8_1", "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
"mmc0_ctrl_1", "mmc0"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
"sdhi0_wp", "sdhi0"),
};
static void __init eva_clock_init(void)
{
struct clk *system = clk_get(NULL, "system_clk");
@ -971,6 +1005,8 @@ static void __init eva_init(void)
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
r8a7740_pinmux_init();
r8a7740_meram_workaround();
@ -980,38 +1016,9 @@ static void __init eva_init(void)
/* LCDC0 */
gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
gpio_request(GPIO_FN_LCD0_D0, NULL);
gpio_request(GPIO_FN_LCD0_D1, NULL);
gpio_request(GPIO_FN_LCD0_D2, NULL);
gpio_request(GPIO_FN_LCD0_D3, NULL);
gpio_request(GPIO_FN_LCD0_D4, NULL);
gpio_request(GPIO_FN_LCD0_D5, NULL);
gpio_request(GPIO_FN_LCD0_D6, NULL);
gpio_request(GPIO_FN_LCD0_D7, NULL);
gpio_request(GPIO_FN_LCD0_D8, NULL);
gpio_request(GPIO_FN_LCD0_D9, NULL);
gpio_request(GPIO_FN_LCD0_D10, NULL);
gpio_request(GPIO_FN_LCD0_D11, NULL);
gpio_request(GPIO_FN_LCD0_D12, NULL);
gpio_request(GPIO_FN_LCD0_D13, NULL);
gpio_request(GPIO_FN_LCD0_D14, NULL);
gpio_request(GPIO_FN_LCD0_D15, NULL);
gpio_request(GPIO_FN_LCD0_D16, NULL);
gpio_request(GPIO_FN_LCD0_D17, NULL);
gpio_request(GPIO_FN_LCD0_D18_PORT40, NULL);
gpio_request(GPIO_FN_LCD0_D19_PORT4, NULL);
gpio_request(GPIO_FN_LCD0_D20_PORT3, NULL);
gpio_request(GPIO_FN_LCD0_D21_PORT2, NULL);
gpio_request(GPIO_FN_LCD0_D22_PORT0, NULL);
gpio_request(GPIO_FN_LCD0_D23_PORT1, NULL);
gpio_request(GPIO_FN_LCD0_DCK, NULL);
gpio_request(GPIO_FN_LCD0_VSYN, NULL);
gpio_request(GPIO_FN_LCD0_HSYN, NULL);
gpio_request(GPIO_FN_LCD0_DISP, NULL);
gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
gpio_request_one(GPIO_PORT202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
/* Touchscreen */
gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */
@ -1037,12 +1044,12 @@ static void __init eva_init(void)
gpio_request(GPIO_FN_ET_RX_DV, NULL);
gpio_request(GPIO_FN_ET_RX_CLK, NULL);
gpio_request_one(GPIO_PORT18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
/* USB */
gpio_request_one(GPIO_PORT159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
gpio_request_one(159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
if (gpio_get_value(GPIO_PORT159)) {
if (gpio_get_value(159)) {
/* USB Host */
} else {
/* USB Func */
@ -1051,47 +1058,22 @@ static void __init eva_init(void)
* OTOH, usbhs interrupt needs its value (HI/LOW) to decide
* USB connection/disconnection (usbhsf_get_vbus()).
* This means we needs to select GPIO_FN_IRQ7_PORT209 first,
* and select GPIO_PORT209 here
* and select GPIO 209 here
*/
gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
gpio_request_one(GPIO_PORT209, GPIOF_IN, NULL);
gpio_request_one(209, GPIOF_IN, NULL);
platform_device_register(&usbhsf_device);
usb = &usbhsf_device;
}
/* SDHI0 */
gpio_request(GPIO_FN_SDHI0_CMD, NULL);
gpio_request(GPIO_FN_SDHI0_CLK, NULL);
gpio_request(GPIO_FN_SDHI0_D0, NULL);
gpio_request(GPIO_FN_SDHI0_D1, NULL);
gpio_request(GPIO_FN_SDHI0_D2, NULL);
gpio_request(GPIO_FN_SDHI0_D3, NULL);
gpio_request(GPIO_FN_SDHI0_WP, NULL);
gpio_request_one(GPIO_PORT17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */
gpio_request_one(GPIO_PORT74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */
gpio_request_one(GPIO_PORT75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */
gpio_request_one(17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */
gpio_request_one(74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */
gpio_request_one(75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */
/* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */
/*
* MMCIF
*
* Here doesn't care SW1.4 status,
* since CON2 is not mounted.
*/
gpio_request(GPIO_FN_MMC1_CLK_PORT103, NULL);
gpio_request(GPIO_FN_MMC1_CMD_PORT104, NULL);
gpio_request(GPIO_FN_MMC1_D0_PORT149, NULL);
gpio_request(GPIO_FN_MMC1_D1_PORT148, NULL);
gpio_request(GPIO_FN_MMC1_D2_PORT147, NULL);
gpio_request(GPIO_FN_MMC1_D3_PORT146, NULL);
gpio_request(GPIO_FN_MMC1_D4_PORT145, NULL);
gpio_request(GPIO_FN_MMC1_D5_PORT144, NULL);
gpio_request(GPIO_FN_MMC1_D6_PORT143, NULL);
gpio_request(GPIO_FN_MMC1_D7_PORT142, NULL);
/* CEU0 */
gpio_request(GPIO_FN_VIO0_D7, NULL);
gpio_request(GPIO_FN_VIO0_D6, NULL);
@ -1108,10 +1090,10 @@ static void __init eva_init(void)
gpio_request(GPIO_FN_VIO_CKO, NULL);
/* CON1/CON15 Camera */
gpio_request_one(GPIO_PORT173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */
gpio_request_one(GPIO_PORT172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */
gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
/* see mt9t111_power() */
gpio_request_one(GPIO_PORT158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */
gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */
/* FSI-WM8978 */
gpio_request(GPIO_FN_FSIAIBT, NULL);
@ -1120,8 +1102,8 @@ static void __init eva_init(void)
gpio_request(GPIO_FN_FSIAOSLD, NULL);
gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL);
gpio_request(GPIO_PORT7, NULL);
gpio_request(GPIO_PORT8, NULL);
gpio_request(7, NULL);
gpio_request(8, NULL);
gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
@ -1138,28 +1120,22 @@ static void __init eva_init(void)
* DBGMD/LCDC0/FSIA MUX
* DBGMD_SELECT_B should be set after setting PFC Function.
*/
gpio_request_one(GPIO_PORT176, GPIOF_OUT_INIT_HIGH, NULL);
gpio_request_one(176, GPIOF_OUT_INIT_HIGH, NULL);
/*
* We can switch CON8/CON14 by SW1.5,
* but it needs after DBGMD_SELECT_B
*/
gpio_request_one(GPIO_PORT6, GPIOF_IN, NULL);
if (gpio_get_value(GPIO_PORT6)) {
gpio_request_one(6, GPIOF_IN, NULL);
if (gpio_get_value(6)) {
/* CON14 enable */
} else {
/* CON8 (SDHI1) enable */
gpio_request(GPIO_FN_SDHI1_CLK, NULL);
gpio_request(GPIO_FN_SDHI1_CMD, NULL);
gpio_request(GPIO_FN_SDHI1_D0, NULL);
gpio_request(GPIO_FN_SDHI1_D1, NULL);
gpio_request(GPIO_FN_SDHI1_D2, NULL);
gpio_request(GPIO_FN_SDHI1_D3, NULL);
gpio_request(GPIO_FN_SDHI1_CD, NULL);
gpio_request(GPIO_FN_SDHI1_WP, NULL);
pinctrl_register_mappings(eva_sdhi1_pinctrl_map,
ARRAY_SIZE(eva_sdhi1_pinctrl_map));
/* SDSLOT2_PON */
gpio_request_one(GPIO_PORT16, GPIOF_OUT_INIT_HIGH, NULL);
gpio_request_one(16, GPIOF_OUT_INIT_HIGH, NULL);
platform_device_register(&sdhi1_device);
}

50
arch/arm/mach-shmobile/board-bonito.c
View file

@ -24,6 +24,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/regulator/fixed.h>
@ -288,6 +289,16 @@ static struct platform_device lcdc0_device = {
},
};
static const struct pinctrl_map lcdc0_pinctrl_map[] = {
/* LCD0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
"lcd0_data24_1", "lcd0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
"lcd0_lclk_1", "lcd0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
"lcd0_sync", "lcd0"),
};
/*
* SMSC 9221
*/
@ -392,8 +403,8 @@ static void __init bonito_init(void)
/*
* base board settings
*/
gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL);
if (!gpio_get_value(GPIO_PORT176)) {
gpio_request_one(176, GPIOF_IN, NULL);
if (!gpio_get_value(176)) {
u16 bsw2;
u16 bsw3;
u16 bsw4;
@ -430,38 +441,11 @@ static void __init bonito_init(void)
*/
if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
gpio_request(GPIO_FN_LCD0_D0, NULL);
gpio_request(GPIO_FN_LCD0_D1, NULL);
gpio_request(GPIO_FN_LCD0_D2, NULL);
gpio_request(GPIO_FN_LCD0_D3, NULL);
gpio_request(GPIO_FN_LCD0_D4, NULL);
gpio_request(GPIO_FN_LCD0_D5, NULL);
gpio_request(GPIO_FN_LCD0_D6, NULL);
gpio_request(GPIO_FN_LCD0_D7, NULL);
gpio_request(GPIO_FN_LCD0_D8, NULL);
gpio_request(GPIO_FN_LCD0_D9, NULL);
gpio_request(GPIO_FN_LCD0_D10, NULL);
gpio_request(GPIO_FN_LCD0_D11, NULL);
gpio_request(GPIO_FN_LCD0_D12, NULL);
gpio_request(GPIO_FN_LCD0_D13, NULL);
gpio_request(GPIO_FN_LCD0_D14, NULL);
gpio_request(GPIO_FN_LCD0_D15, NULL);
gpio_request(GPIO_FN_LCD0_D16, NULL);
gpio_request(GPIO_FN_LCD0_D17, NULL);
gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
gpio_request(GPIO_FN_LCD0_DCK, NULL);
gpio_request(GPIO_FN_LCD0_VSYN, NULL);
gpio_request(GPIO_FN_LCD0_HSYN, NULL);
gpio_request(GPIO_FN_LCD0_DISP, NULL);
gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
pinctrl_register_mappings(lcdc0_pinctrl_map,
ARRAY_SIZE(lcdc0_pinctrl_map));
gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH,
gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
NULL); /* LCDDON */
/* backlight on */

208
arch/arm/mach-shmobile/board-kota2.c
View file

@ -24,6 +24,8 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
@ -135,17 +137,17 @@ static struct platform_device keysc_device = {
#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
static struct gpio_keys_button gpio_buttons[] = {
GPIO_KEY(KEY_VOLUMEUP, GPIO_PORT56, "+"), /* S2: VOL+ [IRQ9] */
GPIO_KEY(KEY_VOLUMEDOWN, GPIO_PORT54, "-"), /* S3: VOL- [IRQ10] */
GPIO_KEY(KEY_MENU, GPIO_PORT27, "Menu"), /* S4: MENU [IRQ30] */
GPIO_KEY(KEY_HOMEPAGE, GPIO_PORT26, "Home"), /* S5: HOME [IRQ31] */
GPIO_KEY(KEY_BACK, GPIO_PORT11, "Back"), /* S6: BACK [IRQ0] */
GPIO_KEY(KEY_PHONE, GPIO_PORT238, "Tel"), /* S7: TEL [IRQ11] */
GPIO_KEY(KEY_POWER, GPIO_PORT239, "C1"), /* S8: CAM [IRQ13] */
GPIO_KEY(KEY_MAIL, GPIO_PORT224, "Mail"), /* S9: MAIL [IRQ3] */
/* Omitted button "C3?": GPIO_PORT223 - S10: CUST [IRQ8] */
GPIO_KEY(KEY_CAMERA, GPIO_PORT164, "C2"), /* S11: CAM_HALF [IRQ25] */
/* Omitted button "?": GPIO_PORT152 - S12: CAM_FULL [No IRQ] */
GPIO_KEY(KEY_VOLUMEUP, 56, "+"), /* S2: VOL+ [IRQ9] */
GPIO_KEY(KEY_VOLUMEDOWN, 54, "-"), /* S3: VOL- [IRQ10] */
GPIO_KEY(KEY_MENU, 27, "Menu"), /* S4: MENU [IRQ30] */
GPIO_KEY(KEY_HOMEPAGE, 26, "Home"), /* S5: HOME [IRQ31] */
GPIO_KEY(KEY_BACK, 11, "Back"), /* S6: BACK [IRQ0] */
GPIO_KEY(KEY_PHONE, 238, "Tel"), /* S7: TEL [IRQ11] */
GPIO_KEY(KEY_POWER, 239, "C1"), /* S8: CAM [IRQ13] */
GPIO_KEY(KEY_MAIL, 224, "Mail"), /* S9: MAIL [IRQ3] */
/* Omitted button "C3?": 223 - S10: CUST [IRQ8] */
GPIO_KEY(KEY_CAMERA, 164, "C2"), /* S11: CAM_HALF [IRQ25] */
/* Omitted button "?": 152 - S12: CAM_FULL [No IRQ] */
};
static struct gpio_keys_platform_data gpio_key_info = {
@ -165,9 +167,9 @@ static struct platform_device gpio_keys_device = {
#define GPIO_LED(n, g) { .name = n, .gpio = g }
static struct gpio_led gpio_leds[] = {
GPIO_LED("G", GPIO_PORT20), /* PORT20 [GPO0] -> LED7 -> "G" */
GPIO_LED("H", GPIO_PORT21), /* PORT21 [GPO1] -> LED8 -> "H" */
GPIO_LED("J", GPIO_PORT22), /* PORT22 [GPO2] -> LED9 -> "J" */
GPIO_LED("G", 20), /* PORT20 [GPO0] -> LED7 -> "G" */
GPIO_LED("H", 21), /* PORT21 [GPO1] -> LED8 -> "H" */
GPIO_LED("J", 22), /* PORT22 [GPO2] -> LED9 -> "J" */
};
static struct gpio_led_platform_data gpio_leds_info = {
@ -187,7 +189,7 @@ static struct platform_device gpio_leds_device = {
static struct led_renesas_tpu_config led_renesas_tpu12_pdata = {
.name = "V2513",
.pin_gpio_fn = GPIO_FN_TPU1TO2,
.pin_gpio = GPIO_PORT153,
.pin_gpio = 153,
.channel_offset = 0x90,
.timer_bit = 2,
.max_brightness = 1000,
@ -215,7 +217,7 @@ static struct platform_device leds_tpu12_device = {
static struct led_renesas_tpu_config led_renesas_tpu41_pdata = {
.name = "V2514",
.pin_gpio_fn = GPIO_FN_TPU4TO1,
.pin_gpio = GPIO_PORT199,
.pin_gpio = 199,
.channel_offset = 0x50,
.timer_bit = 1,
.max_brightness = 1000,
@ -243,7 +245,7 @@ static struct platform_device leds_tpu41_device = {
static struct led_renesas_tpu_config led_renesas_tpu21_pdata = {
.name = "V2515",
.pin_gpio_fn = GPIO_FN_TPU2TO1,
.pin_gpio = GPIO_PORT197,
.pin_gpio = 197,
.channel_offset = 0x50,
.timer_bit = 1,
.max_brightness = 1000,
@ -271,7 +273,7 @@ static struct platform_device leds_tpu21_device = {
static struct led_renesas_tpu_config led_renesas_tpu30_pdata = {
.name = "KEYLED",
.pin_gpio_fn = GPIO_FN_TPU3TO0,
.pin_gpio = GPIO_PORT163,
.pin_gpio = 163,
.channel_offset = 0x10,
.timer_bit = 0,
.max_brightness = 1000,
@ -433,6 +435,85 @@ static struct platform_device *kota2_devices[] __initdata = {
&sdhi1_device,
};
static unsigned long pin_pullup_conf[] = {
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
};
static const struct pinctrl_map kota2_pinctrl_map[] = {
/* KEYSC */
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_in8", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out04", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out5", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out6_0", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out7_0", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out8_0", "keysc"),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_in8", pin_pullup_conf),
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_ctrl_0", "mmc0"),
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"PORT279", pin_pullup_conf),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", pin_pullup_conf),
/* SCIFA2 (UART2) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
"scifa2_data_0", "scifa2"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
"scifa2_ctrl_0", "scifa2"),
/* SCIFA4 (UART1) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
"scifa4_data", "scifa4"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
"scifa4_ctrl", "scifa4"),
/* SCIFB (BT) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
"scifb_data_0", "scifb"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
"scifb_clk_0", "scifb"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
"scifb_ctrl_0", "scifb"),
/* SDHI0 (microSD) */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_cd", "sdhi0"),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_data4", pin_pullup_conf),
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"PORT256", pin_pullup_conf),
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"PORT251", pin_pullup_conf),
/* SDHI1 (BCM4330) */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
"sdhi1_data4", "sdhi1"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
"sdhi1_ctrl", "sdhi1"),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
"sdhi1_data4", pin_pullup_conf),
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
"PORT263", pin_pullup_conf),
/* SMSC911X */
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
"bsc_data_0_7", "bsc"),
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
"bsc_data_8_15", "bsc"),
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
"bsc_cs5_a", "bsc"),
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
"bsc_we0", "bsc"),
};
static void __init kota2_init(void)
{
regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@ -441,97 +522,16 @@ static void __init kota2_init(void)
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
pinctrl_register_mappings(kota2_pinctrl_map,
ARRAY_SIZE(kota2_pinctrl_map));
sh73a0_pinmux_init();
/* SCIFA2 (UART2) */
gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
/* SCIFA4 (UART1) */
gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
/* SMSC911X */
gpio_request(GPIO_FN_D0_NAF0, NULL);
gpio_request(GPIO_FN_D1_NAF1, NULL);
gpio_request(GPIO_FN_D2_NAF2, NULL);
gpio_request(GPIO_FN_D3_NAF3, NULL);
gpio_request(GPIO_FN_D4_NAF4, NULL);
gpio_request(GPIO_FN_D5_NAF5, NULL);
gpio_request(GPIO_FN_D6_NAF6, NULL);
gpio_request(GPIO_FN_D7_NAF7, NULL);
gpio_request(GPIO_FN_D8_NAF8, NULL);
gpio_request(GPIO_FN_D9_NAF9, NULL);
gpio_request(GPIO_FN_D10_NAF10, NULL);
gpio_request(GPIO_FN_D11_NAF11, NULL);
gpio_request(GPIO_FN_D12_NAF12, NULL);
gpio_request(GPIO_FN_D13_NAF13, NULL);
gpio_request(GPIO_FN_D14_NAF14, NULL);
gpio_request(GPIO_FN_D15_NAF15, NULL);
gpio_request(GPIO_FN_CS5A_, NULL);
gpio_request(GPIO_FN_WE0__FWE, NULL);
gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
/* KEYSC */
gpio_request(GPIO_FN_KEYIN0_PU, NULL);
gpio_request(GPIO_FN_KEYIN1_PU, NULL);
gpio_request(GPIO_FN_KEYIN2_PU, NULL);
gpio_request(GPIO_FN_KEYIN3_PU, NULL);
gpio_request(GPIO_FN_KEYIN4_PU, NULL);
gpio_request(GPIO_FN_KEYIN5_PU, NULL);
gpio_request(GPIO_FN_KEYIN6_PU, NULL);
gpio_request(GPIO_FN_KEYIN7_PU, NULL);
gpio_request(GPIO_FN_KEYOUT0, NULL);
gpio_request(GPIO_FN_KEYOUT1, NULL);
gpio_request(GPIO_FN_KEYOUT2, NULL);
gpio_request(GPIO_FN_KEYOUT3, NULL);
gpio_request(GPIO_FN_KEYOUT4, NULL);
gpio_request(GPIO_FN_KEYOUT5, NULL);
gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
gpio_request(GPIO_FN_KEYOUT8, NULL);
gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
/* MMCIF */
gpio_request(GPIO_FN_MMCCLK0, NULL);
gpio_request(GPIO_FN_MMCD0_0, NULL);
gpio_request(GPIO_FN_MMCD0_1, NULL);
gpio_request(GPIO_FN_MMCD0_2, NULL);
gpio_request(GPIO_FN_MMCD0_3, NULL);
gpio_request(GPIO_FN_MMCD0_4, NULL);
gpio_request(GPIO_FN_MMCD0_5, NULL);
gpio_request(GPIO_FN_MMCD0_6, NULL);
gpio_request(GPIO_FN_MMCD0_7, NULL);
gpio_request(GPIO_FN_MMCCMD0, NULL);
gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
/* SDHI0 (microSD) */
gpio_request(GPIO_FN_SDHICD0_PU, NULL);
gpio_request(GPIO_FN_SDHICMD0_PU, NULL);
gpio_request(GPIO_FN_SDHICLK0, NULL);
gpio_request(GPIO_FN_SDHID0_3_PU, NULL);
gpio_request(GPIO_FN_SDHID0_2_PU, NULL);
gpio_request(GPIO_FN_SDHID0_1_PU, NULL);
gpio_request(GPIO_FN_SDHID0_0_PU, NULL);
/* SCIFB (BT) */
gpio_request(GPIO_FN_PORT159_SCIFB_SCK, NULL);
gpio_request(GPIO_FN_PORT160_SCIFB_TXD, NULL);
gpio_request(GPIO_FN_PORT161_SCIFB_CTS_, NULL);
gpio_request(GPIO_FN_PORT162_SCIFB_RXD, NULL);
gpio_request(GPIO_FN_PORT163_SCIFB_RTS_, NULL);
/* SDHI1 (BCM4330) */
gpio_request(GPIO_FN_SDHICLK1, NULL);
gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*8way */

152
arch/arm/mach-shmobile/board-kzm9g.c
View file

@ -30,6 +30,8 @@
#include <linux/mmc/sh_mmcif.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mfd/tmio.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
@ -437,7 +439,7 @@ static struct sh_mobile_sdhi_info sdhi2_info = {
TMIO_MMC_WRPROTECT_DISABLE,
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
.cd_gpio = GPIO_PORT13,
.cd_gpio = 13,
};
static struct resource sdhi2_resources[] = {
@ -603,6 +605,64 @@ static struct platform_device *kzm_devices[] __initdata = {
&fsi_ak4648_device,
};
static unsigned long pin_pullup_conf[] = {
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
};
static const struct pinctrl_map kzm_pinctrl_map[] = {
/* FSIA (AK4648) */
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_mclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_sclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_data_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_data_out", "fsia"),
/* I2C3 */
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
"i2c3_1", "i2c3"),
/* LCD */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
"lcd_data24", "lcd"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
"lcd_sync", "lcd"),
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_ctrl_0", "mmc0"),
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"PORT279", pin_pullup_conf),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", pin_pullup_conf),
/* SCIFA4 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
"scifa4_data", "scifa4"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
"scifa4_ctrl", "scifa4"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_cd", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_wp", "sdhi0"),
/* SDHI2 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
"sdhi2_data4", "sdhi2"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
"sdhi2_ctrl", "sdhi2"),
/* SMSC */
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
"bsc_cs4", "bsc"),
/* USB */
PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0",
"usb_vbus", "usb"),
};
/*
* FIXME
*
@ -664,100 +724,26 @@ static void __init kzm_init(void)
ARRAY_SIZE(fixed2v8_power_consumers), 2800000);
regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
sh73a0_pinmux_init();
/* enable SCIFA4 */
gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
/* CS4 for SMSC/USB */
gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */
/* SMSC */
gpio_request_one(GPIO_PORT224, GPIOF_IN, NULL); /* IRQ3 */
gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */
/* LCDC */
gpio_request(GPIO_FN_LCDD23, NULL);
gpio_request(GPIO_FN_LCDD22, NULL);
gpio_request(GPIO_FN_LCDD21, NULL);
gpio_request(GPIO_FN_LCDD20, NULL);
gpio_request(GPIO_FN_LCDD19, NULL);
gpio_request(GPIO_FN_LCDD18, NULL);
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD9, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDD0, NULL);
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
gpio_request_one(GPIO_PORT222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
gpio_request_one(GPIO_PORT226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
/* Touchscreen */
gpio_request_one(GPIO_PORT223, GPIOF_IN, NULL); /* IRQ8 */
/* enable MMCIF */
gpio_request(GPIO_FN_MMCCLK0, NULL);
gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
/* enable SD */
gpio_request(GPIO_FN_SDHIWP0, NULL);
gpio_request(GPIO_FN_SDHICD0, NULL);
gpio_request(GPIO_FN_SDHICMD0, NULL);
gpio_request(GPIO_FN_SDHICLK0, NULL);
gpio_request(GPIO_FN_SDHID0_3, NULL);
gpio_request(GPIO_FN_SDHID0_2, NULL);
gpio_request(GPIO_FN_SDHID0_1, NULL);
gpio_request(GPIO_FN_SDHID0_0, NULL);
gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
/* enable Micro SD */
gpio_request(GPIO_FN_SDHID2_0, NULL);
gpio_request(GPIO_FN_SDHID2_1, NULL);
gpio_request(GPIO_FN_SDHID2_2, NULL);
gpio_request(GPIO_FN_SDHID2_3, NULL);
gpio_request(GPIO_FN_SDHICMD2, NULL);
gpio_request(GPIO_FN_SDHICLK2, NULL);
gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
/* I2C 3 */
gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
/* enable FSI2 port A (ak4648) */
gpio_request(GPIO_FN_FSIACK, NULL);
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAIBT, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
/* enable USB */
gpio_request(GPIO_FN_VBUS_0, NULL);
gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*8way */

102
arch/arm/mach-shmobile/board-mackerel.c
View file

@ -40,6 +40,7 @@
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/sh_flctl.h>
#include <linux/pinctrl/machine.h>
#include <linux/pm_clock.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
@ -363,7 +364,7 @@ static struct fb_videomode mackerel_lcdc_modes[] = {
static int mackerel_set_brightness(int brightness)
{
gpio_set_value(GPIO_PORT31, brightness);
gpio_set_value(31, brightness);
return 0;
}
@ -825,22 +826,22 @@ static struct platform_device usbhs1_device = {
static struct gpio_led mackerel_leds[] = {
{
.name = "led0",
.gpio = GPIO_PORT0,
.gpio = 0,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led1",
.gpio = GPIO_PORT1,
.gpio = 1,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led2",
.gpio = GPIO_PORT2,
.gpio = 2,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led3",
.gpio = GPIO_PORT159,
.gpio = 159,
.default_state = LEDS_GPIO_DEFSTATE_ON,
}
};
@ -970,11 +971,11 @@ static struct platform_device nand_flash_device = {
/*
* The card detect pin of the top SD/MMC slot (CN7) is active low and is
* connected to GPIO A22 of SH7372 (GPIO_PORT41).
* connected to GPIO A22 of SH7372 (GPIO 41).
*/
static int slot_cn7_get_cd(struct platform_device *pdev)
{
return !gpio_get_value(GPIO_PORT41);
return !gpio_get_value(41);
}
/* SDHI0 */
@ -983,7 +984,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
.tmio_flags = TMIO_MMC_USE_GPIO_CD,
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
.cd_gpio = GPIO_PORT172,
.cd_gpio = 172,
};
static struct resource sdhi0_resources[] = {
@ -1066,11 +1067,11 @@ static struct platform_device sdhi1_device = {
/*
* The card detect pin of the top SD/MMC slot (CN23) is active low and is
* connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162).
* connected to GPIO SCIFB_SCK of SH7372 (162).
*/
static int slot_cn23_get_cd(struct platform_device *pdev)
{
return !gpio_get_value(GPIO_PORT162);
return !gpio_get_value(162);
}
/* SDHI2 */
@ -1334,6 +1335,33 @@ static struct i2c_board_info i2c1_devices[] = {
},
};
static const struct pinctrl_map mackerel_pinctrl_map[] = {
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
"mmc0_data8_0", "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
"mmc0_ctrl_0", "mmc0"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_wp", "sdhi0"),
/* SDHI1 */
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
"sdhi1_data4", "sdhi1"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
"sdhi1_ctrl", "sdhi1"),
#endif
/* SDHI2 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
"sdhi2_data4", "sdhi2"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
"sdhi2_ctrl", "sdhi2"),
};
#define GPIO_PORT9CR IOMEM(0xE6051009)
#define GPIO_PORT10CR IOMEM(0xE605100A)
#define GPIO_PORT167CR IOMEM(0xE60520A7)
@ -1370,6 +1398,8 @@ static void __init mackerel_init(void)
/* External clock source */
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
pinctrl_register_mappings(mackerel_pinctrl_map,
ARRAY_SIZE(mackerel_pinctrl_map));
sh7372_pinmux_init();
/* enable SCIFA0 */
@ -1409,9 +1439,9 @@ static void __init mackerel_init(void)
gpio_request(GPIO_FN_LCDDCK, NULL);
/* backlight, off by default */
gpio_request_one(GPIO_PORT31, GPIOF_OUT_INIT_LOW, NULL);
gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
/* USBHS0 */
gpio_request(GPIO_FN_VBUS0_0, NULL);
@ -1427,10 +1457,10 @@ static void __init mackerel_init(void)
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
gpio_request(GPIO_PORT9, NULL);
gpio_request(GPIO_PORT10, NULL);
gpio_request(9, NULL);
gpio_request(10, NULL);
gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
@ -1459,52 +1489,14 @@ static void __init mackerel_init(void)
gpio_request(GPIO_FN_IRQ21, NULL);
irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
/* enable SDHI0 */
gpio_request(GPIO_FN_SDHIWP0, NULL);
gpio_request(GPIO_FN_SDHICMD0, NULL);
gpio_request(GPIO_FN_SDHICLK0, NULL);
gpio_request(GPIO_FN_SDHID0_3, NULL);
gpio_request(GPIO_FN_SDHID0_2, NULL);
gpio_request(GPIO_FN_SDHID0_1, NULL);
gpio_request(GPIO_FN_SDHID0_0, NULL);
/* SDHI0 PORT172 card-detect IRQ26 */
gpio_request(GPIO_FN_IRQ26_172, NULL);
#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
/* enable SDHI1 */
gpio_request(GPIO_FN_SDHICMD1, NULL);
gpio_request(GPIO_FN_SDHICLK1, NULL);
gpio_request(GPIO_FN_SDHID1_3, NULL);
gpio_request(GPIO_FN_SDHID1_2, NULL);
gpio_request(GPIO_FN_SDHID1_1, NULL);
gpio_request(GPIO_FN_SDHID1_0, NULL);
#endif
/* card detect pin for MMC slot (CN7) */
gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
/* enable SDHI2 */
gpio_request(GPIO_FN_SDHICMD2, NULL);
gpio_request(GPIO_FN_SDHICLK2, NULL);
gpio_request(GPIO_FN_SDHID2_3, NULL);
gpio_request(GPIO_FN_SDHID2_2, NULL);
gpio_request(GPIO_FN_SDHID2_1, NULL);
gpio_request(GPIO_FN_SDHID2_0, NULL);
gpio_request_one(41, GPIOF_IN, NULL);
/* card detect pin for microSD slot (CN23) */
gpio_request_one(GPIO_PORT162, GPIOF_IN, NULL);
/* MMCIF */
gpio_request(GPIO_FN_MMCD0_0, NULL);
gpio_request(GPIO_FN_MMCD0_1, NULL);
gpio_request(GPIO_FN_MMCD0_2, NULL);
gpio_request(GPIO_FN_MMCD0_3, NULL);
gpio_request(GPIO_FN_MMCD0_4, NULL);
gpio_request(GPIO_FN_MMCD0_5, NULL);
gpio_request(GPIO_FN_MMCD0_6, NULL);
gpio_request(GPIO_FN_MMCD0_7, NULL);
gpio_request(GPIO_FN_MMCCMD0, NULL);
gpio_request(GPIO_FN_MMCCLK0, NULL);
gpio_request_one(162, GPIOF_IN, NULL);
/* FLCTL */
gpio_request(GPIO_FN_D0_NAF0, NULL);

75
arch/arm/mach-shmobile/board-marzen.c
View file

@ -25,8 +25,8 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>
#include <linux/pinctrl/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
@ -327,6 +327,41 @@ void __init marzen_init_late(void)
ARRAY_SIZE(marzen_late_devices));
}
static const struct pinctrl_map marzen_pinctrl_map[] = {
/* HSPI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
"hspi0", "hspi0"),
/* SCIF2 (CN18: DEBUG0) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
"scif2_data_c", "scif2"),
/* SCIF4 (CN19: DEBUG1) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
"scif4_data", "scif4"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_cd", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_wp", "sdhi0"),
/* SMSC */
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
"intc_irq1_b", "intc"),
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
"lbsc_ex_cs0", "lbsc"),
/* USB0 */
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
"usb0", "usb0"),
/* USB1 */
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
"usb1", "usb1"),
/* USB2 */
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779",
"usb2", "usb2"),
};
static void __init marzen_init(void)
{
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@ -334,44 +369,10 @@ static void __init marzen_init(void)
regulator_register_fixed(1, dummy_supplies,
ARRAY_SIZE(dummy_supplies));
pinctrl_register_mappings(marzen_pinctrl_map,
ARRAY_SIZE(marzen_pinctrl_map));
r8a7779_pinmux_init();
/* SCIF2 (CN18: DEBUG0) */
gpio_request(GPIO_FN_TX2_C, NULL);
gpio_request(GPIO_FN_RX2_C, NULL);
/* SCIF4 (CN19: DEBUG1) */
gpio_request(GPIO_FN_TX4, NULL);
gpio_request(GPIO_FN_RX4, NULL);
/* LAN89218 */
gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
/* SD0 (CN20) */
gpio_request(GPIO_FN_SD0_CLK, NULL);
gpio_request(GPIO_FN_SD0_CMD, NULL);
gpio_request(GPIO_FN_SD0_DAT0, NULL);
gpio_request(GPIO_FN_SD0_DAT1, NULL);
gpio_request(GPIO_FN_SD0_DAT2, NULL);
gpio_request(GPIO_FN_SD0_DAT3, NULL);
gpio_request(GPIO_FN_SD0_CD, NULL);
gpio_request(GPIO_FN_SD0_WP, NULL);
/* HSPI 0 */
gpio_request(GPIO_FN_HSPI_CLK0, NULL);
gpio_request(GPIO_FN_HSPI_CS0, NULL);
gpio_request(GPIO_FN_HSPI_TX0, NULL);
gpio_request(GPIO_FN_HSPI_RX0, NULL);
/* USB (CN21) */
gpio_request(GPIO_FN_USB_OVC0, NULL);
gpio_request(GPIO_FN_USB_OVC1, NULL);
gpio_request(GPIO_FN_USB_OVC2, NULL);
/* USB (CN22) */
gpio_request(GPIO_FN_USB_PENC2, NULL);
r8a7779_add_standard_devices();
platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
}

74
arch/arm/mach-shmobile/include/mach/r8a7740.h
View file

@ -241,48 +241,9 @@ enum {
/* LCD0 */
GPIO_FN_LCDC0_SELECT,
GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
/* LCD1 */
GPIO_FN_LCDC1_SELECT,
GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
/* RSPI */
GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
@ -346,26 +307,6 @@ enum {
GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
GPIO_FN_SIM_D_PORT199,
/* SDHI0 */
GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
/* SDHI1 */
GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
/* SDHI2 */
GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
GPIO_FN_SDHI2_WP_PORT25,
GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
GPIO_FN_SDHI2_CD_PORT202,
/* MSIOF2 */
GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
@ -417,21 +358,6 @@ enum {
GPIO_FN_MEMC_DREQ1,
GPIO_FN_MEMC_A0,
/* MMC */
GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
GPIO_FN_MMC0_CLK_PORT66,
GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
GPIO_FN_MMC1_CLK_PORT103,
GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
/* MSIOF0 */
GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,

324
arch/arm/mach-shmobile/include/mach/r8a7779.h
View file

@ -71,128 +71,125 @@ enum {
GPIO_FN_A19,
/* IPSR0 */
GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS,
GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
GPIO_FN_HCTS1, GPIO_FN_A0,
GPIO_FN_FD3, GPIO_FN_A20,
GPIO_FN_A21,
GPIO_FN_A22, GPIO_FN_VI1_R0,
GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_VI1_R1,
GPIO_FN_A24, GPIO_FN_FD4,
GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
GPIO_FN_FD5,
GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B,
GPIO_FN_CLKOUT, GPIO_FN_PWM0_B,
GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
GPIO_FN_VI1_R7, GPIO_FN_HRTS1,
/* IPSR1 */
GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
GPIO_FN_FD6, GPIO_FN_FD7,
GPIO_FN_FALE,
GPIO_FN_ATACS00,
GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4,
GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B,
GPIO_FN_SSI_SDATA9,
GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5,
GPIO_FN_HTX1, GPIO_FN_SSI_SCK9,
GPIO_FN_FD1,
GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1,
GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
GPIO_FN_MLB_SIG, GPIO_FN_PWM3,
GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_HTX0,
GPIO_FN_SDATA, GPIO_FN_SUB_TCK,
GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
/* IPSR2 */
GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
GPIO_FN_HRX0, GPIO_FN_SCKZ,
GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
GPIO_FN_HSCK0, GPIO_FN_MTS, GPIO_FN_PWM5,
GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0,
GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_SCIF_CLK_C,
GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
GPIO_FN_MDATA, GPIO_FN_SUB_TMS,
GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33,
GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1,
GPIO_FN_LCDOUT2, GPIO_FN_LCDOUT3,
GPIO_FN_LCDOUT4, GPIO_FN_LCDOUT5,
GPIO_FN_LCDOUT6, GPIO_FN_LCDOUT7,
GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
GPIO_FN_AUDATA2,
/* IPSR3 */
GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
GPIO_FN_AUDATA3, GPIO_FN_LCDOUT10,
GPIO_FN_LCDOUT11, GPIO_FN_LCDOUT12,
GPIO_FN_LCDOUT13, GPIO_FN_LCDOUT14,
GPIO_FN_LCDOUT15, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4,
GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
GPIO_FN_AUDATA5, GPIO_FN_LCDOUT18,
GPIO_FN_LCDOUT19, GPIO_FN_LCDOUT20,
GPIO_FN_LCDOUT21, GPIO_FN_LCDOUT22,
GPIO_FN_LCDOUT23,
GPIO_FN_QSTVA_QVS, GPIO_FN_SCL3_B,
GPIO_FN_QCLK,
GPIO_FN_QSTVB_QVE, GPIO_FN_SDA3_B,
GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
GPIO_FN_QSTH_QHS,
GPIO_FN_QSTB_QHE,
GPIO_FN_QCPV_QDE,
GPIO_FN_CAN1_TX, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
/* IPSR4 */
GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C,
GPIO_FN_QPOLB, GPIO_FN_CAN1_RX,
GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B,
GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6,
GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
GPIO_FN_AUDSYNC,
GPIO_FN_VI2_G0,
GPIO_FN_VI2_G1, GPIO_FN_VI2_G2,
GPIO_FN_VI2_G3, GPIO_FN_VI2_G4,
GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2,
GPIO_FN_SCL1_B, GPIO_FN_AUDATA6,
GPIO_FN_VI2_DATA3_VI2_B3,
GPIO_FN_SDA1_B, GPIO_FN_AUDATA7,
GPIO_FN_VI2_G6,
GPIO_FN_VI2_G7, GPIO_FN_VI2_R0,
GPIO_FN_VI2_R1, GPIO_FN_VI2_R2,
GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4,
GPIO_FN_SCL2_B,
/* IPSR5 */
GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
GPIO_FN_VI2_R4, GPIO_FN_VI2_R5,
GPIO_FN_VI2_R6, GPIO_FN_VI2_R7,
GPIO_FN_SCL2_D, GPIO_FN_SDA2_D,
GPIO_FN_VI2_CLKENB,
GPIO_FN_SCL1_D, GPIO_FN_VI2_FIELD,
GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC,
GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC,
GPIO_FN_VI3_VSYNC,
GPIO_FN_VI2_CLK,
GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
GPIO_FN_AUDIO_CLKC, GPIO_FN_SPEEDIN,
GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6,
GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B,
GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
GPIO_FN_VI2_DATA7_VI2_B7,
GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C,
GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
GPIO_FN_AUDIO_CLKB, GPIO_FN_CAN_DEBUGOUT0,
GPIO_FN_MOUT0,
/* IPSR6 */
@ -208,85 +205,84 @@ enum {
GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12,
GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
/* IPSR7 */
GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
GPIO_FN_CTS1_B,
GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13,
GPIO_FN_SSI_SCK9_B, GPIO_FN_SSI_WS78,
GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_WS9_B,
GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
GPIO_FN_TCLK1_C,
GPIO_FN_SSI_SDATA8, GPIO_FN_VSP,
GPIO_FN_ATACS01,
GPIO_FN_ATACS11, GPIO_FN_CC5_TDO,
GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST,
GPIO_FN_ATAG1, GPIO_FN_CC5_TMS,
GPIO_FN_ATARD1, GPIO_FN_CC5_TCK,
GPIO_FN_ATAWR1, GPIO_FN_CC5_TDI,
GPIO_FN_DREQ2, GPIO_FN_DACK2,
/* IPSR8 */
GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
GPIO_FN_AD_CLK,
GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36,
GPIO_FN_AD_DI,
GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37,
GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38,
GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB,
GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD,
GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
GPIO_FN_HSCK1_B,
GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
GPIO_FN_PWMFSW0_C,
/* IPSR9 */
GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_VI0_DATA3_VI0_B3,
GPIO_FN_VI0_DATA4_VI0_B4,
GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_VI0_DATA6_VI0_B6,
GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
GPIO_FN_SSI_SCK78_C, GPIO_FN_ARM_TRACEDATA_2,
GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C,
GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV,
GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
GPIO_FN_ETH_TX_EN, GPIO_FN_ARM_TRACEDATA_6,
GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER,
GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
GPIO_FN_ETH_RXD1, GPIO_FN_ARM_TRACEDATA_9,
/* IPSR10 */
GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_DREQ1_B,
GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
GPIO_FN_ARM_TRACEDATA_12,
GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC,
GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
GPIO_FN_ARM_TRACEDATA_14,
GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
GPIO_FN_ARM_TRACEDATA_15,
GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
GPIO_FN_DREQ2_C, GPIO_FN_TRACECLK,
GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
GPIO_FN_DACK2_C, GPIO_FN_SCIF_CLK_D,
GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
@ -294,35 +290,35 @@ enum {
GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
/* IPSR11 */
GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SIM_RST,
GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2,
GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_MT0_BEN,
GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS,
GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM,
GPIO_FN_SPA_TDI, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B,
GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B,
GPIO_FN_HRTS0_B,
/* IPSR12 */
GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_SIM_D_B,
GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
GPIO_FN_GPS_MAG, GPIO_FN_FCE,
};
struct platform_device;

29
arch/arm/mach-shmobile/include/mach/sh7372.h
View file

@ -294,21 +294,6 @@ enum {
GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14,
GPIO_FN_D15_NAF15,
/*
* MMCIF(1) (PORT 84, 85, 86, 87, 88, 89,
* 90, 91, 92, 99)
*/
GPIO_FN_MMCD0_0, GPIO_FN_MMCD0_1, GPIO_FN_MMCD0_2,
GPIO_FN_MMCD0_3, GPIO_FN_MMCD0_4, GPIO_FN_MMCD0_5,
GPIO_FN_MMCD0_6, GPIO_FN_MMCD0_7,
GPIO_FN_MMCCMD0, GPIO_FN_MMCCLK0,
/* MMCIF(2) (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */
GPIO_FN_MMCD1_0, GPIO_FN_MMCD1_1, GPIO_FN_MMCD1_2,
GPIO_FN_MMCD1_3, GPIO_FN_MMCD1_4, GPIO_FN_MMCD1_5,
GPIO_FN_MMCD1_6, GPIO_FN_MMCD1_7,
GPIO_FN_MMCCLK1, GPIO_FN_MMCCMD1,
/* SPU2 (PORT 65) */
GPIO_FN_VINT_I,
@ -416,20 +401,6 @@ enum {
/* HDMI (PORT 169, 170) */
GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC,
/* SDHI0 (PORT 171, 172, 173, 174, 175, 176, 177, 178) */
GPIO_FN_SDHICLK0, GPIO_FN_SDHICD0,
GPIO_FN_SDHICMD0, GPIO_FN_SDHIWP0,
GPIO_FN_SDHID0_0, GPIO_FN_SDHID0_1,
GPIO_FN_SDHID0_2, GPIO_FN_SDHID0_3,
/* SDHI1 (PORT 179, 180, 181, 182, 183, 184) */
GPIO_FN_SDHICLK1, GPIO_FN_SDHICMD1, GPIO_FN_SDHID1_0,
GPIO_FN_SDHID1_1, GPIO_FN_SDHID1_2, GPIO_FN_SDHID1_3,
/* SDHI2 (PORT 185, 186, 187, 188, 189, 190) */
GPIO_FN_SDHICLK2, GPIO_FN_SDHICMD2, GPIO_FN_SDHID2_0,
GPIO_FN_SDHID2_1, GPIO_FN_SDHID2_2, GPIO_FN_SDHID2_3,
/* SDENC see MSEL4CR 19 */
GPIO_FN_SDENC_CPG,
GPIO_FN_SDENC_DV_CLKI,

357
arch/arm/mach-shmobile/include/mach/sh73a0.h
View file

@ -94,8 +94,7 @@ enum {
GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
/* Table 25-1 (Function 0-7) */
GPIO_FN_VBUS_0,
GPIO_FN_GPI0,
GPIO_FN_GPI0 = 310,
GPIO_FN_GPI1,
GPIO_FN_GPI2,
GPIO_FN_GPI3,
@ -103,15 +102,11 @@ enum {
GPIO_FN_GPI5,
GPIO_FN_GPI6,
GPIO_FN_GPI7,
GPIO_FN_SCIFA7_RXD,
GPIO_FN_SCIFA7_CTS_,
GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
GPIO_FN_GPO5,
GPIO_FN_PORT16_VIO_CKOR,
GPIO_FN_SCIFA0_TXD,
GPIO_FN_SCIFA7_TXD,
GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
GPIO_FN_PORT19_VIO_CKO2,
GPIO_FN_GPO0,
GPIO_FN_GPO1,
GPIO_FN_GPO2, GPIO_FN_STATUS0,
@ -119,83 +114,44 @@ enum {
GPIO_FN_GPO4, GPIO_FN_STATUS2,
GPIO_FN_VINT,
GPIO_FN_TCKON,
GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
GPIO_FN_XDVFS1,
GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
GPIO_FN_XDVFS2,
GPIO_FN_PORT28_TPU1TO1,
GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
GPIO_FN_SCIFA4_TXD,
GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
GPIO_FN_SCIFA4_RTS_,
GPIO_FN_SCIFA4_CTS_,
GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
GPIO_FN_FSIBOSLD,
GPIO_FN_FSIBISLD,
GPIO_FN_XWUP,
GPIO_FN_VACK,
GPIO_FN_XTAL1L,
GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
GPIO_FN_SCIFA0_RXD,
GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
GPIO_FN_FSIAOMC,
GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
GPIO_FN_PORT49_IROUT,
GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2,
GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3,
GPIO_FN_BBIF2_TXD2,
GPIO_FN_TPU3TO3,
GPIO_FN_TPU3TO2,
GPIO_FN_TPU0TO0,
GPIO_FN_A0, GPIO_FN_BS_,
GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
GPIO_FN_A14, GPIO_FN_KEYOUT5,
GPIO_FN_A15, GPIO_FN_KEYOUT4,
GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
GPIO_FN_A26, GPIO_FN_KEYIN6,
GPIO_FN_KEYIN7,
GPIO_FN_D0_NAF0,
GPIO_FN_D1_NAF1,
GPIO_FN_D2_NAF2,
GPIO_FN_D3_NAF3,
GPIO_FN_D4_NAF4,
GPIO_FN_D5_NAF5,
GPIO_FN_D6_NAF6,
GPIO_FN_D7_NAF7,
GPIO_FN_D8_NAF8,
GPIO_FN_D9_NAF9,
GPIO_FN_D10_NAF10,
GPIO_FN_D11_NAF11,
GPIO_FN_D12_NAF12,
GPIO_FN_D13_NAF13,
GPIO_FN_D14_NAF14,
GPIO_FN_D15_NAF15,
GPIO_FN_CS4_,
GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
GPIO_FN_CS5B_, GPIO_FN_FCE1_,
GPIO_FN_CS6B_, GPIO_FN_DACK0,
GPIO_FN_FCE0_, GPIO_FN_CS6A_,
GPIO_FN_A12, GPIO_FN_TPU4TO2,
GPIO_FN_A13, GPIO_FN_TPU0TO1,
GPIO_FN_A14,
GPIO_FN_A15,
GPIO_FN_A16, GPIO_FN_MSIOF0_SS1,
GPIO_FN_A17, GPIO_FN_MSIOF0_TSYNC,
GPIO_FN_A18, GPIO_FN_MSIOF0_TSCK,
GPIO_FN_A19, GPIO_FN_MSIOF0_TXD,
GPIO_FN_A20, GPIO_FN_MSIOF0_RSCK,
GPIO_FN_A21, GPIO_FN_MSIOF0_RSYNC,
GPIO_FN_A22, GPIO_FN_MSIOF0_MCK0,
GPIO_FN_A23, GPIO_FN_MSIOF0_MCK1,
GPIO_FN_A24, GPIO_FN_MSIOF0_RXD,
GPIO_FN_A25, GPIO_FN_MSIOF0_SS2,
GPIO_FN_A26,
GPIO_FN_FCE1_,
GPIO_FN_DACK0,
GPIO_FN_FCE0_,
GPIO_FN_WAIT_, GPIO_FN_DREQ0,
GPIO_FN_RD__FSC,
GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
GPIO_FN_WE1_,
GPIO_FN_FRB,
GPIO_FN_CKO,
GPIO_FN_NBRSTOUT_,
@ -204,145 +160,118 @@ enum {
GPIO_FN_BBIF2_RXD,
GPIO_FN_BBIF2_SYNC,
GPIO_FN_BBIF2_SCK,
GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
GPIO_FN_SCIFA3_TXD,
GPIO_FN_MFG3_IN2,
GPIO_FN_MFG3_IN1,
GPIO_FN_BBIF1_SS2, GPIO_FN_MFG3_OUT1,
GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
GPIO_FN_PORT115_I2C_SCL3,
GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
GPIO_FN_PORT116_I2C_SDA3,
GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK,
GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC,
GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
GPIO_FN_HSI_TX_FLAG,
GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
GPIO_FN_LCD2D0,
GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD,
GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
GPIO_FN_LCD2D6,
GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
GPIO_FN_LCD2D7,
GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
GPIO_FN_LCD2D2,
GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
GPIO_FN_LCD2D4,
GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
GPIO_FN_VIO_HD,
GPIO_FN_VIO2_HD,
GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD,
GPIO_FN_VIO_D1, GPIO_FN_PORT131_MSIOF2_SS1,
GPIO_FN_VIO_D2, GPIO_FN_PORT132_MSIOF2_SS2,
GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC,
GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD,
GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK,
GPIO_FN_VIO_D6,
GPIO_FN_VIO_D7,
GPIO_FN_VIO_D8, GPIO_FN_VIO2_D0,
GPIO_FN_VIO_D9, GPIO_FN_VIO2_D1,
GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2,
GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3,
GPIO_FN_VIO_D12, GPIO_FN_VIO2_D4,
GPIO_FN_VIO_D13,
GPIO_FN_VIO2_D5,
GPIO_FN_VIO_D14, GPIO_FN_VIO2_D6,
GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3,
GPIO_FN_VIO2_D7,
GPIO_FN_VIO_CLK,
GPIO_FN_VIO2_CLK,
GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD,
GPIO_FN_VIO_CKO,
GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
GPIO_FN_PORT149_KEYOUT9,
GPIO_FN_A27, GPIO_FN_MFG0_IN1,
GPIO_FN_MFG0_IN2,
GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
GPIO_FN_MSIOF2_MCK0,
GPIO_FN_MSIOF2_MCK1,
GPIO_FN_PORT156_MSIOF2_SS2,
GPIO_FN_PORT157_MSIOF2_RXD,
GPIO_FN_DINT_, GPIO_FN_TS_SCK3,
GPIO_FN_NMI,
GPIO_FN_TPU3TO0,
GPIO_FN_LCDD0,
GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
GPIO_FN_BBIF2_TSYNC1,
GPIO_FN_BBIF2_TSCK1,
GPIO_FN_BBIF2_TXD1,
GPIO_FN_MFG2_OUT2,
GPIO_FN_TPU2TO1,
GPIO_FN_LCDD6,
GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
GPIO_FN_LCDD8, GPIO_FN_D16,
GPIO_FN_LCDD9, GPIO_FN_D17,
GPIO_FN_LCDD10, GPIO_FN_D18,
GPIO_FN_LCDD11, GPIO_FN_D19,
GPIO_FN_LCDD12, GPIO_FN_D20,
GPIO_FN_LCDD13, GPIO_FN_D21,
GPIO_FN_LCDD14, GPIO_FN_D22,
GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
GPIO_FN_LCDD17, GPIO_FN_D25,
GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
GPIO_FN_D16,
GPIO_FN_D17,
GPIO_FN_D18,
GPIO_FN_D19,
GPIO_FN_D20,
GPIO_FN_D21,
GPIO_FN_D22,
GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
GPIO_FN_D25,
GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
GPIO_FN_DACK2,
GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3,
GPIO_FN_DACK3,
GPIO_FN_PORT218_VIO_CKOR,
GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
GPIO_FN_LCD2DCK_2,
GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
GPIO_FN_DREQ1,
GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
GPIO_FN_PORT221_LCD2HSYN,
GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
GPIO_FN_DACK1, GPIO_FN_OVCN,
GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3,
GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
GPIO_FN_SCIFA1_RXD,
GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
GPIO_FN_LCD2D20,
GPIO_FN_OVCN2,
GPIO_FN_EXTLP, GPIO_FN_PORT226_VIO_CKO2,
GPIO_FN_IDIN,
GPIO_FN_MFG1_IN1,
GPIO_FN_MSIOF1_TXD,
GPIO_FN_MSIOF1_TSYNC,
GPIO_FN_MSIOF1_TSCK,
GPIO_FN_MSIOF1_RXD,
GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2,
GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
GPIO_FN_LCD2D21,
GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
GPIO_FN_SCIFA6_TXD,
GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
GPIO_FN_MSIOF1_MCK0,
GPIO_FN_MSIOF1_MCK1,
GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2,
GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2,
GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
GPIO_FN_TPU4TO0,
GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
GPIO_FN_MFG4_IN2,
GPIO_FN_PORT243_VIO_CKO2,
GPIO_FN_MFG2_IN1,
GPIO_FN_MSIOF2R_RXD,
GPIO_FN_MFG2_IN2,
GPIO_FN_MSIOF2R_TXD,
GPIO_FN_MFG1_OUT1,
GPIO_FN_TPU1TO0,
GPIO_FN_MFG3_OUT2,
GPIO_FN_TPU3TO1,
GPIO_FN_MFG2_OUT1,
GPIO_FN_TPU2TO0,
GPIO_FN_MSIOF2R_TSCK,
GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
GPIO_FN_MSIOF2R_TSYNC,
GPIO_FN_SDHICLK0,
GPIO_FN_SDHICD0,
GPIO_FN_SDHID0_0,
@ -435,54 +364,12 @@ enum {
GPIO_FN_IRQ9_MEM_INT,
GPIO_FN_IRQ9_MCP_INT,
GPIO_FN_A11,
GPIO_FN_KEYOUT8,
GPIO_FN_TPU4TO3,
GPIO_FN_RESETA_N_PU_ON,
GPIO_FN_RESETA_N_PU_OFF,
GPIO_FN_EDBGREQ_PD,
GPIO_FN_EDBGREQ_PU,
/* Functions with pull-ups */
GPIO_FN_KEYIN0_PU,
GPIO_FN_KEYIN1_PU,
GPIO_FN_KEYIN2_PU,
GPIO_FN_KEYIN3_PU,
GPIO_FN_KEYIN4_PU,
GPIO_FN_KEYIN5_PU,
GPIO_FN_KEYIN6_PU,
GPIO_FN_KEYIN7_PU,
GPIO_FN_SDHICD0_PU,
GPIO_FN_SDHID0_0_PU,
GPIO_FN_SDHID0_1_PU,
GPIO_FN_SDHID0_2_PU,
GPIO_FN_SDHID0_3_PU,
GPIO_FN_SDHICMD0_PU,
GPIO_FN_SDHIWP0_PU,
GPIO_FN_SDHID1_0_PU,
GPIO_FN_SDHID1_1_PU,
GPIO_FN_SDHID1_2_PU,
GPIO_FN_SDHID1_3_PU,
GPIO_FN_SDHICMD1_PU,
GPIO_FN_SDHID2_0_PU,
GPIO_FN_SDHID2_1_PU,
GPIO_FN_SDHID2_2_PU,
GPIO_FN_SDHID2_3_PU,
GPIO_FN_SDHICMD2_PU,
GPIO_FN_MMCCMD0_PU,
GPIO_FN_MMCCMD1_PU,
GPIO_FN_MMCD0_0_PU,
GPIO_FN_MMCD0_1_PU,
GPIO_FN_MMCD0_2_PU,
GPIO_FN_MMCD0_3_PU,
GPIO_FN_MMCD0_4_PU,
GPIO_FN_MMCD0_5_PU,
GPIO_FN_MMCD0_6_PU,
GPIO_FN_MMCD0_7_PU,
GPIO_FN_FSIACK_PU,
GPIO_FN_FSIAILR_PU,
GPIO_FN_FSIAIBT_PU,
GPIO_FN_FSIAISLD_PU,
/* end of GPIO */
GPIO_NR,
};

13
arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
View file

@ -8,12 +8,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7203_pfc_resources[] = {
[0] = {
.start = 0xfffe3800,
.end = 0xfffe3a9f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7203", NULL, 0);
return sh_pfc_register("pfc-sh7203", sh7203_pfc_resources,
ARRAY_SIZE(sh7203_pfc_resources));
}
arch_initcall(plat_pinmux_setup);

13
arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
View file

@ -8,12 +8,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7264_pfc_resources[] = {
[0] = {
.start = 0xfffe3800,
.end = 0xfffe393f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7264", NULL, 0);
return sh_pfc_register("pfc-sh7264", sh7264_pfc_resources,
ARRAY_SIZE(sh7264_pfc_resources));
}
arch_initcall(plat_pinmux_setup);

11
arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
View file

@ -13,8 +13,17 @@
#include <linux/kernel.h>
#include <cpu/pfc.h>
static struct resource sh7269_pfc_resources[] = {
[0] = {
.start = 0xfffe3800,
.end = 0xfffe391f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7269", NULL, 0);
return sh_pfc_register("pfc-sh7269", sh7269_pfc_resources,
ARRAY_SIZE(sh7269_pfc_resources));
}
arch_initcall(plat_pinmux_setup);

14
arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
View file

@ -8,13 +8,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7720_pfc_resources[] = {
[0] = {
.start = 0xa4050100,
.end = 0xa405016f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7720", NULL, 0);
return sh_pfc_register("pfc-sh7720", sh7720_pfc_resources,
ARRAY_SIZE(sh7720_pfc_resources));
}
arch_initcall(plat_pinmux_setup);

14
arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
View file

@ -1,10 +1,20 @@
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7722_pfc_resources[] = {
[0] = {
.start = 0xa4050100,
.end = 0xa405018f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7722", NULL, 0);
return sh_pfc_register("pfc-sh7722", sh7722_pfc_resources,
ARRAY_SIZE(sh7722_pfc_resources));
}
arch_initcall(plat_pinmux_setup);

14
arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
View file

@ -8,13 +8,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7723_pfc_resources[] = {
[0] = {
.start = 0xa4050100,
.end = 0xa405016f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7723", NULL, 0);
return sh_pfc_register("pfc-sh7723", sh7723_pfc_resources,
ARRAY_SIZE(sh7723_pfc_resources));
}
arch_initcall(plat_pinmux_setup);

13
arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
View file

@ -13,12 +13,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7724_pfc_resources[] = {
[0] = {
.start = 0xa4050100,
.end = 0xa405016f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7724", NULL, 0);
return sh_pfc_register("pfc-sh7724", sh7724_pfc_resources,
ARRAY_SIZE(sh7724_pfc_resources));
}
arch_initcall(plat_pinmux_setup);

13
arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
View file

@ -13,12 +13,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7757_pfc_resources[] = {
[0] = {
.start = 0xffec0000,
.end = 0xffec008f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7757", NULL, 0);
return sh_pfc_register("pfc-sh7757", sh7757_pfc_resources,
ARRAY_SIZE(sh7757_pfc_resources));
}
arch_initcall(plat_pinmux_setup);

14
arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
View file

@ -8,13 +8,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7785_pfc_resources[] = {
[0] = {
.start = 0xffe70000,
.end = 0xffe7008f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7785", NULL, 0);
return sh_pfc_register("pfc-sh7785", sh7785_pfc_resources,
ARRAY_SIZE(sh7785_pfc_resources));
}
arch_initcall(plat_pinmux_setup);

14
arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
View file

@ -13,13 +13,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7786_pfc_resources[] = {
[0] = {
.start = 0xffcc0000,
.end = 0xffcc008f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7786", NULL, 0);
return sh_pfc_register("pfc-sh7786", sh7786_pfc_resources,
ARRAY_SIZE(sh7786_pfc_resources));
}
arch_initcall(plat_pinmux_setup);

17
arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
View file

@ -7,12 +7,23 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static int __init shx3_pinmux_setup(void)
static struct resource shx3_pfc_resources[] = {
[0] = {
.start = 0xffc70000,
.end = 0xffc7001f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-shx3", NULL, 0);
return sh_pfc_register("pfc-shx3", shx3_pfc_resources,
ARRAY_SIZE(shx3_pfc_resources));
}
arch_initcall(shx3_pinmux_setup);
arch_initcall(plat_pinmux_setup);

1
drivers/pinctrl/sh-pfc/Kconfig
View file

@ -10,6 +10,7 @@ config PINCTRL_SH_PFC
select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
select PINMUX
select PINCONF
select GENERIC_PINCONF
def_bool y
help
This enables pin control drivers for SH and SH Mobile platforms

261
drivers/pinctrl/sh-pfc/core.c
View file

@ -10,7 +10,6 @@
*/
#define DRV_NAME "sh-pfc"
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bitops.h>
#include <linux/err.h>
@ -30,10 +29,8 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
struct resource *res;
int k;
if (pdev->num_resources == 0) {
pfc->num_windows = 0;
return 0;
}
if (pdev->num_resources == 0)
return -EINVAL;
pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
sizeof(*pfc->window), GFP_NOWAIT);
@ -59,11 +56,11 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
unsigned long address)
{
struct sh_pfc_window *window;
int k;
unsigned int i;
/* scan through physical windows and convert address */
for (k = 0; k < pfc->num_windows; k++) {
window = pfc->window + k;
for (i = 0; i < pfc->num_windows; i++) {
window = pfc->window + i;
if (address < window->phys)
continue;
@ -74,11 +71,32 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
return window->virt + (address - window->phys);
}
/* no windows defined, register must be 1:1 mapped virt:phys */
return (void __iomem *)address;
BUG();
}
static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
{
unsigned int offset;
unsigned int i;
if (pfc->info->ranges == NULL)
return pin;
for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
const struct pinmux_range *range = &pfc->info->ranges[i];
if (pin <= range->end)
return pin >= range->begin
? offset + pin - range->begin : -1;
offset += range->end - range->begin + 1;
}
return -EINVAL;
}
static int sh_pfc_enum_in_range(pinmux_enum_t enum_id,
const struct pinmux_range *r)
{
if (enum_id < r->begin)
return 0;
@ -89,8 +107,8 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
return 1;
}
static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
unsigned long reg_width)
unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
unsigned long reg_width)
{
switch (reg_width) {
case 8:
@ -105,8 +123,8 @@ static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
return 0;
}
static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
unsigned long reg_width, unsigned long data)
void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
unsigned long data)
{
switch (reg_width) {
case 8:
@ -123,39 +141,8 @@ static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
BUG();
}
int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
{
unsigned long pos;
pos = dr->reg_width - (in_pos + 1);
pr_debug("read_bit: addr = %lx, pos = %ld, "
"r_width = %ld\n", dr->reg, pos, dr->reg_width);
return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
}
void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
unsigned long value)
{
unsigned long pos;
pos = dr->reg_width - (in_pos + 1);
pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
"r_width = %ld\n",
dr->reg, !!value, pos, dr->reg_width);
if (value)
set_bit(pos, &dr->reg_shadow);
else
clear_bit(pos, &dr->reg_shadow);
sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
}
static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
struct pinmux_cfg_reg *crp,
const struct pinmux_cfg_reg *crp,
unsigned long in_pos,
void __iomem **mapped_regp,
unsigned long *maskp,
@ -176,24 +163,8 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
}
}
static int sh_pfc_read_config_reg(struct sh_pfc *pfc,
struct pinmux_cfg_reg *crp,
unsigned long field)
{
void __iomem *mapped_reg;
unsigned long mask, pos;
sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
pr_debug("read_reg: addr = %lx, field = %ld, "
"r_width = %ld, f_width = %ld\n",
crp->reg, field, crp->reg_width, crp->field_width);
return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
}
static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
struct pinmux_cfg_reg *crp,
const struct pinmux_cfg_reg *crp,
unsigned long field, unsigned long value)
{
void __iomem *mapped_reg;
@ -201,9 +172,9 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
"r_width = %ld, f_width = %ld\n",
crp->reg, value, field, crp->reg_width, crp->field_width);
dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
"r_width = %ld, f_width = %ld\n",
crp->reg, value, field, crp->reg_width, crp->field_width);
mask = ~(mask << pos);
value = value << pos;
@ -220,83 +191,11 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}
static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
{
struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
struct pinmux_data_reg *data_reg;
int k, n;
if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
return -1;
k = 0;
while (1) {
data_reg = pfc->info->data_regs + k;
if (!data_reg->reg_width)
break;
data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
for (n = 0; n < data_reg->reg_width; n++) {
if (data_reg->enum_ids[n] == gpiop->enum_id) {
gpiop->flags &= ~PINMUX_FLAG_DREG;
gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
gpiop->flags &= ~PINMUX_FLAG_DBIT;
gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
return 0;
}
}
k++;
}
BUG();
return -1;
}
static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
{
struct pinmux_data_reg *drp;
int k;
for (k = pfc->info->first_gpio; k <= pfc->info->last_gpio; k++)
sh_pfc_setup_data_reg(pfc, k);
k = 0;
while (1) {
drp = pfc->info->data_regs + k;
if (!drp->reg_width)
break;
drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
drp->reg_width);
k++;
}
}
int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
struct pinmux_data_reg **drp, int *bitp)
{
struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
int k, n;
if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
return -1;
k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
*drp = pfc->info->data_regs + k;
*bitp = n;
return 0;
}
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
struct pinmux_cfg_reg **crp, int *fieldp,
int *valuep, unsigned long **cntp)
const struct pinmux_cfg_reg **crp, int *fieldp,
int *valuep)
{
struct pinmux_cfg_reg *config_reg;
const struct pinmux_cfg_reg *config_reg;
unsigned long r_width, f_width, curr_width, ncomb;
int k, m, n, pos, bit_pos;
@ -324,7 +223,6 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
*crp = config_reg;
*fieldp = m;
*valuep = n;
*cntp = &config_reg->cnt[m];
return 0;
}
}
@ -334,47 +232,39 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
k++;
}
return -1;
return -EINVAL;
}
int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
pinmux_enum_t *enum_idp)
static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
pinmux_enum_t *enum_idp)
{
pinmux_enum_t enum_id = pfc->info->gpios[gpio].enum_id;
pinmux_enum_t *data = pfc->info->gpio_data;
const pinmux_enum_t *data = pfc->info->gpio_data;
int k;
if (!sh_pfc_enum_in_range(enum_id, &pfc->info->data)) {
if (!sh_pfc_enum_in_range(enum_id, &pfc->info->mark)) {
pr_err("non data/mark enum_id for gpio %d\n", gpio);
return -1;
}
}
if (pos) {
*enum_idp = data[pos + 1];
return pos + 1;
}
for (k = 0; k < pfc->info->gpio_data_size; k++) {
if (data[k] == enum_id) {
if (data[k] == mark) {
*enum_idp = data[k + 1];
return k + 1;
}
}
pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
return -1;
dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
mark);
return -EINVAL;
}
int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
int cfg_mode)
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
{
struct pinmux_cfg_reg *cr = NULL;
const struct pinmux_cfg_reg *cr = NULL;
pinmux_enum_t enum_id;
struct pinmux_range *range;
const struct pinmux_range *range;
int in_range, pos, field, value;
unsigned long *cntp;
int ret;
switch (pinmux_type) {
@ -399,7 +289,7 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
break;
default:
goto out_err;
return -EINVAL;
}
pos = 0;
@ -407,9 +297,9 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
field = 0;
value = 0;
while (1) {
pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
if (pos <= 0)
goto out_err;
pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
if (pos < 0)
return pos;
if (!enum_id)
break;
@ -452,44 +342,22 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
if (!in_range)
continue;
if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
&field, &value, &cntp) != 0)
goto out_err;
ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
if (ret < 0)
return ret;
switch (cfg_mode) {
case GPIO_CFG_DRYRUN:
if (!*cntp ||
(sh_pfc_read_config_reg(pfc, cr, field) != value))
continue;
break;
case GPIO_CFG_REQ:
sh_pfc_write_config_reg(pfc, cr, field, value);
*cntp = *cntp + 1;
break;
case GPIO_CFG_FREE:
*cntp = *cntp - 1;
break;
}
sh_pfc_write_config_reg(pfc, cr, field, value);
}
return 0;
out_err:
return -1;
}
static int sh_pfc_probe(struct platform_device *pdev)
{
struct sh_pfc_soc_info *info;
const struct sh_pfc_soc_info *info;
struct sh_pfc *pfc;
int ret;
/*
* Ensure that the type encoding fits
*/
BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
info = pdev->id_entry->driver_data
? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
if (info == NULL)
@ -509,7 +377,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
spin_lock_init(&pfc->lock);
pinctrl_provide_dummies();
sh_pfc_setup_data_regs(pfc);
/*
* Initialize pinctrl bindings first
@ -529,13 +396,13 @@ static int sh_pfc_probe(struct platform_device *pdev)
* PFC state as it is, given that there are already
* extant users of it that have succeeded by this point.
*/
pr_notice("failed to init GPIO chip, ignoring...\n");
dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
}
#endif
platform_set_drvdata(pdev, pfc);
pr_info("%s support registered\n", info->name);
dev_info(pfc->dev, "%s support registered\n", info->name);
return 0;
}

54
drivers/pinctrl/sh-pfc/core.h
View file

@ -26,13 +26,17 @@ struct sh_pfc_pinctrl;
struct sh_pfc {
struct device *dev;
struct sh_pfc_soc_info *info;
const struct sh_pfc_soc_info *info;
spinlock_t lock;
unsigned int num_windows;
struct sh_pfc_window *window;
unsigned int nr_pins;
struct sh_pfc_chip *gpio;
struct sh_pfc_chip *func;
struct sh_pfc_pinctrl *pinctrl;
};
@ -42,31 +46,29 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc);
int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc);
int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos);
void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
unsigned long value);
int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
struct pinmux_data_reg **drp, int *bitp);
int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
pinmux_enum_t *enum_idp);
int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
int cfg_mode);
unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
unsigned long reg_width);
void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
unsigned long data);
extern struct sh_pfc_soc_info r8a7740_pinmux_info;
extern struct sh_pfc_soc_info r8a7779_pinmux_info;
extern struct sh_pfc_soc_info sh7203_pinmux_info;
extern struct sh_pfc_soc_info sh7264_pinmux_info;
extern struct sh_pfc_soc_info sh7269_pinmux_info;
extern struct sh_pfc_soc_info sh7372_pinmux_info;
extern struct sh_pfc_soc_info sh73a0_pinmux_info;
extern struct sh_pfc_soc_info sh7720_pinmux_info;
extern struct sh_pfc_soc_info sh7722_pinmux_info;
extern struct sh_pfc_soc_info sh7723_pinmux_info;
extern struct sh_pfc_soc_info sh7724_pinmux_info;
extern struct sh_pfc_soc_info sh7734_pinmux_info;
extern struct sh_pfc_soc_info sh7757_pinmux_info;
extern struct sh_pfc_soc_info sh7785_pinmux_info;
extern struct sh_pfc_soc_info sh7786_pinmux_info;
extern struct sh_pfc_soc_info shx3_pinmux_info;
int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
extern const struct sh_pfc_soc_info sh7269_pinmux_info;
extern const struct sh_pfc_soc_info sh7372_pinmux_info;
extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
extern const struct sh_pfc_soc_info sh7720_pinmux_info;
extern const struct sh_pfc_soc_info sh7722_pinmux_info;
extern const struct sh_pfc_soc_info sh7723_pinmux_info;
extern const struct sh_pfc_soc_info sh7724_pinmux_info;
extern const struct sh_pfc_soc_info sh7734_pinmux_info;
extern const struct sh_pfc_soc_info sh7757_pinmux_info;
extern const struct sh_pfc_soc_info sh7785_pinmux_info;
extern const struct sh_pfc_soc_info sh7786_pinmux_info;
extern const struct sh_pfc_soc_info shx3_pinmux_info;
#endif /* __SH_PFC_CORE_H__ */

371
drivers/pinctrl/sh-pfc/gpio.c
View file

@ -9,8 +9,6 @@
* for more details.
*/
#define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/init.h>
@ -21,9 +19,23 @@
#include "core.h"
struct sh_pfc_gpio_data_reg {
const struct pinmux_data_reg *info;
unsigned long shadow;
};
struct sh_pfc_gpio_pin {
u8 dbit;
u8 dreg;
};
struct sh_pfc_chip {
struct sh_pfc *pfc;
struct gpio_chip gpio_chip;
struct sh_pfc *pfc;
struct gpio_chip gpio_chip;
struct sh_pfc_window *mem;
struct sh_pfc_gpio_data_reg *regs;
struct sh_pfc_gpio_pin *pins;
};
static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
@ -36,143 +48,358 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
return gpio_to_pfc_chip(gc)->pfc;
}
static int sh_gpio_request(struct gpio_chip *gc, unsigned offset)
static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio,
struct sh_pfc_gpio_data_reg **reg,
unsigned int *bit)
{
int idx = sh_pfc_get_pin_index(chip->pfc, gpio);
struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
*reg = &chip->regs[gpio_pin->dreg];
*bit = gpio_pin->dbit;
}
static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip,
const struct pinmux_data_reg *dreg)
{
void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt;
return sh_pfc_read_raw_reg(mem, dreg->reg_width);
}
static void gpio_write_data_reg(struct sh_pfc_chip *chip,
const struct pinmux_data_reg *dreg,
unsigned long value)
{
void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt;
sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
}
static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio)
{
struct sh_pfc *pfc = chip->pfc;
struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio];
const struct sh_pfc_pin *pin = &pfc->info->pins[gpio];
const struct pinmux_data_reg *dreg;
unsigned int bit;
unsigned int i;
for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) {
for (bit = 0; bit < dreg->reg_width; bit++) {
if (dreg->enum_ids[bit] == pin->enum_id) {
gpio_pin->dreg = i;
gpio_pin->dbit = bit;
return;
}
}
}
BUG();
}
static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
{
struct sh_pfc *pfc = chip->pfc;
unsigned long addr = pfc->info->data_regs[0].reg;
const struct pinmux_data_reg *dreg;
unsigned int i;
/* Find the window that contain the GPIO registers. */
for (i = 0; i < pfc->num_windows; ++i) {
struct sh_pfc_window *window = &pfc->window[i];
if (addr >= window->phys && addr < window->phys + window->size)
break;
}
if (i == pfc->num_windows)
return -EINVAL;
/* GPIO data registers must be in the first memory resource. */
chip->mem = &pfc->window[i];
/* Count the number of data registers, allocate memory and initialize
* them.
*/
for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
;
chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs),
GFP_KERNEL);
if (chip->regs == NULL)
return -ENOMEM;
for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
chip->regs[i].info = dreg;
chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
}
for (i = 0; i < pfc->info->nr_pins; i++) {
if (pfc->info->pins[i].enum_id == 0)
continue;
gpio_setup_data_reg(chip, i);
}
return 0;
}
/* -----------------------------------------------------------------------------
* Pin GPIOs
*/
static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
int idx = sh_pfc_get_pin_index(pfc, offset);
if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
return -EINVAL;
return pinctrl_request_gpio(offset);
}
static void sh_gpio_free(struct gpio_chip *gc, unsigned offset)
static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
{
pinctrl_free_gpio(offset);
return pinctrl_free_gpio(offset);
}
static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value)
static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
int value)
{
struct pinmux_data_reg *dr = NULL;
int bit = 0;
struct sh_pfc_gpio_data_reg *reg;
unsigned long pos;
unsigned int bit;
if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
BUG();
gpio_get_data_reg(chip, offset, &reg, &bit);
pos = reg->info->reg_width - (bit + 1);
if (value)
set_bit(pos, &reg->shadow);
else
sh_pfc_write_bit(dr, bit, value);
clear_bit(pos, &reg->shadow);
gpio_write_data_reg(chip, reg->info, reg->shadow);
}
static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio)
{
struct pinmux_data_reg *dr = NULL;
int bit = 0;
if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
return -EINVAL;
return sh_pfc_read_bit(dr, bit);
}
static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
{
return pinctrl_gpio_direction_input(offset);
}
static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
int value)
{
sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
return pinctrl_gpio_direction_output(offset);
}
static int sh_gpio_get(struct gpio_chip *gc, unsigned offset)
static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
{
return sh_gpio_get_value(gpio_to_pfc(gc), offset);
struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc);
struct sh_pfc_gpio_data_reg *reg;
unsigned long pos;
unsigned int bit;
gpio_get_data_reg(chip, offset, &reg, &bit);
pos = reg->info->reg_width - (bit + 1);
return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
}
static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
{
sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
}
static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
pinmux_enum_t enum_id;
pinmux_enum_t *enum_ids;
int i, k, pos;
int i, k;
pos = 0;
enum_id = 0;
while (1) {
pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id);
if (pos <= 0 || !enum_id)
break;
for (i = 0; i < pfc->info->gpio_irq_size; i++) {
unsigned short *gpios = pfc->info->gpio_irq[i].gpios;
for (i = 0; i < pfc->info->gpio_irq_size; i++) {
enum_ids = pfc->info->gpio_irq[i].enum_ids;
for (k = 0; enum_ids[k]; k++) {
if (enum_ids[k] == enum_id)
return pfc->info->gpio_irq[i].irq;
}
for (k = 0; gpios[k]; k++) {
if (gpios[k] == offset)
return pfc->info->gpio_irq[i].irq;
}
}
return -ENOSYS;
}
static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip)
static int gpio_pin_setup(struct sh_pfc_chip *chip)
{
struct sh_pfc *pfc = chip->pfc;
struct gpio_chip *gc = &chip->gpio_chip;
int ret;
chip->pins = devm_kzalloc(pfc->dev, pfc->nr_pins * sizeof(*chip->pins),
GFP_KERNEL);
if (chip->pins == NULL)
return -ENOMEM;
ret = gpio_setup_data_regs(chip);
if (ret < 0)
return ret;
gc->request = gpio_pin_request;
gc->free = gpio_pin_free;
gc->direction_input = gpio_pin_direction_input;
gc->get = gpio_pin_get;
gc->direction_output = gpio_pin_direction_output;
gc->set = gpio_pin_set;
gc->to_irq = gpio_pin_to_irq;
gc->label = pfc->info->name;
gc->dev = pfc->dev;
gc->owner = THIS_MODULE;
gc->base = 0;
gc->ngpio = pfc->nr_pins;
return 0;
}
/* -----------------------------------------------------------------------------
* Function GPIOs
*/
static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
{
static bool __print_once;
struct sh_pfc *pfc = gpio_to_pfc(gc);
unsigned int mark = pfc->info->func_gpios[offset].enum_id;
unsigned long flags;
int ret;
if (!__print_once) {
dev_notice(pfc->dev,
"Use of GPIO API for function requests is deprecated."
" Convert to pinctrl\n");
__print_once = true;
}
if (mark == 0)
return -EINVAL;
spin_lock_irqsave(&pfc->lock, flags);
ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
spin_unlock_irqrestore(&pfc->lock, flags);
return ret;
}
static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
{
}
static int gpio_function_setup(struct sh_pfc_chip *chip)
{
struct sh_pfc *pfc = chip->pfc;
struct gpio_chip *gc = &chip->gpio_chip;
gc->request = sh_gpio_request;
gc->free = sh_gpio_free;
gc->direction_input = sh_gpio_direction_input;
gc->get = sh_gpio_get;
gc->direction_output = sh_gpio_direction_output;
gc->set = sh_gpio_set;
gc->to_irq = sh_gpio_to_irq;
WARN_ON(pfc->info->first_gpio != 0); /* needs testing */
gc->request = gpio_function_request;
gc->free = gpio_function_free;
gc->label = pfc->info->name;
gc->owner = THIS_MODULE;
gc->base = pfc->info->first_gpio;
gc->ngpio = (pfc->info->last_gpio - pfc->info->first_gpio) + 1;
gc->base = pfc->nr_pins;
gc->ngpio = pfc->info->nr_func_gpios;
return 0;
}
int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
/* -----------------------------------------------------------------------------
* Register/unregister
*/
static struct sh_pfc_chip *
sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *))
{
struct sh_pfc_chip *chip;
int ret;
chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
if (unlikely(!chip))
return -ENOMEM;
return ERR_PTR(-ENOMEM);
chip->pfc = pfc;
sh_pfc_gpio_setup(chip);
ret = setup(chip);
if (ret < 0)
return ERR_PTR(ret);
ret = gpiochip_add(&chip->gpio_chip);
if (unlikely(ret < 0))
return ret;
return ERR_PTR(ret);
dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
chip->gpio_chip.label, chip->gpio_chip.base,
chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
return chip;
}
int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
{
const struct pinmux_range *ranges;
struct pinmux_range def_range;
struct sh_pfc_chip *chip;
unsigned int nr_ranges;
unsigned int i;
int ret;
/* Register the real GPIOs chip. */
chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
if (IS_ERR(chip))
return PTR_ERR(chip);
pfc->gpio = chip;
pr_info("%s handling gpio %d -> %d\n",
pfc->info->name, pfc->info->first_gpio,
pfc->info->last_gpio);
/* Register the GPIO to pin mappings. */
if (pfc->info->ranges == NULL) {
def_range.begin = 0;
def_range.end = pfc->info->nr_pins - 1;
ranges = &def_range;
nr_ranges = 1;
} else {
ranges = pfc->info->ranges;
nr_ranges = pfc->info->nr_ranges;
}
for (i = 0; i < nr_ranges; ++i) {
const struct pinmux_range *range = &ranges[i];
ret = gpiochip_add_pin_range(&chip->gpio_chip,
dev_name(pfc->dev),
range->begin, range->begin,
range->end - range->begin + 1);
if (ret < 0)
return ret;
}
/* Register the function GPIOs chip. */
chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup);
if (IS_ERR(chip))
return PTR_ERR(chip);
pfc->func = chip;
return 0;
}
int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
{
struct sh_pfc_chip *chip = pfc->gpio;
int err;
int ret;
ret = gpiochip_remove(&chip->gpio_chip);
if (unlikely(ret < 0))
return ret;
ret = gpiochip_remove(&pfc->gpio->gpio_chip);
err = gpiochip_remove(&pfc->func->gpio_chip);
pfc->gpio = NULL;
return 0;
return ret < 0 ? ret : err;
}

690
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
View file

@ -577,7 +577,7 @@ enum {
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
static const pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
/* I/O and Pull U/D */
@ -1654,11 +1654,532 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
};
static struct pinmux_gpio pinmux_gpios[] = {
/* PORT */
static struct sh_pfc_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
};
/* - LCD0 ------------------------------------------------------------------- */
static const unsigned int lcd0_data8_pins[] = {
/* D[0:7] */
58, 57, 56, 55, 54, 53, 52, 51,
};
static const unsigned int lcd0_data8_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
};
static const unsigned int lcd0_data9_pins[] = {
/* D[0:8] */
58, 57, 56, 55, 54, 53, 52, 51,
50,
};
static const unsigned int lcd0_data9_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK,
};
static const unsigned int lcd0_data12_pins[] = {
/* D[0:11] */
58, 57, 56, 55, 54, 53, 52, 51,
50, 49, 48, 47,
};
static const unsigned int lcd0_data12_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
};
static const unsigned int lcd0_data16_pins[] = {
/* D[0:15] */
58, 57, 56, 55, 54, 53, 52, 51,
50, 49, 48, 47, 46, 45, 44, 43,
};
static const unsigned int lcd0_data16_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
};
static const unsigned int lcd0_data18_pins[] = {
/* D[0:17] */
58, 57, 56, 55, 54, 53, 52, 51,
50, 49, 48, 47, 46, 45, 44, 43,
42, 41,
};
static const unsigned int lcd0_data18_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
LCD0_D16_MARK, LCD0_D17_MARK,
};
static const unsigned int lcd0_data24_0_pins[] = {
/* D[0:23] */
58, 57, 56, 55, 54, 53, 52, 51,
50, 49, 48, 47, 46, 45, 44, 43,
42, 41, 40, 4, 3, 2, 0, 1,
};
static const unsigned int lcd0_data24_0_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
LCD0_D23_PORT1_MARK,
};
static const unsigned int lcd0_data24_1_pins[] = {
/* D[0:23] */
58, 57, 56, 55, 54, 53, 52, 51,
50, 49, 48, 47, 46, 45, 44, 43,
42, 41, 163, 162, 161, 158, 160, 159,
};
static const unsigned int lcd0_data24_1_mux[] = {
LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
};
static const unsigned int lcd0_display_pins[] = {
/* DON, VCPWC, VEPWC */
61, 59, 60,
};
static const unsigned int lcd0_display_mux[] = {
LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
};
static const unsigned int lcd0_lclk_0_pins[] = {
/* LCLK */
102,
};
static const unsigned int lcd0_lclk_0_mux[] = {
LCD0_LCLK_PORT102_MARK,
};
static const unsigned int lcd0_lclk_1_pins[] = {
/* LCLK */
165,
};
static const unsigned int lcd0_lclk_1_mux[] = {
LCD0_LCLK_PORT165_MARK,
};
static const unsigned int lcd0_sync_pins[] = {
/* VSYN, HSYN, DCK, DISP */
63, 64, 62, 65,
};
static const unsigned int lcd0_sync_mux[] = {
LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
};
static const unsigned int lcd0_sys_pins[] = {
/* CS, WR, RD, RS */
64, 62, 164, 65,
};
static const unsigned int lcd0_sys_mux[] = {
LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
};
/* - LCD1 ------------------------------------------------------------------- */
static const unsigned int lcd1_data8_pins[] = {
/* D[0:7] */
4, 3, 2, 1, 0, 91, 92, 23,
};
static const unsigned int lcd1_data8_mux[] = {
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
};
static const unsigned int lcd1_data9_pins[] = {
/* D[0:8] */
4, 3, 2, 1, 0, 91, 92, 23,
93,
};
static const unsigned int lcd1_data9_mux[] = {
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
LCD1_D8_MARK,
};
static const unsigned int lcd1_data12_pins[] = {
/* D[0:12] */
4, 3, 2, 1, 0, 91, 92, 23,
93, 94, 21, 201,
};
static const unsigned int lcd1_data12_mux[] = {
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
};
static const unsigned int lcd1_data16_pins[] = {
/* D[0:15] */
4, 3, 2, 1, 0, 91, 92, 23,
93, 94, 21, 201, 200, 199, 196, 195,
};
static const unsigned int lcd1_data16_mux[] = {
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
};
static const unsigned int lcd1_data18_pins[] = {
/* D[0:17] */
4, 3, 2, 1, 0, 91, 92, 23,
93, 94, 21, 201, 200, 199, 196, 195,
194, 193,
};
static const unsigned int lcd1_data18_mux[] = {
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
LCD1_D16_MARK, LCD1_D17_MARK,
};
static const unsigned int lcd1_data24_pins[] = {
/* D[0:23] */
4, 3, 2, 1, 0, 91, 92, 23,
93, 94, 21, 201, 200, 199, 196, 195,
194, 193, 198, 197, 75, 74, 15, 14,
};
static const unsigned int lcd1_data24_mux[] = {
LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
};
static const unsigned int lcd1_display_pins[] = {
/* DON, VCPWC, VEPWC */
100, 5, 6,
};
static const unsigned int lcd1_display_mux[] = {
LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
};
static const unsigned int lcd1_lclk_pins[] = {
/* LCLK */
40,
};
static const unsigned int lcd1_lclk_mux[] = {
LCD1_LCLK_MARK,
};
static const unsigned int lcd1_sync_pins[] = {
/* VSYN, HSYN, DCK, DISP */
98, 97, 99, 12,
};
static const unsigned int lcd1_sync_mux[] = {
LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
};
static const unsigned int lcd1_sys_pins[] = {
/* CS, WR, RD, RS */
97, 99, 13, 12,
};
static const unsigned int lcd1_sys_mux[] = {
LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
};
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc0_data1_0_pins[] = {
/* D[0] */
68,
};
static const unsigned int mmc0_data1_0_mux[] = {
MMC0_D0_PORT68_MARK,
};
static const unsigned int mmc0_data4_0_pins[] = {
/* D[0:3] */
68, 69, 70, 71,
};
static const unsigned int mmc0_data4_0_mux[] = {
MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
};
static const unsigned int mmc0_data8_0_pins[] = {
/* D[0:7] */
68, 69, 70, 71, 72, 73, 74, 75,
};
static const unsigned int mmc0_data8_0_mux[] = {
MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
};
static const unsigned int mmc0_ctrl_0_pins[] = {
/* CMD, CLK */
67, 66,
};
static const unsigned int mmc0_ctrl_0_mux[] = {
MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
};
static const unsigned int mmc0_data1_1_pins[] = {
/* D[0] */
149,
};
static const unsigned int mmc0_data1_1_mux[] = {
MMC1_D0_PORT149_MARK,
};
static const unsigned int mmc0_data4_1_pins[] = {
/* D[0:3] */
149, 148, 147, 146,
};
static const unsigned int mmc0_data4_1_mux[] = {
MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
};
static const unsigned int mmc0_data8_1_pins[] = {
/* D[0:7] */
149, 148, 147, 146, 145, 144, 143, 142,
};
static const unsigned int mmc0_data8_1_mux[] = {
MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
};
static const unsigned int mmc0_ctrl_1_pins[] = {
/* CMD, CLK */
104, 103,
};
static const unsigned int mmc0_ctrl_1_mux[] = {
MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
77,
};
static const unsigned int sdhi0_data1_mux[] = {
SDHI0_D0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
/* D[0:3] */
77, 78, 79, 80,
};
static const unsigned int sdhi0_data4_mux[] = {
SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
/* CMD, CLK */
76, 82,
};
static const unsigned int sdhi0_ctrl_mux[] = {
SDHI0_CMD_MARK, SDHI0_CLK_MARK,
};
static const unsigned int sdhi0_cd_pins[] = {
/* CD */
81,
};
static const unsigned int sdhi0_cd_mux[] = {
SDHI0_CD_MARK,
};
static const unsigned int sdhi0_wp_pins[] = {
/* WP */
83,
};
static const unsigned int sdhi0_wp_mux[] = {
SDHI0_WP_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
68,
};
static const unsigned int sdhi1_data1_mux[] = {
SDHI1_D0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
/* D[0:3] */
68, 69, 70, 71,
};
static const unsigned int sdhi1_data4_mux[] = {
SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
/* CMD, CLK */
67, 66,
};
static const unsigned int sdhi1_ctrl_mux[] = {
SDHI1_CMD_MARK, SDHI1_CLK_MARK,
};
static const unsigned int sdhi1_cd_pins[] = {
/* CD */
72,
};
static const unsigned int sdhi1_cd_mux[] = {
SDHI1_CD_MARK,
};
static const unsigned int sdhi1_wp_pins[] = {
/* WP */
73,
};
static const unsigned int sdhi1_wp_mux[] = {
SDHI1_WP_MARK,
};
/* - SDHI2 ------------------------------------------------------------------ */
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
205,
};
static const unsigned int sdhi2_data1_mux[] = {
SDHI2_D0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
/* D[0:3] */
205, 206, 207, 208,
};
static const unsigned int sdhi2_data4_mux[] = {
SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
/* CMD, CLK */
204, 203,
};
static const unsigned int sdhi2_ctrl_mux[] = {
SDHI2_CMD_MARK, SDHI2_CLK_MARK,
};
static const unsigned int sdhi2_cd_0_pins[] = {
/* CD */
202,
};
static const unsigned int sdhi2_cd_0_mux[] = {
SDHI2_CD_PORT202_MARK,
};
static const unsigned int sdhi2_wp_0_pins[] = {
/* WP */
177,
};
static const unsigned int sdhi2_wp_0_mux[] = {
SDHI2_WP_PORT177_MARK,
};
static const unsigned int sdhi2_cd_1_pins[] = {
/* CD */
24,
};
static const unsigned int sdhi2_cd_1_mux[] = {
SDHI2_CD_PORT24_MARK,
};
static const unsigned int sdhi2_wp_1_pins[] = {
/* WP */
25,
};
static const unsigned int sdhi2_wp_1_mux[] = {
SDHI2_WP_PORT25_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(lcd0_data8),
SH_PFC_PIN_GROUP(lcd0_data9),
SH_PFC_PIN_GROUP(lcd0_data12),
SH_PFC_PIN_GROUP(lcd0_data16),
SH_PFC_PIN_GROUP(lcd0_data18),
SH_PFC_PIN_GROUP(lcd0_data24_0),
SH_PFC_PIN_GROUP(lcd0_data24_1),
SH_PFC_PIN_GROUP(lcd0_display),
SH_PFC_PIN_GROUP(lcd0_lclk_0),
SH_PFC_PIN_GROUP(lcd0_lclk_1),
SH_PFC_PIN_GROUP(lcd0_sync),
SH_PFC_PIN_GROUP(lcd0_sys),
SH_PFC_PIN_GROUP(lcd1_data8),
SH_PFC_PIN_GROUP(lcd1_data9),
SH_PFC_PIN_GROUP(lcd1_data12),
SH_PFC_PIN_GROUP(lcd1_data16),
SH_PFC_PIN_GROUP(lcd1_data18),
SH_PFC_PIN_GROUP(lcd1_data24),
SH_PFC_PIN_GROUP(lcd1_display),
SH_PFC_PIN_GROUP(lcd1_lclk),
SH_PFC_PIN_GROUP(lcd1_sync),
SH_PFC_PIN_GROUP(lcd1_sys),
SH_PFC_PIN_GROUP(mmc0_data1_0),
SH_PFC_PIN_GROUP(mmc0_data4_0),
SH_PFC_PIN_GROUP(mmc0_data8_0),
SH_PFC_PIN_GROUP(mmc0_ctrl_0),
SH_PFC_PIN_GROUP(mmc0_data1_1),
SH_PFC_PIN_GROUP(mmc0_data4_1),
SH_PFC_PIN_GROUP(mmc0_data8_1),
SH_PFC_PIN_GROUP(mmc0_ctrl_1),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi1_cd),
SH_PFC_PIN_GROUP(sdhi1_wp),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
SH_PFC_PIN_GROUP(sdhi2_cd_0),
SH_PFC_PIN_GROUP(sdhi2_wp_0),
SH_PFC_PIN_GROUP(sdhi2_cd_1),
SH_PFC_PIN_GROUP(sdhi2_wp_1),
};
static const char * const lcd0_groups[] = {
"lcd0_data8",
"lcd0_data9",
"lcd0_data12",
"lcd0_data16",
"lcd0_data18",
"lcd0_data24_0",
"lcd0_data24_1",
"lcd0_display",
"lcd0_lclk_0",
"lcd0_lclk_1",
"lcd0_sync",
"lcd0_sys",
};
static const char * const lcd1_groups[] = {
"lcd1_data8",
"lcd1_data9",
"lcd1_data12",
"lcd1_data16",
"lcd1_data18",
"lcd1_data24",
"lcd1_display",
"lcd1_lclk",
"lcd1_sync",
"lcd1_sys",
};
static const char * const mmc0_groups[] = {
"mmc0_data1_0",
"mmc0_data4_0",
"mmc0_data8_0",
"mmc0_ctrl_0",
"mmc0_data1_1",
"mmc0_data4_1",
"mmc0_data8_1",
"mmc0_ctrl_1",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
"sdhi0_ctrl",
"sdhi0_cd",
"sdhi0_wp",
};
static const char * const sdhi1_groups[] = {
"sdhi1_data1",
"sdhi1_data4",
"sdhi1_ctrl",
"sdhi1_cd",
"sdhi1_wp",
};
static const char * const sdhi2_groups[] = {
"sdhi2_data1",
"sdhi2_data4",
"sdhi2_ctrl",
"sdhi2_cd_0",
"sdhi2_wp_0",
"sdhi2_cd_1",
"sdhi2_wp_1",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(lcd0),
SH_PFC_FUNCTION(lcd1),
SH_PFC_FUNCTION(mmc0),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
/* IRQ */
GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
GPIO_FN(IRQ1),
@ -1792,43 +2313,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(SCIFB_RTS_PORT172),
GPIO_FN(SCIFB_CTS_PORT173),
/* LCD0 */
GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
/* LCD1 */
GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
/* RSPI */
GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
@ -1889,26 +2373,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
GPIO_FN(SIM_D_PORT199),
/* SDHI0 */
GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
/* SDHI1 */
GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
/* SDHI2 */
GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
GPIO_FN(SDHI2_WP_PORT25),
GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
GPIO_FN(SDHI2_CD_PORT202),
/* MSIOF2 */
GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
@ -1953,21 +2417,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
GPIO_FN(MEMC_A0),
/* MMC */
GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
GPIO_FN(MMC0_CLK_PORT66),
GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
GPIO_FN(MMC1_CLK_PORT103),
GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
/* MSIOF0 */
GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
@ -2126,7 +2575,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(TRACEAUD_FROM_MEMC),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xe6050000), /* PORT0CR */
PORTCR(1, 0xe6050001), /* PORT1CR */
PORTCR(2, 0xe6050002), /* PORT2CR */
@ -2440,7 +2889,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static struct pinmux_data_reg pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
@ -2544,46 +2993,43 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
static struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */
PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */
PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */
PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */
PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */
PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */
PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */
PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */
PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */
PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */
PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */
PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */
PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */
PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */
PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */
PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */
PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */
PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */
PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */
PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */
PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */
PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */
PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */
PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */
PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */
PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */
PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */
PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */
PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */
PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */
PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */
PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */
static const struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(evt2irq(0x0200), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */
PINMUX_IRQ(evt2irq(0x0220), GPIO_PORT20), /* IRQ1A */
PINMUX_IRQ(evt2irq(0x0240), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */
PINMUX_IRQ(evt2irq(0x0260), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */
PINMUX_IRQ(evt2irq(0x0280), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */
PINMUX_IRQ(evt2irq(0x02A0), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */
PINMUX_IRQ(evt2irq(0x02C0), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */
PINMUX_IRQ(evt2irq(0x02E0), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */
PINMUX_IRQ(evt2irq(0x0300), GPIO_PORT119), /* IRQ8A */
PINMUX_IRQ(evt2irq(0x0320), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */
PINMUX_IRQ(evt2irq(0x0340), GPIO_PORT19), /* IRQ10A */
PINMUX_IRQ(evt2irq(0x0360), GPIO_PORT104), /* IRQ11A */
PINMUX_IRQ(evt2irq(0x0380), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */
PINMUX_IRQ(evt2irq(0x03A0), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */
PINMUX_IRQ(evt2irq(0x03C0), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */
PINMUX_IRQ(evt2irq(0x03E0), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */
PINMUX_IRQ(evt2irq(0x3200), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */
PINMUX_IRQ(evt2irq(0x3220), GPIO_PORT69), /* IRQ17A */
PINMUX_IRQ(evt2irq(0x3240), GPIO_PORT70), /* IRQ18A */
PINMUX_IRQ(evt2irq(0x3260), GPIO_PORT71), /* IRQ19A */
PINMUX_IRQ(evt2irq(0x3280), GPIO_PORT67), /* IRQ20A */
PINMUX_IRQ(evt2irq(0x32A0), GPIO_PORT202), /* IRQ21A */
PINMUX_IRQ(evt2irq(0x32C0), GPIO_PORT95), /* IRQ22A */
PINMUX_IRQ(evt2irq(0x32E0), GPIO_PORT96), /* IRQ23A */
PINMUX_IRQ(evt2irq(0x3300), GPIO_PORT180), /* IRQ24A */
PINMUX_IRQ(evt2irq(0x3320), GPIO_PORT38), /* IRQ25A */
PINMUX_IRQ(evt2irq(0x3340), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */
PINMUX_IRQ(evt2irq(0x3360), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */
PINMUX_IRQ(evt2irq(0x3380), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */
PINMUX_IRQ(evt2irq(0x33A0), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */
PINMUX_IRQ(evt2irq(0x33C0), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */
PINMUX_IRQ(evt2irq(0x33E0), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */
};
struct sh_pfc_soc_info r8a7740_pinmux_info = {
const struct sh_pfc_soc_info r8a7740_pinmux_info = {
.name = "r8a7740_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN,
PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN,
PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
@ -2592,15 +3038,19 @@ struct sh_pfc_soc_info r8a7740_pinmux_info = {
PINMUX_INPUT_PULLDOWN_END },
.output = { PINMUX_OUTPUT_BEGIN,
PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN,
PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN,
PINMUX_FUNCTION_END },
.first_gpio = GPIO_PORT0,
.last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups,
.nr_groups = ARRAY_SIZE(pinmux_groups),
.functions = pinmux_functions,
.nr_functions = ARRAY_SIZE(pinmux_functions),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

1648
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
View file

File diff suppressed because it is too large Load diff

536
drivers/pinctrl/sh-pfc/pfc-sh7203.c
View file

@ -272,7 +272,7 @@ enum {
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
static const pinmux_enum_t pinmux_data[] = {
/* PA */
PINMUX_DATA(PA7_DATA, PA7_IN),
@ -703,7 +703,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11),
};
static struct pinmux_gpio pinmux_gpios[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
@ -815,265 +815,269 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
/* INTC */
PINMUX_GPIO(GPIO_FN_PINT7_PB, PINT7_PB_MARK),
PINMUX_GPIO(GPIO_FN_PINT6_PB, PINT6_PB_MARK),
PINMUX_GPIO(GPIO_FN_PINT5_PB, PINT5_PB_MARK),
PINMUX_GPIO(GPIO_FN_PINT4_PB, PINT4_PB_MARK),
PINMUX_GPIO(GPIO_FN_PINT3_PB, PINT3_PB_MARK),
PINMUX_GPIO(GPIO_FN_PINT2_PB, PINT2_PB_MARK),
PINMUX_GPIO(GPIO_FN_PINT1_PB, PINT1_PB_MARK),
PINMUX_GPIO(GPIO_FN_PINT0_PB, PINT0_PB_MARK),
PINMUX_GPIO(GPIO_FN_PINT7_PD, PINT7_PD_MARK),
PINMUX_GPIO(GPIO_FN_PINT6_PD, PINT6_PD_MARK),
PINMUX_GPIO(GPIO_FN_PINT5_PD, PINT5_PD_MARK),
PINMUX_GPIO(GPIO_FN_PINT4_PD, PINT4_PD_MARK),
PINMUX_GPIO(GPIO_FN_PINT3_PD, PINT3_PD_MARK),
PINMUX_GPIO(GPIO_FN_PINT2_PD, PINT2_PD_MARK),
PINMUX_GPIO(GPIO_FN_PINT1_PD, PINT1_PD_MARK),
PINMUX_GPIO(GPIO_FN_PINT0_PD, PINT0_PD_MARK),
PINMUX_GPIO(GPIO_FN_IRQ7_PB, IRQ7_PB_MARK),
PINMUX_GPIO(GPIO_FN_IRQ6_PB, IRQ6_PB_MARK),
PINMUX_GPIO(GPIO_FN_IRQ5_PB, IRQ5_PB_MARK),
PINMUX_GPIO(GPIO_FN_IRQ4_PB, IRQ4_PB_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3_PB, IRQ3_PB_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2_PB, IRQ2_PB_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1_PB, IRQ1_PB_MARK),
PINMUX_GPIO(GPIO_FN_IRQ0_PB, IRQ0_PB_MARK),
PINMUX_GPIO(GPIO_FN_IRQ7_PD, IRQ7_PD_MARK),
PINMUX_GPIO(GPIO_FN_IRQ6_PD, IRQ6_PD_MARK),
PINMUX_GPIO(GPIO_FN_IRQ5_PD, IRQ5_PD_MARK),
PINMUX_GPIO(GPIO_FN_IRQ4_PD, IRQ4_PD_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3_PD, IRQ3_PD_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2_PD, IRQ2_PD_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1_PD, IRQ1_PD_MARK),
PINMUX_GPIO(GPIO_FN_IRQ0_PD, IRQ0_PD_MARK),
PINMUX_GPIO(GPIO_FN_IRQ7_PE, IRQ7_PE_MARK),
PINMUX_GPIO(GPIO_FN_IRQ6_PE, IRQ6_PE_MARK),
PINMUX_GPIO(GPIO_FN_IRQ5_PE, IRQ5_PE_MARK),
PINMUX_GPIO(GPIO_FN_IRQ4_PE, IRQ4_PE_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK),
PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK),
PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK),
PINMUX_GPIO(GPIO_FN_IRQOUT_REFOUT, IRQOUT_REFOUT_MARK),
PINMUX_GPIO(GPIO_FN_UBCTRG, UBCTRG_MARK),
/* CAN */
PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
PINMUX_GPIO(GPIO_FN_CTX0_CTX1, CTX0_CTX1_MARK),
PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK),
/* IIC3 */
PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
/* DMAC */
PINMUX_GPIO(GPIO_FN_TEND0_PD, TEND0_PD_MARK),
PINMUX_GPIO(GPIO_FN_TEND0_PE, TEND0_PE_MARK),
PINMUX_GPIO(GPIO_FN_DACK0_PD, DACK0_PD_MARK),
PINMUX_GPIO(GPIO_FN_DACK0_PE, DACK0_PE_MARK),
PINMUX_GPIO(GPIO_FN_DREQ0_PD, DREQ0_PD_MARK),
PINMUX_GPIO(GPIO_FN_DREQ0_PE, DREQ0_PE_MARK),
PINMUX_GPIO(GPIO_FN_TEND1_PD, TEND1_PD_MARK),
PINMUX_GPIO(GPIO_FN_TEND1_PE, TEND1_PE_MARK),
PINMUX_GPIO(GPIO_FN_DACK1_PD, DACK1_PD_MARK),
PINMUX_GPIO(GPIO_FN_DACK1_PE, DACK1_PE_MARK),
PINMUX_GPIO(GPIO_FN_DREQ1_PD, DREQ1_PD_MARK),
PINMUX_GPIO(GPIO_FN_DREQ1_PE, DREQ1_PE_MARK),
PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
/* ADC */
PINMUX_GPIO(GPIO_FN_ADTRG_PD, ADTRG_PD_MARK),
PINMUX_GPIO(GPIO_FN_ADTRG_PE, ADTRG_PE_MARK),
/* BSC */
PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
PINMUX_GPIO(GPIO_FN_MRES, MRES_MARK),
PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
PINMUX_GPIO(GPIO_FN_CS6_CE1B, CS6_CE1B_MARK),
PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
PINMUX_GPIO(GPIO_FN_CS5_CE1A, CS5_CE1A_MARK),
PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
PINMUX_GPIO(GPIO_FN_FRAME, FRAME_MARK),
PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
PINMUX_GPIO(GPIO_FN_CASU, CASU_MARK),
PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
PINMUX_GPIO(GPIO_FN_RASU, RASU_MARK),
PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
PINMUX_GPIO(GPIO_FN_CASL, CASL_MARK),
PINMUX_GPIO(GPIO_FN_RASL, RASL_MARK),
PINMUX_GPIO(GPIO_FN_WE3_DQMUU_AH_ICIO_WR, WE3_DQMUU_AH_ICIO_WR_MARK),
PINMUX_GPIO(GPIO_FN_WE2_DQMUL_ICIORD, WE2_DQMUL_ICIORD_MARK),
PINMUX_GPIO(GPIO_FN_WE1_DQMLU_WE, WE1_DQMLU_WE_MARK),
PINMUX_GPIO(GPIO_FN_WE0_DQMLL, WE0_DQMLL_MARK),
PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
PINMUX_GPIO(GPIO_FN_CS7, CS7_MARK),
/* TMU */
PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
PINMUX_GPIO(GPIO_FN_TCLKD_PD, TCLKD_PD_MARK),
PINMUX_GPIO(GPIO_FN_TCLKC_PD, TCLKC_PD_MARK),
PINMUX_GPIO(GPIO_FN_TCLKB_PD, TCLKB_PD_MARK),
PINMUX_GPIO(GPIO_FN_TCLKA_PD, TCLKA_PD_MARK),
PINMUX_GPIO(GPIO_FN_TCLKD_PF, TCLKD_PF_MARK),
PINMUX_GPIO(GPIO_FN_TCLKC_PF, TCLKC_PF_MARK),
PINMUX_GPIO(GPIO_FN_TCLKB_PF, TCLKB_PF_MARK),
PINMUX_GPIO(GPIO_FN_TCLKA_PF, TCLKA_PF_MARK),
/* SSU */
PINMUX_GPIO(GPIO_FN_SCS0_PD, SCS0_PD_MARK),
PINMUX_GPIO(GPIO_FN_SSO0_PD, SSO0_PD_MARK),
PINMUX_GPIO(GPIO_FN_SSI0_PD, SSI0_PD_MARK),
PINMUX_GPIO(GPIO_FN_SSCK0_PD, SSCK0_PD_MARK),
PINMUX_GPIO(GPIO_FN_SCS0_PF, SCS0_PF_MARK),
PINMUX_GPIO(GPIO_FN_SSO0_PF, SSO0_PF_MARK),
PINMUX_GPIO(GPIO_FN_SSI0_PF, SSI0_PF_MARK),
PINMUX_GPIO(GPIO_FN_SSCK0_PF, SSCK0_PF_MARK),
PINMUX_GPIO(GPIO_FN_SCS1_PD, SCS1_PD_MARK),
PINMUX_GPIO(GPIO_FN_SSO1_PD, SSO1_PD_MARK),
PINMUX_GPIO(GPIO_FN_SSI1_PD, SSI1_PD_MARK),
PINMUX_GPIO(GPIO_FN_SSCK1_PD, SSCK1_PD_MARK),
PINMUX_GPIO(GPIO_FN_SCS1_PF, SCS1_PF_MARK),
PINMUX_GPIO(GPIO_FN_SSO1_PF, SSO1_PF_MARK),
PINMUX_GPIO(GPIO_FN_SSI1_PF, SSI1_PF_MARK),
PINMUX_GPIO(GPIO_FN_SSCK1_PF, SSCK1_PF_MARK),
/* SCIF */
PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
/* SSI */
PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
PINMUX_GPIO(GPIO_FN_SSIDATA0, SSIDATA0_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
/* FLCTL */
PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK),
PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK),
PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK),
PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK),
PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK),
PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK),
PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK),
PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK),
PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK),
PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK),
PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK),
PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
/* LCDC */
PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK),
PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK),
PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK),
PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK),
PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
/* INTC */
GPIO_FN(PINT7_PB),
GPIO_FN(PINT6_PB),
GPIO_FN(PINT5_PB),
GPIO_FN(PINT4_PB),
GPIO_FN(PINT3_PB),
GPIO_FN(PINT2_PB),
GPIO_FN(PINT1_PB),
GPIO_FN(PINT0_PB),
GPIO_FN(PINT7_PD),
GPIO_FN(PINT6_PD),
GPIO_FN(PINT5_PD),
GPIO_FN(PINT4_PD),
GPIO_FN(PINT3_PD),
GPIO_FN(PINT2_PD),
GPIO_FN(PINT1_PD),
GPIO_FN(PINT0_PD),
GPIO_FN(IRQ7_PB),
GPIO_FN(IRQ6_PB),
GPIO_FN(IRQ5_PB),
GPIO_FN(IRQ4_PB),
GPIO_FN(IRQ3_PB),
GPIO_FN(IRQ2_PB),
GPIO_FN(IRQ1_PB),
GPIO_FN(IRQ0_PB),
GPIO_FN(IRQ7_PD),
GPIO_FN(IRQ6_PD),
GPIO_FN(IRQ5_PD),
GPIO_FN(IRQ4_PD),
GPIO_FN(IRQ3_PD),
GPIO_FN(IRQ2_PD),
GPIO_FN(IRQ1_PD),
GPIO_FN(IRQ0_PD),
GPIO_FN(IRQ7_PE),
GPIO_FN(IRQ6_PE),
GPIO_FN(IRQ5_PE),
GPIO_FN(IRQ4_PE),
GPIO_FN(IRQ3_PE),
GPIO_FN(IRQ2_PE),
GPIO_FN(IRQ1_PE),
GPIO_FN(IRQ0_PE),
GPIO_FN(WDTOVF),
GPIO_FN(IRQOUT),
GPIO_FN(REFOUT),
GPIO_FN(IRQOUT_REFOUT),
GPIO_FN(UBCTRG),
/* CAN */
GPIO_FN(CTX1),
GPIO_FN(CRX1),
GPIO_FN(CTX0),
GPIO_FN(CTX0_CTX1),
GPIO_FN(CRX0),
GPIO_FN(CRX0_CRX1),
/* IIC3 */
GPIO_FN(SDA3),
GPIO_FN(SCL3),
GPIO_FN(SDA2),
GPIO_FN(SCL2),
GPIO_FN(SDA1),
GPIO_FN(SCL1),
GPIO_FN(SDA0),
GPIO_FN(SCL0),
/* DMAC */
GPIO_FN(TEND0_PD),
GPIO_FN(TEND0_PE),
GPIO_FN(DACK0_PD),
GPIO_FN(DACK0_PE),
GPIO_FN(DREQ0_PD),
GPIO_FN(DREQ0_PE),
GPIO_FN(TEND1_PD),
GPIO_FN(TEND1_PE),
GPIO_FN(DACK1_PD),
GPIO_FN(DACK1_PE),
GPIO_FN(DREQ1_PD),
GPIO_FN(DREQ1_PE),
GPIO_FN(DACK2),
GPIO_FN(DREQ2),
GPIO_FN(DACK3),
GPIO_FN(DREQ3),
/* ADC */
GPIO_FN(ADTRG_PD),
GPIO_FN(ADTRG_PE),
/* BSC */
GPIO_FN(D31),
GPIO_FN(D30),
GPIO_FN(D29),
GPIO_FN(D28),
GPIO_FN(D27),
GPIO_FN(D26),
GPIO_FN(D25),
GPIO_FN(D24),
GPIO_FN(D23),
GPIO_FN(D22),
GPIO_FN(D21),
GPIO_FN(D20),
GPIO_FN(D19),
GPIO_FN(D18),
GPIO_FN(D17),
GPIO_FN(D16),
GPIO_FN(A25),
GPIO_FN(A24),
GPIO_FN(A23),
GPIO_FN(A22),
GPIO_FN(A21),
GPIO_FN(CS4),
GPIO_FN(MRES),
GPIO_FN(BS),
GPIO_FN(IOIS16),
GPIO_FN(CS1),
GPIO_FN(CS6_CE1B),
GPIO_FN(CE2B),
GPIO_FN(CS5_CE1A),
GPIO_FN(CE2A),
GPIO_FN(FRAME),
GPIO_FN(WAIT),
GPIO_FN(RDWR),
GPIO_FN(CKE),
GPIO_FN(CASU),
GPIO_FN(BREQ),
GPIO_FN(RASU),
GPIO_FN(BACK),
GPIO_FN(CASL),
GPIO_FN(RASL),
GPIO_FN(WE3_DQMUU_AH_ICIO_WR),
GPIO_FN(WE2_DQMUL_ICIORD),
GPIO_FN(WE1_DQMLU_WE),
GPIO_FN(WE0_DQMLL),
GPIO_FN(CS3),
GPIO_FN(CS2),
GPIO_FN(A1),
GPIO_FN(A0),
GPIO_FN(CS7),
/* TMU */
GPIO_FN(TIOC4D),
GPIO_FN(TIOC4C),
GPIO_FN(TIOC4B),
GPIO_FN(TIOC4A),
GPIO_FN(TIOC3D),
GPIO_FN(TIOC3C),
GPIO_FN(TIOC3B),
GPIO_FN(TIOC3A),
GPIO_FN(TIOC2B),
GPIO_FN(TIOC1B),
GPIO_FN(TIOC2A),
GPIO_FN(TIOC1A),
GPIO_FN(TIOC0D),
GPIO_FN(TIOC0C),
GPIO_FN(TIOC0B),
GPIO_FN(TIOC0A),
GPIO_FN(TCLKD_PD),
GPIO_FN(TCLKC_PD),
GPIO_FN(TCLKB_PD),
GPIO_FN(TCLKA_PD),
GPIO_FN(TCLKD_PF),
GPIO_FN(TCLKC_PF),
GPIO_FN(TCLKB_PF),
GPIO_FN(TCLKA_PF),
/* SSU */
GPIO_FN(SCS0_PD),
GPIO_FN(SSO0_PD),
GPIO_FN(SSI0_PD),
GPIO_FN(SSCK0_PD),
GPIO_FN(SCS0_PF),
GPIO_FN(SSO0_PF),
GPIO_FN(SSI0_PF),
GPIO_FN(SSCK0_PF),
GPIO_FN(SCS1_PD),
GPIO_FN(SSO1_PD),
GPIO_FN(SSI1_PD),
GPIO_FN(SSCK1_PD),
GPIO_FN(SCS1_PF),
GPIO_FN(SSO1_PF),
GPIO_FN(SSI1_PF),
GPIO_FN(SSCK1_PF),
/* SCIF */
GPIO_FN(TXD0),
GPIO_FN(RXD0),
GPIO_FN(SCK0),
GPIO_FN(TXD1),
GPIO_FN(RXD1),
GPIO_FN(SCK1),
GPIO_FN(TXD2),
GPIO_FN(RXD2),
GPIO_FN(SCK2),
GPIO_FN(RTS3),
GPIO_FN(CTS3),
GPIO_FN(TXD3),
GPIO_FN(RXD3),
GPIO_FN(SCK3),
/* SSI */
GPIO_FN(AUDIO_CLK),
GPIO_FN(SSIDATA3),
GPIO_FN(SSIWS3),
GPIO_FN(SSISCK3),
GPIO_FN(SSIDATA2),
GPIO_FN(SSIWS2),
GPIO_FN(SSISCK2),
GPIO_FN(SSIDATA1),
GPIO_FN(SSIWS1),
GPIO_FN(SSISCK1),
GPIO_FN(SSIDATA0),
GPIO_FN(SSIWS0),
GPIO_FN(SSISCK0),
/* FLCTL */
GPIO_FN(FCE),
GPIO_FN(FRB),
GPIO_FN(NAF7),
GPIO_FN(NAF6),
GPIO_FN(NAF5),
GPIO_FN(NAF4),
GPIO_FN(NAF3),
GPIO_FN(NAF2),
GPIO_FN(NAF1),
GPIO_FN(NAF0),
GPIO_FN(FSC),
GPIO_FN(FOE),
GPIO_FN(FCDE),
GPIO_FN(FWE),
/* LCDC */
GPIO_FN(LCD_VEPWC),
GPIO_FN(LCD_VCPWC),
GPIO_FN(LCD_CLK),
GPIO_FN(LCD_FLM),
GPIO_FN(LCD_M_DISP),
GPIO_FN(LCD_CL2),
GPIO_FN(LCD_CL1),
GPIO_FN(LCD_DON),
GPIO_FN(LCD_DATA15),
GPIO_FN(LCD_DATA14),
GPIO_FN(LCD_DATA13),
GPIO_FN(LCD_DATA12),
GPIO_FN(LCD_DATA11),
GPIO_FN(LCD_DATA10),
GPIO_FN(LCD_DATA9),
GPIO_FN(LCD_DATA8),
GPIO_FN(LCD_DATA7),
GPIO_FN(LCD_DATA6),
GPIO_FN(LCD_DATA5),
GPIO_FN(LCD_DATA4),
GPIO_FN(LCD_DATA3),
GPIO_FN(LCD_DATA2),
GPIO_FN(LCD_DATA1),
GPIO_FN(LCD_DATA0),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) {
0, 0,
0, 0,
@ -1525,7 +1529,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
static struct pinmux_data_reg pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) {
0, 0, 0, 0,
0, 0, 0, 0,
@ -1571,19 +1575,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
struct sh_pfc_soc_info sh7203_pinmux_info = {
const struct sh_pfc_soc_info sh7203_pinmux_info = {
.name = "sh7203_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PA7,
.last_gpio = GPIO_FN_LCD_DATA0,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

520
drivers/pinctrl/sh-pfc/pfc-sh7264.c
View file

@ -604,7 +604,7 @@ enum {
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
static const pinmux_enum_t pinmux_data[] = {
/* Port A */
PINMUX_DATA(PA3_DATA, PA3_IN),
@ -1072,7 +1072,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SD_D2_MARK, PK0MD_10),
};
static struct pinmux_gpio pinmux_gpios[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* Port A */
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
@ -1216,257 +1216,261 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PK2, PK2_DATA),
PINMUX_GPIO(GPIO_PK1, PK1_DATA),
PINMUX_GPIO(GPIO_PK0, PK0_DATA),
/* INTC */
PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ7_PC, IRQ7_PC_MARK),
PINMUX_GPIO(GPIO_FN_IRQ6_PC, IRQ6_PC_MARK),
PINMUX_GPIO(GPIO_FN_IRQ5_PC, IRQ5_PC_MARK),
PINMUX_GPIO(GPIO_FN_IRQ4_PC, IRQ4_PC_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK),
PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK),
PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK),
/* WDT */
PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
/* CAN */
PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK),
/* DMAC */
PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
/* ADC */
PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
/* BSCh */
PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
PINMUX_GPIO(GPIO_FN_CS6CE1B, CS6CE1B_MARK),
PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK),
PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
PINMUX_GPIO(GPIO_FN_ICIOWRAH, ICIOWRAH_MARK),
PINMUX_GPIO(GPIO_FN_ICIORD, ICIORD_MARK),
PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK),
PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK),
PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
/* TMU */
PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK),
PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK),
PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK),
PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK),
/* SCIF */
PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK),
PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK),
PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK),
PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK),
PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK),
PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK),
PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK),
PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK),
/* RSPI */
PINMUX_GPIO(GPIO_FN_RSPCK0, RSPCK0_MARK),
PINMUX_GPIO(GPIO_FN_MOSI0, MOSI0_MARK),
PINMUX_GPIO(GPIO_FN_MISO0_PF12, MISO0_PF12_MARK),
PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK),
PINMUX_GPIO(GPIO_FN_SSL00, SSL00_MARK),
PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK),
PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK),
PINMUX_GPIO(GPIO_FN_MISO1_PG19, MISO1_PG19_MARK),
PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK),
/* IIC3 */
PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
/* SSI */
PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK),
PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
/* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK),
PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK),
/* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK),
PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK),
/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
/* VDC3 */
PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK),
PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK),
PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK),
PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
/* INTC */
GPIO_FN(PINT7_PG),
GPIO_FN(PINT6_PG),
GPIO_FN(PINT5_PG),
GPIO_FN(PINT4_PG),
GPIO_FN(PINT3_PG),
GPIO_FN(PINT2_PG),
GPIO_FN(PINT1_PG),
GPIO_FN(IRQ7_PC),
GPIO_FN(IRQ6_PC),
GPIO_FN(IRQ5_PC),
GPIO_FN(IRQ4_PC),
GPIO_FN(IRQ3_PG),
GPIO_FN(IRQ2_PG),
GPIO_FN(IRQ1_PJ),
GPIO_FN(IRQ0_PJ),
GPIO_FN(IRQ3_PE),
GPIO_FN(IRQ2_PE),
GPIO_FN(IRQ1_PE),
GPIO_FN(IRQ0_PE),
/* WDT */
GPIO_FN(WDTOVF),
/* CAN */
GPIO_FN(CTX1),
GPIO_FN(CRX1),
GPIO_FN(CTX0),
GPIO_FN(CRX0),
GPIO_FN(CRX0_CRX1),
/* DMAC */
GPIO_FN(TEND0),
GPIO_FN(DACK0),
GPIO_FN(DREQ0),
GPIO_FN(TEND1),
GPIO_FN(DACK1),
GPIO_FN(DREQ1),
/* ADC */
GPIO_FN(ADTRG),
/* BSCh */
GPIO_FN(A25),
GPIO_FN(A24),
GPIO_FN(A23),
GPIO_FN(A22),
GPIO_FN(A21),
GPIO_FN(A20),
GPIO_FN(A19),
GPIO_FN(A18),
GPIO_FN(A17),
GPIO_FN(A16),
GPIO_FN(A15),
GPIO_FN(A14),
GPIO_FN(A13),
GPIO_FN(A12),
GPIO_FN(A11),
GPIO_FN(A10),
GPIO_FN(A9),
GPIO_FN(A8),
GPIO_FN(A7),
GPIO_FN(A6),
GPIO_FN(A5),
GPIO_FN(A4),
GPIO_FN(A3),
GPIO_FN(A2),
GPIO_FN(A1),
GPIO_FN(A0),
GPIO_FN(D15),
GPIO_FN(D14),
GPIO_FN(D13),
GPIO_FN(D12),
GPIO_FN(D11),
GPIO_FN(D10),
GPIO_FN(D9),
GPIO_FN(D8),
GPIO_FN(D7),
GPIO_FN(D6),
GPIO_FN(D5),
GPIO_FN(D4),
GPIO_FN(D3),
GPIO_FN(D2),
GPIO_FN(D1),
GPIO_FN(D0),
GPIO_FN(BS),
GPIO_FN(CS4),
GPIO_FN(CS3),
GPIO_FN(CS2),
GPIO_FN(CS1),
GPIO_FN(CS0),
GPIO_FN(CS6CE1B),
GPIO_FN(CS5CE1A),
GPIO_FN(CE2A),
GPIO_FN(CE2B),
GPIO_FN(RD),
GPIO_FN(RDWR),
GPIO_FN(ICIOWRAH),
GPIO_FN(ICIORD),
GPIO_FN(WE1DQMUWE),
GPIO_FN(WE0DQML),
GPIO_FN(RAS),
GPIO_FN(CAS),
GPIO_FN(CKE),
GPIO_FN(WAIT),
GPIO_FN(BREQ),
GPIO_FN(BACK),
GPIO_FN(IOIS16),
/* TMU */
GPIO_FN(TIOC4D),
GPIO_FN(TIOC4C),
GPIO_FN(TIOC4B),
GPIO_FN(TIOC4A),
GPIO_FN(TIOC3D),
GPIO_FN(TIOC3C),
GPIO_FN(TIOC3B),
GPIO_FN(TIOC3A),
GPIO_FN(TIOC2B),
GPIO_FN(TIOC1B),
GPIO_FN(TIOC2A),
GPIO_FN(TIOC1A),
GPIO_FN(TIOC0D),
GPIO_FN(TIOC0C),
GPIO_FN(TIOC0B),
GPIO_FN(TIOC0A),
GPIO_FN(TCLKD),
GPIO_FN(TCLKC),
GPIO_FN(TCLKB),
GPIO_FN(TCLKA),
/* SCIF */
GPIO_FN(TXD0),
GPIO_FN(RXD0),
GPIO_FN(SCK0),
GPIO_FN(TXD1),
GPIO_FN(RXD1),
GPIO_FN(SCK1),
GPIO_FN(TXD2),
GPIO_FN(RXD2),
GPIO_FN(SCK2),
GPIO_FN(RTS3),
GPIO_FN(CTS3),
GPIO_FN(TXD3),
GPIO_FN(RXD3),
GPIO_FN(SCK3),
GPIO_FN(TXD4),
GPIO_FN(RXD4),
GPIO_FN(TXD5),
GPIO_FN(RXD5),
GPIO_FN(TXD6),
GPIO_FN(RXD6),
GPIO_FN(TXD7),
GPIO_FN(RXD7),
GPIO_FN(RTS1),
GPIO_FN(CTS1),
/* RSPI */
GPIO_FN(RSPCK0),
GPIO_FN(MOSI0),
GPIO_FN(MISO0_PF12),
GPIO_FN(MISO1),
GPIO_FN(SSL00),
GPIO_FN(RSPCK1),
GPIO_FN(MOSI1),
GPIO_FN(MISO1_PG19),
GPIO_FN(SSL10),
/* IIC3 */
GPIO_FN(SCL0),
GPIO_FN(SCL1),
GPIO_FN(SCL2),
GPIO_FN(SDA0),
GPIO_FN(SDA1),
GPIO_FN(SDA2),
/* SSI */
GPIO_FN(SSISCK0),
GPIO_FN(SSIWS0),
GPIO_FN(SSITXD0),
GPIO_FN(SSIRXD0),
GPIO_FN(SSIWS1),
GPIO_FN(SSIWS2),
GPIO_FN(SSIWS3),
GPIO_FN(SSISCK1),
GPIO_FN(SSISCK2),
GPIO_FN(SSISCK3),
GPIO_FN(SSIDATA1),
GPIO_FN(SSIDATA2),
GPIO_FN(SSIDATA3),
GPIO_FN(AUDIO_CLK),
/* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
GPIO_FN(SIOFTXD),
GPIO_FN(SIOFRXD),
GPIO_FN(SIOFSYNC),
GPIO_FN(SIOFSCK),
/* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
GPIO_FN(SPDIF_IN),
GPIO_FN(SPDIF_OUT),
/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
GPIO_FN(FCE),
GPIO_FN(FRB),
/* VDC3 */
GPIO_FN(DV_CLK),
GPIO_FN(DV_VSYNC),
GPIO_FN(DV_HSYNC),
GPIO_FN(DV_DATA7),
GPIO_FN(DV_DATA6),
GPIO_FN(DV_DATA5),
GPIO_FN(DV_DATA4),
GPIO_FN(DV_DATA3),
GPIO_FN(DV_DATA2),
GPIO_FN(DV_DATA1),
GPIO_FN(DV_DATA0),
GPIO_FN(LCD_CLK),
GPIO_FN(LCD_EXTCLK),
GPIO_FN(LCD_VSYNC),
GPIO_FN(LCD_HSYNC),
GPIO_FN(LCD_DE),
GPIO_FN(LCD_DATA15),
GPIO_FN(LCD_DATA14),
GPIO_FN(LCD_DATA13),
GPIO_FN(LCD_DATA12),
GPIO_FN(LCD_DATA11),
GPIO_FN(LCD_DATA10),
GPIO_FN(LCD_DATA9),
GPIO_FN(LCD_DATA8),
GPIO_FN(LCD_DATA7),
GPIO_FN(LCD_DATA6),
GPIO_FN(LCD_DATA5),
GPIO_FN(LCD_DATA4),
GPIO_FN(LCD_DATA3),
GPIO_FN(LCD_DATA2),
GPIO_FN(LCD_DATA1),
GPIO_FN(LCD_DATA0),
GPIO_FN(LCD_M_DISP),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@ -2032,7 +2036,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
static struct pinmux_data_reg pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) {
0, 0, 0, 0, 0, 0, 0, PA3_DATA,
0, 0, 0, 0, 0, 0, 0, PA2_DATA }
@ -2110,19 +2114,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ }
};
struct sh_pfc_soc_info sh7264_pinmux_info = {
const struct sh_pfc_soc_info sh7264_pinmux_info = {
.name = "sh7264_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PA3,
.last_gpio = GPIO_FN_LCD_M_DISP,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

684
drivers/pinctrl/sh-pfc/pfc-sh7269.c
View file

@ -781,7 +781,7 @@ enum {
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
static const pinmux_enum_t pinmux_data[] = {
/* Port A */
PINMUX_DATA(PA1_DATA, PA1_IN),
@ -1452,7 +1452,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(PWM1A_MARK, PJ0MD_100),
};
static struct pinmux_gpio pinmux_gpios[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* Port A */
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
@ -1613,339 +1613,343 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
/* INTC */
PINMUX_GPIO(GPIO_FN_IRQ7_PG, IRQ7_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ6_PG, IRQ6_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ5_PG, IRQ5_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ4_PG, IRQ4_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1_PG, IRQ1_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ0_PG, IRQ0_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ7_PF, IRQ7_PF_MARK),
PINMUX_GPIO(GPIO_FN_IRQ6_PF, IRQ6_PF_MARK),
PINMUX_GPIO(GPIO_FN_IRQ5_PF, IRQ5_PF_MARK),
PINMUX_GPIO(GPIO_FN_IRQ4_PF, IRQ4_PF_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3_PJ, IRQ3_PJ_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2_PJ, IRQ2_PJ_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK),
PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1_PC, IRQ1_PC_MARK),
PINMUX_GPIO(GPIO_FN_IRQ0_PC, IRQ0_PC_MARK),
PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT0_PG, PINT0_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT7_PH, PINT7_PH_MARK),
PINMUX_GPIO(GPIO_FN_PINT6_PH, PINT6_PH_MARK),
PINMUX_GPIO(GPIO_FN_PINT5_PH, PINT5_PH_MARK),
PINMUX_GPIO(GPIO_FN_PINT4_PH, PINT4_PH_MARK),
PINMUX_GPIO(GPIO_FN_PINT3_PH, PINT3_PH_MARK),
PINMUX_GPIO(GPIO_FN_PINT2_PH, PINT2_PH_MARK),
PINMUX_GPIO(GPIO_FN_PINT1_PH, PINT1_PH_MARK),
PINMUX_GPIO(GPIO_FN_PINT0_PH, PINT0_PH_MARK),
PINMUX_GPIO(GPIO_FN_PINT7_PJ, PINT7_PJ_MARK),
PINMUX_GPIO(GPIO_FN_PINT6_PJ, PINT6_PJ_MARK),
PINMUX_GPIO(GPIO_FN_PINT5_PJ, PINT5_PJ_MARK),
PINMUX_GPIO(GPIO_FN_PINT4_PJ, PINT4_PJ_MARK),
PINMUX_GPIO(GPIO_FN_PINT3_PJ, PINT3_PJ_MARK),
PINMUX_GPIO(GPIO_FN_PINT2_PJ, PINT2_PJ_MARK),
PINMUX_GPIO(GPIO_FN_PINT1_PJ, PINT1_PJ_MARK),
PINMUX_GPIO(GPIO_FN_PINT0_PJ, PINT0_PJ_MARK),
/* WDT */
PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
/* CAN */
PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK),
PINMUX_GPIO(GPIO_FN_CRX0_CRX1_CRX2, CRX0_CRX1_CRX2_MARK),
/* DMAC */
PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
/* ADC */
PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
/* BSCh */
PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK),
PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
PINMUX_GPIO(GPIO_FN_WE3ICIOWRAHDQMUU, WE3ICIOWRAHDQMUU_MARK),
PINMUX_GPIO(GPIO_FN_WE2ICIORDDQMUL, WE2ICIORDDQMUL_MARK),
PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK),
PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK),
PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
/* TMU */
PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK),
PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK),
PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK),
PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK),
/* SCIF */
PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK),
PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK),
PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
PINMUX_GPIO(GPIO_FN_SCK5, SCK5_MARK),
PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK),
PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK),
PINMUX_GPIO(GPIO_FN_RTS5, RTS5_MARK),
PINMUX_GPIO(GPIO_FN_CTS5, CTS5_MARK),
PINMUX_GPIO(GPIO_FN_SCK6, SCK6_MARK),
PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK),
PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK),
PINMUX_GPIO(GPIO_FN_SCK7, SCK7_MARK),
PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK),
PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK),
PINMUX_GPIO(GPIO_FN_RTS7, RTS7_MARK),
PINMUX_GPIO(GPIO_FN_CTS7, CTS7_MARK),
/* RSPI */
PINMUX_GPIO(GPIO_FN_RSPCK0_PJ16, RSPCK0_PJ16_MARK),
PINMUX_GPIO(GPIO_FN_SSL00_PJ17, SSL00_PJ17_MARK),
PINMUX_GPIO(GPIO_FN_MOSI0_PJ18, MOSI0_PJ18_MARK),
PINMUX_GPIO(GPIO_FN_MISO0_PJ19, MISO0_PJ19_MARK),
PINMUX_GPIO(GPIO_FN_RSPCK0_PB17, RSPCK0_PB17_MARK),
PINMUX_GPIO(GPIO_FN_SSL00_PB18, SSL00_PB18_MARK),
PINMUX_GPIO(GPIO_FN_MOSI0_PB19, MOSI0_PB19_MARK),
PINMUX_GPIO(GPIO_FN_MISO0_PB20, MISO0_PB20_MARK),
PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK),
PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK),
PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK),
PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK),
/* IIC3 */
PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
/* SSI */
PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK),
PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
PINMUX_GPIO(GPIO_FN_AUDIO_XOUT, AUDIO_XOUT_MARK),
/* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK),
PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK),
/* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK),
PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK),
/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
/* VDC3 */
PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA23, DV_DATA23_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA22, DV_DATA22_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA21, DV_DATA21_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA20, DV_DATA20_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA19, DV_DATA19_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA18, DV_DATA18_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA17, DV_DATA17_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA16, DV_DATA16_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA15, DV_DATA15_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA14, DV_DATA14_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA13, DV_DATA13_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA12, DV_DATA12_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA11, DV_DATA11_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA10, DV_DATA10_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA9, DV_DATA9_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA8, DV_DATA8_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK),
PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK),
PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK),
PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA23_PG23, LCD_DATA23_PG23_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA22_PG22, LCD_DATA22_PG22_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA21_PG21, LCD_DATA21_PG21_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA20_PG20, LCD_DATA20_PG20_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA19_PG19, LCD_DATA19_PG19_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA18_PG18, LCD_DATA18_PG18_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA17_PG17, LCD_DATA17_PG17_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA16_PG16, LCD_DATA16_PG16_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA15_PG15, LCD_DATA15_PG15_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA14_PG14, LCD_DATA14_PG14_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA13_PG13, LCD_DATA13_PG13_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA12_PG12, LCD_DATA12_PG12_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA11_PG11, LCD_DATA11_PG11_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA10_PG10, LCD_DATA10_PG10_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA9_PG9, LCD_DATA9_PG9_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA8_PG8, LCD_DATA8_PG8_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA7_PG7, LCD_DATA7_PG7_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA6_PG6, LCD_DATA6_PG6_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA5_PG5, LCD_DATA5_PG5_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA4_PG4, LCD_DATA4_PG4_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA3_PG3, LCD_DATA3_PG3_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA2_PG2, LCD_DATA2_PG2_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA1_PG1, LCD_DATA1_PG1_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA0_PG0, LCD_DATA0_PG0_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA23_PJ23, LCD_DATA23_PJ23_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA22_PJ22, LCD_DATA22_PJ22_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA21_PJ21, LCD_DATA21_PJ21_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA20_PJ20, LCD_DATA20_PJ20_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA19_PJ19, LCD_DATA19_PJ19_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA18_PJ18, LCD_DATA18_PJ18_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA17_PJ17, LCD_DATA17_PJ17_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA16_PJ16, LCD_DATA16_PJ16_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA15_PJ15, LCD_DATA15_PJ15_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA14_PJ14, LCD_DATA14_PJ14_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA13_PJ13, LCD_DATA13_PJ13_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA12_PJ12, LCD_DATA12_PJ12_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA11_PJ11, LCD_DATA11_PJ11_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA10_PJ10, LCD_DATA10_PJ10_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA9_PJ9, LCD_DATA9_PJ9_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA8_PJ8, LCD_DATA8_PJ8_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA7_PJ7, LCD_DATA7_PJ7_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA6_PJ6, LCD_DATA6_PJ6_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA5_PJ5, LCD_DATA5_PJ5_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA4_PJ4, LCD_DATA4_PJ4_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA3_PJ3, LCD_DATA3_PJ3_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA2_PJ2, LCD_DATA2_PJ2_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA1_PJ1, LCD_DATA1_PJ1_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA0_PJ0, LCD_DATA0_PJ0_MARK),
PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
/* INTC */
GPIO_FN(IRQ7_PG),
GPIO_FN(IRQ6_PG),
GPIO_FN(IRQ5_PG),
GPIO_FN(IRQ4_PG),
GPIO_FN(IRQ3_PG),
GPIO_FN(IRQ2_PG),
GPIO_FN(IRQ1_PG),
GPIO_FN(IRQ0_PG),
GPIO_FN(IRQ7_PF),
GPIO_FN(IRQ6_PF),
GPIO_FN(IRQ5_PF),
GPIO_FN(IRQ4_PF),
GPIO_FN(IRQ3_PJ),
GPIO_FN(IRQ2_PJ),
GPIO_FN(IRQ1_PJ),
GPIO_FN(IRQ0_PJ),
GPIO_FN(IRQ1_PC),
GPIO_FN(IRQ0_PC),
GPIO_FN(PINT7_PG),
GPIO_FN(PINT6_PG),
GPIO_FN(PINT5_PG),
GPIO_FN(PINT4_PG),
GPIO_FN(PINT3_PG),
GPIO_FN(PINT2_PG),
GPIO_FN(PINT1_PG),
GPIO_FN(PINT0_PG),
GPIO_FN(PINT7_PH),
GPIO_FN(PINT6_PH),
GPIO_FN(PINT5_PH),
GPIO_FN(PINT4_PH),
GPIO_FN(PINT3_PH),
GPIO_FN(PINT2_PH),
GPIO_FN(PINT1_PH),
GPIO_FN(PINT0_PH),
GPIO_FN(PINT7_PJ),
GPIO_FN(PINT6_PJ),
GPIO_FN(PINT5_PJ),
GPIO_FN(PINT4_PJ),
GPIO_FN(PINT3_PJ),
GPIO_FN(PINT2_PJ),
GPIO_FN(PINT1_PJ),
GPIO_FN(PINT0_PJ),
/* WDT */
GPIO_FN(WDTOVF),
/* CAN */
GPIO_FN(CTX1),
GPIO_FN(CRX1),
GPIO_FN(CTX0),
GPIO_FN(CRX0),
GPIO_FN(CRX0_CRX1),
GPIO_FN(CRX0_CRX1_CRX2),
/* DMAC */
GPIO_FN(TEND0),
GPIO_FN(DACK0),
GPIO_FN(DREQ0),
GPIO_FN(TEND1),
GPIO_FN(DACK1),
GPIO_FN(DREQ1),
/* ADC */
GPIO_FN(ADTRG),
/* BSCh */
GPIO_FN(A25),
GPIO_FN(A24),
GPIO_FN(A23),
GPIO_FN(A22),
GPIO_FN(A21),
GPIO_FN(A20),
GPIO_FN(A19),
GPIO_FN(A18),
GPIO_FN(A17),
GPIO_FN(A16),
GPIO_FN(A15),
GPIO_FN(A14),
GPIO_FN(A13),
GPIO_FN(A12),
GPIO_FN(A11),
GPIO_FN(A10),
GPIO_FN(A9),
GPIO_FN(A8),
GPIO_FN(A7),
GPIO_FN(A6),
GPIO_FN(A5),
GPIO_FN(A4),
GPIO_FN(A3),
GPIO_FN(A2),
GPIO_FN(A1),
GPIO_FN(A0),
GPIO_FN(D15),
GPIO_FN(D14),
GPIO_FN(D13),
GPIO_FN(D12),
GPIO_FN(D11),
GPIO_FN(D10),
GPIO_FN(D9),
GPIO_FN(D8),
GPIO_FN(D7),
GPIO_FN(D6),
GPIO_FN(D5),
GPIO_FN(D4),
GPIO_FN(D3),
GPIO_FN(D2),
GPIO_FN(D1),
GPIO_FN(D0),
GPIO_FN(BS),
GPIO_FN(CS4),
GPIO_FN(CS3),
GPIO_FN(CS2),
GPIO_FN(CS1),
GPIO_FN(CS0),
GPIO_FN(CS5CE1A),
GPIO_FN(CE2A),
GPIO_FN(CE2B),
GPIO_FN(RD),
GPIO_FN(RDWR),
GPIO_FN(WE3ICIOWRAHDQMUU),
GPIO_FN(WE2ICIORDDQMUL),
GPIO_FN(WE1DQMUWE),
GPIO_FN(WE0DQML),
GPIO_FN(RAS),
GPIO_FN(CAS),
GPIO_FN(CKE),
GPIO_FN(WAIT),
GPIO_FN(BREQ),
GPIO_FN(BACK),
GPIO_FN(IOIS16),
/* TMU */
GPIO_FN(TIOC4D),
GPIO_FN(TIOC4C),
GPIO_FN(TIOC4B),
GPIO_FN(TIOC4A),
GPIO_FN(TIOC3D),
GPIO_FN(TIOC3C),
GPIO_FN(TIOC3B),
GPIO_FN(TIOC3A),
GPIO_FN(TIOC2B),
GPIO_FN(TIOC1B),
GPIO_FN(TIOC2A),
GPIO_FN(TIOC1A),
GPIO_FN(TIOC0D),
GPIO_FN(TIOC0C),
GPIO_FN(TIOC0B),
GPIO_FN(TIOC0A),
GPIO_FN(TCLKD),
GPIO_FN(TCLKC),
GPIO_FN(TCLKB),
GPIO_FN(TCLKA),
/* SCIF */
GPIO_FN(SCK0),
GPIO_FN(TXD0),
GPIO_FN(RXD0),
GPIO_FN(SCK1),
GPIO_FN(TXD1),
GPIO_FN(RXD1),
GPIO_FN(RTS1),
GPIO_FN(CTS1),
GPIO_FN(SCK2),
GPIO_FN(TXD2),
GPIO_FN(RXD2),
GPIO_FN(SCK3),
GPIO_FN(TXD3),
GPIO_FN(RXD3),
GPIO_FN(SCK4),
GPIO_FN(TXD4),
GPIO_FN(RXD4),
GPIO_FN(SCK5),
GPIO_FN(TXD5),
GPIO_FN(RXD5),
GPIO_FN(RTS5),
GPIO_FN(CTS5),
GPIO_FN(SCK6),
GPIO_FN(TXD6),
GPIO_FN(RXD6),
GPIO_FN(SCK7),
GPIO_FN(TXD7),
GPIO_FN(RXD7),
GPIO_FN(RTS7),
GPIO_FN(CTS7),
/* RSPI */
GPIO_FN(RSPCK0_PJ16),
GPIO_FN(SSL00_PJ17),
GPIO_FN(MOSI0_PJ18),
GPIO_FN(MISO0_PJ19),
GPIO_FN(RSPCK0_PB17),
GPIO_FN(SSL00_PB18),
GPIO_FN(MOSI0_PB19),
GPIO_FN(MISO0_PB20),
GPIO_FN(RSPCK1),
GPIO_FN(MOSI1),
GPIO_FN(MISO1),
GPIO_FN(SSL10),
/* IIC3 */
GPIO_FN(SCL0),
GPIO_FN(SCL1),
GPIO_FN(SCL2),
GPIO_FN(SDA0),
GPIO_FN(SDA1),
GPIO_FN(SDA2),
/* SSI */
GPIO_FN(SSISCK0),
GPIO_FN(SSIWS0),
GPIO_FN(SSITXD0),
GPIO_FN(SSIRXD0),
GPIO_FN(SSIWS1),
GPIO_FN(SSIWS2),
GPIO_FN(SSIWS3),
GPIO_FN(SSISCK1),
GPIO_FN(SSISCK2),
GPIO_FN(SSISCK3),
GPIO_FN(SSIDATA1),
GPIO_FN(SSIDATA2),
GPIO_FN(SSIDATA3),
GPIO_FN(AUDIO_CLK),
GPIO_FN(AUDIO_XOUT),
/* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
GPIO_FN(SIOFTXD),
GPIO_FN(SIOFRXD),
GPIO_FN(SIOFSYNC),
GPIO_FN(SIOFSCK),
/* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
GPIO_FN(SPDIF_IN),
GPIO_FN(SPDIF_OUT),
/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
GPIO_FN(FCE),
GPIO_FN(FRB),
/* VDC3 */
GPIO_FN(DV_CLK),
GPIO_FN(DV_VSYNC),
GPIO_FN(DV_HSYNC),
GPIO_FN(DV_DATA23),
GPIO_FN(DV_DATA22),
GPIO_FN(DV_DATA21),
GPIO_FN(DV_DATA20),
GPIO_FN(DV_DATA19),
GPIO_FN(DV_DATA18),
GPIO_FN(DV_DATA17),
GPIO_FN(DV_DATA16),
GPIO_FN(DV_DATA15),
GPIO_FN(DV_DATA14),
GPIO_FN(DV_DATA13),
GPIO_FN(DV_DATA12),
GPIO_FN(DV_DATA11),
GPIO_FN(DV_DATA10),
GPIO_FN(DV_DATA9),
GPIO_FN(DV_DATA8),
GPIO_FN(DV_DATA7),
GPIO_FN(DV_DATA6),
GPIO_FN(DV_DATA5),
GPIO_FN(DV_DATA4),
GPIO_FN(DV_DATA3),
GPIO_FN(DV_DATA2),
GPIO_FN(DV_DATA1),
GPIO_FN(DV_DATA0),
GPIO_FN(LCD_CLK),
GPIO_FN(LCD_EXTCLK),
GPIO_FN(LCD_VSYNC),
GPIO_FN(LCD_HSYNC),
GPIO_FN(LCD_DE),
GPIO_FN(LCD_DATA23_PG23),
GPIO_FN(LCD_DATA22_PG22),
GPIO_FN(LCD_DATA21_PG21),
GPIO_FN(LCD_DATA20_PG20),
GPIO_FN(LCD_DATA19_PG19),
GPIO_FN(LCD_DATA18_PG18),
GPIO_FN(LCD_DATA17_PG17),
GPIO_FN(LCD_DATA16_PG16),
GPIO_FN(LCD_DATA15_PG15),
GPIO_FN(LCD_DATA14_PG14),
GPIO_FN(LCD_DATA13_PG13),
GPIO_FN(LCD_DATA12_PG12),
GPIO_FN(LCD_DATA11_PG11),
GPIO_FN(LCD_DATA10_PG10),
GPIO_FN(LCD_DATA9_PG9),
GPIO_FN(LCD_DATA8_PG8),
GPIO_FN(LCD_DATA7_PG7),
GPIO_FN(LCD_DATA6_PG6),
GPIO_FN(LCD_DATA5_PG5),
GPIO_FN(LCD_DATA4_PG4),
GPIO_FN(LCD_DATA3_PG3),
GPIO_FN(LCD_DATA2_PG2),
GPIO_FN(LCD_DATA1_PG1),
GPIO_FN(LCD_DATA0_PG0),
GPIO_FN(LCD_DATA23_PJ23),
GPIO_FN(LCD_DATA22_PJ22),
GPIO_FN(LCD_DATA21_PJ21),
GPIO_FN(LCD_DATA20_PJ20),
GPIO_FN(LCD_DATA19_PJ19),
GPIO_FN(LCD_DATA18_PJ18),
GPIO_FN(LCD_DATA17_PJ17),
GPIO_FN(LCD_DATA16_PJ16),
GPIO_FN(LCD_DATA15_PJ15),
GPIO_FN(LCD_DATA14_PJ14),
GPIO_FN(LCD_DATA13_PJ13),
GPIO_FN(LCD_DATA12_PJ12),
GPIO_FN(LCD_DATA11_PJ11),
GPIO_FN(LCD_DATA10_PJ10),
GPIO_FN(LCD_DATA9_PJ9),
GPIO_FN(LCD_DATA8_PJ8),
GPIO_FN(LCD_DATA7_PJ7),
GPIO_FN(LCD_DATA6_PJ6),
GPIO_FN(LCD_DATA5_PJ5),
GPIO_FN(LCD_DATA4_PJ4),
GPIO_FN(LCD_DATA3_PJ3),
GPIO_FN(LCD_DATA2_PJ2),
GPIO_FN(LCD_DATA1_PJ1),
GPIO_FN(LCD_DATA0_PJ0),
GPIO_FN(LCD_M_DISP),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* "name" addr register_size Field_Width */
/* where Field_Width is 1 for single mode registers or 4 for upto 16
@ -2734,7 +2738,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
static struct pinmux_data_reg pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
0, 0, 0, 0, 0, 0, 0, PA1_DATA,
0, 0, 0, 0, 0, 0, 0, PA0_DATA }
@ -2813,19 +2817,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ }
};
struct sh_pfc_soc_info sh7269_pinmux_info = {
const struct sh_pfc_soc_info sh7269_pinmux_info = {
.name = "sh7269_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PA1,
.last_gpio = GPIO_FN_LCD_M_DISP,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

323
drivers/pinctrl/sh-pfc/pfc-sh7372.c
View file

@ -368,7 +368,7 @@ enum {
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
static const pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
@ -929,11 +929,214 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
};
static struct pinmux_gpio pinmux_gpios[] = {
/* PORT */
static struct sh_pfc_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
};
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc0_data1_0_pins[] = {
/* D[0] */
84,
};
static const unsigned int mmc0_data1_0_mux[] = {
MMCD0_0_MARK,
};
static const unsigned int mmc0_data4_0_pins[] = {
/* D[0:3] */
84, 85, 86, 87,
};
static const unsigned int mmc0_data4_0_mux[] = {
MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
};
static const unsigned int mmc0_data8_0_pins[] = {
/* D[0:7] */
84, 85, 86, 87, 88, 89, 90, 91,
};
static const unsigned int mmc0_data8_0_mux[] = {
MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
};
static const unsigned int mmc0_ctrl_0_pins[] = {
/* CMD, CLK */
92, 99,
};
static const unsigned int mmc0_ctrl_0_mux[] = {
MMCCMD0_MARK, MMCCLK0_MARK,
};
static const unsigned int mmc0_data1_1_pins[] = {
/* D[0] */
54,
};
static const unsigned int mmc0_data1_1_mux[] = {
MMCD1_0_MARK,
};
static const unsigned int mmc0_data4_1_pins[] = {
/* D[0:3] */
54, 55, 56, 57,
};
static const unsigned int mmc0_data4_1_mux[] = {
MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
};
static const unsigned int mmc0_data8_1_pins[] = {
/* D[0:7] */
54, 55, 56, 57, 58, 59, 60, 61,
};
static const unsigned int mmc0_data8_1_mux[] = {
MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
};
static const unsigned int mmc0_ctrl_1_pins[] = {
/* CMD, CLK */
67, 66,
};
static const unsigned int mmc0_ctrl_1_mux[] = {
MMCCMD1_MARK, MMCCLK1_MARK,
};
/* - SDHI0 ------------------------------------------------------------------ */
static const unsigned int sdhi0_data1_pins[] = {
/* D0 */
173,
};
static const unsigned int sdhi0_data1_mux[] = {
SDHID0_0_MARK,
};
static const unsigned int sdhi0_data4_pins[] = {
/* D[0:3] */
173, 174, 175, 176,
};
static const unsigned int sdhi0_data4_mux[] = {
SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
};
static const unsigned int sdhi0_ctrl_pins[] = {
/* CMD, CLK */
177, 171,
};
static const unsigned int sdhi0_ctrl_mux[] = {
SDHICMD0_MARK, SDHICLK0_MARK,
};
static const unsigned int sdhi0_cd_pins[] = {
/* CD */
172,
};
static const unsigned int sdhi0_cd_mux[] = {
SDHICD0_MARK,
};
static const unsigned int sdhi0_wp_pins[] = {
/* WP */
178,
};
static const unsigned int sdhi0_wp_mux[] = {
SDHIWP0_MARK,
};
/* - SDHI1 ------------------------------------------------------------------ */
static const unsigned int sdhi1_data1_pins[] = {
/* D0 */
180,
};
static const unsigned int sdhi1_data1_mux[] = {
SDHID1_0_MARK,
};
static const unsigned int sdhi1_data4_pins[] = {
/* D[0:3] */
180, 181, 182, 183,
};
static const unsigned int sdhi1_data4_mux[] = {
SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
};
static const unsigned int sdhi1_ctrl_pins[] = {
/* CMD, CLK */
184, 179,
};
static const unsigned int sdhi1_ctrl_mux[] = {
SDHICMD1_MARK, SDHICLK1_MARK,
};
static const unsigned int sdhi2_data1_pins[] = {
/* D0 */
186,
};
static const unsigned int sdhi2_data1_mux[] = {
SDHID2_0_MARK,
};
static const unsigned int sdhi2_data4_pins[] = {
/* D[0:3] */
186, 187, 188, 189,
};
static const unsigned int sdhi2_data4_mux[] = {
SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
};
static const unsigned int sdhi2_ctrl_pins[] = {
/* CMD, CLK */
190, 185,
};
static const unsigned int sdhi2_ctrl_mux[] = {
SDHICMD2_MARK, SDHICLK2_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(mmc0_data1_0),
SH_PFC_PIN_GROUP(mmc0_data4_0),
SH_PFC_PIN_GROUP(mmc0_data8_0),
SH_PFC_PIN_GROUP(mmc0_ctrl_0),
SH_PFC_PIN_GROUP(mmc0_data1_1),
SH_PFC_PIN_GROUP(mmc0_data4_1),
SH_PFC_PIN_GROUP(mmc0_data8_1),
SH_PFC_PIN_GROUP(mmc0_ctrl_1),
SH_PFC_PIN_GROUP(sdhi0_data1),
SH_PFC_PIN_GROUP(sdhi0_data4),
SH_PFC_PIN_GROUP(sdhi0_ctrl),
SH_PFC_PIN_GROUP(sdhi0_cd),
SH_PFC_PIN_GROUP(sdhi0_wp),
SH_PFC_PIN_GROUP(sdhi1_data1),
SH_PFC_PIN_GROUP(sdhi1_data4),
SH_PFC_PIN_GROUP(sdhi1_ctrl),
SH_PFC_PIN_GROUP(sdhi2_data1),
SH_PFC_PIN_GROUP(sdhi2_data4),
SH_PFC_PIN_GROUP(sdhi2_ctrl),
};
static const char * const mmc0_groups[] = {
"mmc0_data1_0",
"mmc0_data4_0",
"mmc0_data8_0",
"mmc0_ctrl_0",
"mmc0_data1_1",
"mmc0_data4_1",
"mmc0_data8_1",
"mmc0_ctrl_1",
};
static const char * const sdhi0_groups[] = {
"sdhi0_data1",
"sdhi0_data4",
"sdhi0_ctrl",
"sdhi0_cd",
"sdhi0_wp",
};
static const char * const sdhi1_groups[] = {
"sdhi1_data1",
"sdhi1_data4",
"sdhi1_ctrl",
};
static const char * const sdhi2_groups[] = {
"sdhi2_data1",
"sdhi2_data4",
"sdhi2_ctrl",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(mmc0),
SH_PFC_FUNCTION(sdhi0),
SH_PFC_FUNCTION(sdhi1),
SH_PFC_FUNCTION(sdhi2),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
/* IRQ */
GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1),
GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8),
@ -1074,18 +1277,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13),
GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15),
/* MMCIF(1) */
GPIO_FN(MMCD0_0), GPIO_FN(MMCD0_1), GPIO_FN(MMCD0_2),
GPIO_FN(MMCD0_3), GPIO_FN(MMCD0_4), GPIO_FN(MMCD0_5),
GPIO_FN(MMCD0_6), GPIO_FN(MMCD0_7), GPIO_FN(MMCCMD0),
GPIO_FN(MMCCLK0),
/* MMCIF(2) */
GPIO_FN(MMCD1_0), GPIO_FN(MMCD1_1), GPIO_FN(MMCD1_2),
GPIO_FN(MMCD1_3), GPIO_FN(MMCD1_4), GPIO_FN(MMCD1_5),
GPIO_FN(MMCD1_6), GPIO_FN(MMCD1_7), GPIO_FN(MMCCLK1),
GPIO_FN(MMCCMD1),
/* SPU2 */
GPIO_FN(VINT_I),
@ -1182,25 +1373,12 @@ static struct pinmux_gpio pinmux_gpios[] = {
/* HDMI */
GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC),
/* SDHI0 */
GPIO_FN(SDHICLK0), GPIO_FN(SDHICD0), GPIO_FN(SDHICMD0),
GPIO_FN(SDHIWP0), GPIO_FN(SDHID0_0), GPIO_FN(SDHID0_1),
GPIO_FN(SDHID0_2), GPIO_FN(SDHID0_3),
/* SDHI1 */
GPIO_FN(SDHICLK1), GPIO_FN(SDHICMD1), GPIO_FN(SDHID1_0),
GPIO_FN(SDHID1_1), GPIO_FN(SDHID1_2), GPIO_FN(SDHID1_3),
/* SDHI2 */
GPIO_FN(SDHICLK2), GPIO_FN(SDHICMD2), GPIO_FN(SDHID2_0),
GPIO_FN(SDHID2_1), GPIO_FN(SDHID2_2), GPIO_FN(SDHID2_3),
/* SDENC */
GPIO_FN(SDENC_CPG),
GPIO_FN(SDENC_DV_CLKI),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xE6051000), /* PORT0CR */
PORTCR(1, 0xE6051001), /* PORT1CR */
PORTCR(2, 0xE6051002), /* PORT2CR */
@ -1472,7 +1650,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static struct pinmux_data_reg pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) {
PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
@ -1597,56 +1775,59 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
static struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0),
PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0),
PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0),
PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0),
PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0),
PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0),
PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0),
PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0),
PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0),
PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0),
PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0),
PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0),
PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0),
PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0),
PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0),
PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0),
PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0),
PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0),
PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0),
PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0),
PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0),
PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0),
PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0),
PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0),
PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0),
PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0),
PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0),
PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0),
PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0),
PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0),
PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0),
PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0),
static const struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162),
PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12),
PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5),
PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16),
PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163),
PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18),
PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164),
PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167),
PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168),
PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169),
PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65),
PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67),
PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137),
PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145),
PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146),
PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147),
PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170),
PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85),
PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86),
PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87),
PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92),
PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93),
PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94),
PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95),
PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112),
PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119),
PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172),
PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180),
PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181),
PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182),
PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183),
PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184),
};
struct sh_pfc_soc_info sh7372_pinmux_info = {
const struct sh_pfc_soc_info sh7372_pinmux_info = {
.name = "sh7372_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PORT0,
.last_gpio = GPIO_FN_SDENC_DV_CLKI,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.groups = pinmux_groups,
.nr_groups = ARRAY_SIZE(pinmux_groups),
.functions = pinmux_functions,
.nr_functions = ARRAY_SIZE(pinmux_functions),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

2648
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
View file

File diff suppressed because it is too large Load diff

409
drivers/pinctrl/sh-pfc/pfc-sh7720.c
View file

@ -262,7 +262,7 @@ enum {
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
static const pinmux_enum_t pinmux_data[] = {
/* PTA GPIO */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
@ -606,7 +606,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN),
};
static struct pinmux_gpio pinmux_gpios[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@ -759,202 +759,205 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
/* BSC */
PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK),
PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK),
PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
/* LCDC */
PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK),
PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK),
PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK),
PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK),
PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK),
/* AFEIF */
PINMUX_GPIO(GPIO_FN_AFE_RXIN, AFE_RXIN_MARK),
PINMUX_GPIO(GPIO_FN_AFE_RDET, AFE_RDET_MARK),
PINMUX_GPIO(GPIO_FN_AFE_FS, AFE_FS_MARK),
PINMUX_GPIO(GPIO_FN_AFE_TXOUT, AFE_TXOUT_MARK),
PINMUX_GPIO(GPIO_FN_AFE_SCLK, AFE_SCLK_MARK),
PINMUX_GPIO(GPIO_FN_AFE_RLYCNT, AFE_RLYCNT_MARK),
PINMUX_GPIO(GPIO_FN_AFE_HC1, AFE_HC1_MARK),
/* IIC */
PINMUX_GPIO(GPIO_FN_IIC_SCL, IIC_SCL_MARK),
PINMUX_GPIO(GPIO_FN_IIC_SDA, IIC_SDA_MARK),
/* DAC */
PINMUX_GPIO(GPIO_FN_DA1, DA1_MARK),
PINMUX_GPIO(GPIO_FN_DA0, DA0_MARK),
/* ADC */
PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK),
PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK),
PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK),
PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK),
PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
/* USB */
PINMUX_GPIO(GPIO_FN_USB1D_RCV, USB1D_RCV_MARK),
PINMUX_GPIO(GPIO_FN_USB1D_TXSE0, USB1D_TXSE0_MARK),
PINMUX_GPIO(GPIO_FN_USB1D_TXDPLS, USB1D_TXDPLS_MARK),
PINMUX_GPIO(GPIO_FN_USB1D_DMNS, USB1D_DMNS_MARK),
PINMUX_GPIO(GPIO_FN_USB1D_DPLS, USB1D_DPLS_MARK),
PINMUX_GPIO(GPIO_FN_USB1D_SPEED, USB1D_SPEED_MARK),
PINMUX_GPIO(GPIO_FN_USB1D_TXENL, USB1D_TXENL_MARK),
PINMUX_GPIO(GPIO_FN_USB2_PWR_EN, USB2_PWR_EN_MARK),
PINMUX_GPIO(GPIO_FN_USB1_PWR_EN_USBF_UPLUP,
USB1_PWR_EN_USBF_UPLUP_MARK),
PINMUX_GPIO(GPIO_FN_USB1D_SUSPEND, USB1D_SUSPEND_MARK),
/* INTC */
PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3_IRL3, IRQ3_IRL3_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2_IRL2, IRQ2_IRL2_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1_IRL1, IRQ1_IRL1_MARK),
PINMUX_GPIO(GPIO_FN_IRQ0_IRL0, IRQ0_IRL0_MARK),
/* PCC */
PINMUX_GPIO(GPIO_FN_PCC_REG, PCC_REG_MARK),
PINMUX_GPIO(GPIO_FN_PCC_DRV, PCC_DRV_MARK),
PINMUX_GPIO(GPIO_FN_PCC_BVD2, PCC_BVD2_MARK),
PINMUX_GPIO(GPIO_FN_PCC_BVD1, PCC_BVD1_MARK),
PINMUX_GPIO(GPIO_FN_PCC_CD2, PCC_CD2_MARK),
PINMUX_GPIO(GPIO_FN_PCC_CD1, PCC_CD1_MARK),
PINMUX_GPIO(GPIO_FN_PCC_RESET, PCC_RESET_MARK),
PINMUX_GPIO(GPIO_FN_PCC_RDY, PCC_RDY_MARK),
PINMUX_GPIO(GPIO_FN_PCC_VS2, PCC_VS2_MARK),
PINMUX_GPIO(GPIO_FN_PCC_VS1, PCC_VS1_MARK),
/* HUDI */
PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
PINMUX_GPIO(GPIO_FN_ASEBRKAK, ASEBRKAK_MARK),
PINMUX_GPIO(GPIO_FN_TRST, TRST_MARK),
PINMUX_GPIO(GPIO_FN_TMS, TMS_MARK),
PINMUX_GPIO(GPIO_FN_TDO, TDO_MARK),
PINMUX_GPIO(GPIO_FN_TDI, TDI_MARK),
PINMUX_GPIO(GPIO_FN_TCK, TCK_MARK),
/* DMAC */
PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
/* SIOF0 */
PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK),
PINMUX_GPIO(GPIO_FN_SIOF0_MCLK, SIOF0_MCLK_MARK),
PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK),
/* SIOF1 */
PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK),
PINMUX_GPIO(GPIO_FN_SIOF1_MCLK, SIOF1_MCLK_MARK),
PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK),
/* SCIF0 */
PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
/* SCIF1 */
PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
/* TPU */
PINMUX_GPIO(GPIO_FN_TPU_TO1, TPU_TO1_MARK),
PINMUX_GPIO(GPIO_FN_TPU_TO0, TPU_TO0_MARK),
PINMUX_GPIO(GPIO_FN_TPU_TI3B, TPU_TI3B_MARK),
PINMUX_GPIO(GPIO_FN_TPU_TI3A, TPU_TI3A_MARK),
PINMUX_GPIO(GPIO_FN_TPU_TI2B, TPU_TI2B_MARK),
PINMUX_GPIO(GPIO_FN_TPU_TI2A, TPU_TI2A_MARK),
PINMUX_GPIO(GPIO_FN_TPU_TO3, TPU_TO3_MARK),
PINMUX_GPIO(GPIO_FN_TPU_TO2, TPU_TO2_MARK),
/* SIM */
PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
/* MMC */
PINMUX_GPIO(GPIO_FN_MMC_DAT, MMC_DAT_MARK),
PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK),
PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK),
PINMUX_GPIO(GPIO_FN_MMC_VDDON, MMC_VDDON_MARK),
PINMUX_GPIO(GPIO_FN_MMC_ODMOD, MMC_ODMOD_MARK),
/* SYSC */
PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
/* BSC */
GPIO_FN(D31),
GPIO_FN(D30),
GPIO_FN(D29),
GPIO_FN(D28),
GPIO_FN(D27),
GPIO_FN(D26),
GPIO_FN(D25),
GPIO_FN(D24),
GPIO_FN(D23),
GPIO_FN(D22),
GPIO_FN(D21),
GPIO_FN(D20),
GPIO_FN(D19),
GPIO_FN(D18),
GPIO_FN(D17),
GPIO_FN(D16),
GPIO_FN(IOIS16),
GPIO_FN(RAS),
GPIO_FN(CAS),
GPIO_FN(CKE),
GPIO_FN(CS5B_CE1A),
GPIO_FN(CS6B_CE1B),
GPIO_FN(A25),
GPIO_FN(A24),
GPIO_FN(A23),
GPIO_FN(A22),
GPIO_FN(A21),
GPIO_FN(A20),
GPIO_FN(A19),
GPIO_FN(A0),
GPIO_FN(REFOUT),
GPIO_FN(IRQOUT),
/* LCDC */
GPIO_FN(LCD_DATA15),
GPIO_FN(LCD_DATA14),
GPIO_FN(LCD_DATA13),
GPIO_FN(LCD_DATA12),
GPIO_FN(LCD_DATA11),
GPIO_FN(LCD_DATA10),
GPIO_FN(LCD_DATA9),
GPIO_FN(LCD_DATA8),
GPIO_FN(LCD_DATA7),
GPIO_FN(LCD_DATA6),
GPIO_FN(LCD_DATA5),
GPIO_FN(LCD_DATA4),
GPIO_FN(LCD_DATA3),
GPIO_FN(LCD_DATA2),
GPIO_FN(LCD_DATA1),
GPIO_FN(LCD_DATA0),
GPIO_FN(LCD_M_DISP),
GPIO_FN(LCD_CL1),
GPIO_FN(LCD_CL2),
GPIO_FN(LCD_DON),
GPIO_FN(LCD_FLM),
GPIO_FN(LCD_VEPWC),
GPIO_FN(LCD_VCPWC),
/* AFEIF */
GPIO_FN(AFE_RXIN),
GPIO_FN(AFE_RDET),
GPIO_FN(AFE_FS),
GPIO_FN(AFE_TXOUT),
GPIO_FN(AFE_SCLK),
GPIO_FN(AFE_RLYCNT),
GPIO_FN(AFE_HC1),
/* IIC */
GPIO_FN(IIC_SCL),
GPIO_FN(IIC_SDA),
/* DAC */
GPIO_FN(DA1),
GPIO_FN(DA0),
/* ADC */
GPIO_FN(AN3),
GPIO_FN(AN2),
GPIO_FN(AN1),
GPIO_FN(AN0),
GPIO_FN(ADTRG),
/* USB */
GPIO_FN(USB1D_RCV),
GPIO_FN(USB1D_TXSE0),
GPIO_FN(USB1D_TXDPLS),
GPIO_FN(USB1D_DMNS),
GPIO_FN(USB1D_DPLS),
GPIO_FN(USB1D_SPEED),
GPIO_FN(USB1D_TXENL),
GPIO_FN(USB2_PWR_EN),
GPIO_FN(USB1_PWR_EN_USBF_UPLUP),
GPIO_FN(USB1D_SUSPEND),
/* INTC */
GPIO_FN(IRQ5),
GPIO_FN(IRQ4),
GPIO_FN(IRQ3_IRL3),
GPIO_FN(IRQ2_IRL2),
GPIO_FN(IRQ1_IRL1),
GPIO_FN(IRQ0_IRL0),
/* PCC */
GPIO_FN(PCC_REG),
GPIO_FN(PCC_DRV),
GPIO_FN(PCC_BVD2),
GPIO_FN(PCC_BVD1),
GPIO_FN(PCC_CD2),
GPIO_FN(PCC_CD1),
GPIO_FN(PCC_RESET),
GPIO_FN(PCC_RDY),
GPIO_FN(PCC_VS2),
GPIO_FN(PCC_VS1),
/* HUDI */
GPIO_FN(AUDATA3),
GPIO_FN(AUDATA2),
GPIO_FN(AUDATA1),
GPIO_FN(AUDATA0),
GPIO_FN(AUDCK),
GPIO_FN(AUDSYNC),
GPIO_FN(ASEBRKAK),
GPIO_FN(TRST),
GPIO_FN(TMS),
GPIO_FN(TDO),
GPIO_FN(TDI),
GPIO_FN(TCK),
/* DMAC */
GPIO_FN(DACK1),
GPIO_FN(DREQ1),
GPIO_FN(DACK0),
GPIO_FN(DREQ0),
GPIO_FN(TEND1),
GPIO_FN(TEND0),
/* SIOF0 */
GPIO_FN(SIOF0_SYNC),
GPIO_FN(SIOF0_MCLK),
GPIO_FN(SIOF0_TXD),
GPIO_FN(SIOF0_RXD),
GPIO_FN(SIOF0_SCK),
/* SIOF1 */
GPIO_FN(SIOF1_SYNC),
GPIO_FN(SIOF1_MCLK),
GPIO_FN(SIOF1_TXD),
GPIO_FN(SIOF1_RXD),
GPIO_FN(SIOF1_SCK),
/* SCIF0 */
GPIO_FN(SCIF0_TXD),
GPIO_FN(SCIF0_RXD),
GPIO_FN(SCIF0_RTS),
GPIO_FN(SCIF0_CTS),
GPIO_FN(SCIF0_SCK),
/* SCIF1 */
GPIO_FN(SCIF1_TXD),
GPIO_FN(SCIF1_RXD),
GPIO_FN(SCIF1_RTS),
GPIO_FN(SCIF1_CTS),
GPIO_FN(SCIF1_SCK),
/* TPU */
GPIO_FN(TPU_TO1),
GPIO_FN(TPU_TO0),
GPIO_FN(TPU_TI3B),
GPIO_FN(TPU_TI3A),
GPIO_FN(TPU_TI2B),
GPIO_FN(TPU_TI2A),
GPIO_FN(TPU_TO3),
GPIO_FN(TPU_TO2),
/* SIM */
GPIO_FN(SIM_D),
GPIO_FN(SIM_CLK),
GPIO_FN(SIM_RST),
/* MMC */
GPIO_FN(MMC_DAT),
GPIO_FN(MMC_CMD),
GPIO_FN(MMC_CLK),
GPIO_FN(MMC_VDDON),
GPIO_FN(MMC_ODMOD),
/* SYSC */
GPIO_FN(STATUS0),
GPIO_FN(STATUS1),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
@ -1138,7 +1141,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
static struct pinmux_data_reg pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xa4050140, 8) {
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@ -1214,20 +1217,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
struct sh_pfc_soc_info sh7720_pinmux_info = {
const struct sh_pfc_soc_info sh7720_pinmux_info = {
.name = "sh7720_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PTA7,
.last_gpio = GPIO_FN_STATUS1,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

584
drivers/pinctrl/sh-pfc/pfc-sh7722.c
View file

@ -296,7 +296,7 @@ enum {
PINMUX_FUNCTION_END,
};
static pinmux_enum_t pinmux_data[] = {
static const pinmux_enum_t pinmux_data[] = {
/* PTA */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD),
@ -787,7 +787,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5),
};
static struct pinmux_gpio pinmux_gpios[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@ -982,289 +982,293 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
/* SCIF0 */
PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
/* SCIF1 */
PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
/* SCIF2 */
PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_RTS, SCIF2_RTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_CTS, SCIF2_CTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK),
/* SIO */
PINMUX_GPIO(GPIO_FN_SIOTXD, SIOTXD_MARK),
PINMUX_GPIO(GPIO_FN_SIORXD, SIORXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOD, SIOD_MARK),
PINMUX_GPIO(GPIO_FN_SIOSTRB0, SIOSTRB0_MARK),
PINMUX_GPIO(GPIO_FN_SIOSTRB1, SIOSTRB1_MARK),
PINMUX_GPIO(GPIO_FN_SIOSCK, SIOSCK_MARK),
PINMUX_GPIO(GPIO_FN_SIOMCK, SIOMCK_MARK),
/* CEU */
PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK),
PINMUX_GPIO(GPIO_FN_VIO_CLK, VIO_CLK_MARK),
PINMUX_GPIO(GPIO_FN_VIO_VD, VIO_VD_MARK),
PINMUX_GPIO(GPIO_FN_VIO_HD, VIO_HD_MARK),
PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK),
PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK),
PINMUX_GPIO(GPIO_FN_VIO_STEX, VIO_STEX_MARK),
PINMUX_GPIO(GPIO_FN_VIO_STEM, VIO_STEM_MARK),
PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK),
PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK),
PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK),
/* LCDC */
PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK),
PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK),
PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK),
PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK),
PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK),
PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK),
PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK),
PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK),
PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK),
PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK),
PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK),
PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK),
PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK),
PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK),
PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK),
PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK),
PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK),
PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK),
PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK),
PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK),
PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK),
PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK),
PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK),
PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK),
PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK),
/* Main LCD */
PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK),
PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK),
PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK),
PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK),
/* Main LCD - RGB Mode */
PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK),
PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK),
PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK),
/* Main LCD - SYS Mode */
PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK),
PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK),
PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK),
PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK),
/* Sub LCD - SYS Mode */
PINMUX_GPIO(GPIO_FN_LCDDON2, LCDDON2_MARK),
PINMUX_GPIO(GPIO_FN_LCDVCPWC2, LCDVCPWC2_MARK),
PINMUX_GPIO(GPIO_FN_LCDVEPWC2, LCDVEPWC2_MARK),
PINMUX_GPIO(GPIO_FN_LCDVSYN2, LCDVSYN2_MARK),
PINMUX_GPIO(GPIO_FN_LCDCS2, LCDCS2_MARK),
/* BSC */
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK),
/* SBSC */
PINMUX_GPIO(GPIO_FN_HPD63, HPD63_MARK),
PINMUX_GPIO(GPIO_FN_HPD62, HPD62_MARK),
PINMUX_GPIO(GPIO_FN_HPD61, HPD61_MARK),
PINMUX_GPIO(GPIO_FN_HPD60, HPD60_MARK),
PINMUX_GPIO(GPIO_FN_HPD59, HPD59_MARK),
PINMUX_GPIO(GPIO_FN_HPD58, HPD58_MARK),
PINMUX_GPIO(GPIO_FN_HPD57, HPD57_MARK),
PINMUX_GPIO(GPIO_FN_HPD56, HPD56_MARK),
PINMUX_GPIO(GPIO_FN_HPD55, HPD55_MARK),
PINMUX_GPIO(GPIO_FN_HPD54, HPD54_MARK),
PINMUX_GPIO(GPIO_FN_HPD53, HPD53_MARK),
PINMUX_GPIO(GPIO_FN_HPD52, HPD52_MARK),
PINMUX_GPIO(GPIO_FN_HPD51, HPD51_MARK),
PINMUX_GPIO(GPIO_FN_HPD50, HPD50_MARK),
PINMUX_GPIO(GPIO_FN_HPD49, HPD49_MARK),
PINMUX_GPIO(GPIO_FN_HPD48, HPD48_MARK),
PINMUX_GPIO(GPIO_FN_HPDQM7, HPDQM7_MARK),
PINMUX_GPIO(GPIO_FN_HPDQM6, HPDQM6_MARK),
PINMUX_GPIO(GPIO_FN_HPDQM5, HPDQM5_MARK),
PINMUX_GPIO(GPIO_FN_HPDQM4, HPDQM4_MARK),
/* IRQ */
PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
/* SDHI */
PINMUX_GPIO(GPIO_FN_SDHICD, SDHICD_MARK),
PINMUX_GPIO(GPIO_FN_SDHIWP, SDHIWP_MARK),
PINMUX_GPIO(GPIO_FN_SDHID3, SDHID3_MARK),
PINMUX_GPIO(GPIO_FN_SDHID2, SDHID2_MARK),
PINMUX_GPIO(GPIO_FN_SDHID1, SDHID1_MARK),
PINMUX_GPIO(GPIO_FN_SDHID0, SDHID0_MARK),
PINMUX_GPIO(GPIO_FN_SDHICMD, SDHICMD_MARK),
PINMUX_GPIO(GPIO_FN_SDHICLK, SDHICLK_MARK),
/* SIU - Port A */
PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK),
PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK),
PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK),
PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK),
PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK),
PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK),
PINMUX_GPIO(GPIO_FN_SIUMCKA, SIUMCKA_MARK),
PINMUX_GPIO(GPIO_FN_SIUFCKA, SIUFCKA_MARK),
/* SIU - Port B */
PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK),
PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK),
PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK),
PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK),
PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK),
PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK),
PINMUX_GPIO(GPIO_FN_SIUMCKB, SIUMCKB_MARK),
PINMUX_GPIO(GPIO_FN_SIUFCKB, SIUFCKB_MARK),
/* AUD */
PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
/* DMAC */
PINMUX_GPIO(GPIO_FN_DACK, DACK_MARK),
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
/* VOU */
PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK),
PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK),
PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK),
PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK),
PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK),
PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK),
PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK),
PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK),
PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK),
PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK),
PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK),
PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK),
PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK),
PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK),
PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK),
PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK),
PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK),
/* CPG */
PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK),
/* SIOF0 */
PINMUX_GPIO(GPIO_FN_SIOF0_MCK, SIOF0_MCK_MARK),
PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK),
PINMUX_GPIO(GPIO_FN_SIOF0_SS1, SIOF0_SS1_MARK),
PINMUX_GPIO(GPIO_FN_SIOF0_SS2, SIOF0_SS2_MARK),
PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK),
/* SIOF1 */
PINMUX_GPIO(GPIO_FN_SIOF1_MCK, SIOF1_MCK_MARK),
PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK),
PINMUX_GPIO(GPIO_FN_SIOF1_SS1, SIOF1_SS1_MARK),
PINMUX_GPIO(GPIO_FN_SIOF1_SS2, SIOF1_SS2_MARK),
PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK),
/* SIM */
PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
/* TSIF */
PINMUX_GPIO(GPIO_FN_TS_SDAT, TS_SDAT_MARK),
PINMUX_GPIO(GPIO_FN_TS_SCK, TS_SCK_MARK),
PINMUX_GPIO(GPIO_FN_TS_SDEN, TS_SDEN_MARK),
PINMUX_GPIO(GPIO_FN_TS_SPSYNC, TS_SPSYNC_MARK),
/* IRDA */
PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK),
PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK),
/* TPU */
PINMUX_GPIO(GPIO_FN_TPUTO, TPUTO_MARK),
/* FLCTL */
PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK),
PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK),
PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK),
PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK),
PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK),
PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK),
PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK),
PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK),
PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK),
PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK),
PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK),
PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
/* KEYSC */
PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK),
PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK),
PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK),
PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK),
PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
/* SCIF0 */
GPIO_FN(SCIF0_TXD),
GPIO_FN(SCIF0_RXD),
GPIO_FN(SCIF0_RTS),
GPIO_FN(SCIF0_CTS),
GPIO_FN(SCIF0_SCK),
/* SCIF1 */
GPIO_FN(SCIF1_TXD),
GPIO_FN(SCIF1_RXD),
GPIO_FN(SCIF1_RTS),
GPIO_FN(SCIF1_CTS),
GPIO_FN(SCIF1_SCK),
/* SCIF2 */
GPIO_FN(SCIF2_TXD),
GPIO_FN(SCIF2_RXD),
GPIO_FN(SCIF2_RTS),
GPIO_FN(SCIF2_CTS),
GPIO_FN(SCIF2_SCK),
/* SIO */
GPIO_FN(SIOTXD),
GPIO_FN(SIORXD),
GPIO_FN(SIOD),
GPIO_FN(SIOSTRB0),
GPIO_FN(SIOSTRB1),
GPIO_FN(SIOSCK),
GPIO_FN(SIOMCK),
/* CEU */
GPIO_FN(VIO_D15),
GPIO_FN(VIO_D14),
GPIO_FN(VIO_D13),
GPIO_FN(VIO_D12),
GPIO_FN(VIO_D11),
GPIO_FN(VIO_D10),
GPIO_FN(VIO_D9),
GPIO_FN(VIO_D8),
GPIO_FN(VIO_D7),
GPIO_FN(VIO_D6),
GPIO_FN(VIO_D5),
GPIO_FN(VIO_D4),
GPIO_FN(VIO_D3),
GPIO_FN(VIO_D2),
GPIO_FN(VIO_D1),
GPIO_FN(VIO_D0),
GPIO_FN(VIO_CLK),
GPIO_FN(VIO_VD),
GPIO_FN(VIO_HD),
GPIO_FN(VIO_FLD),
GPIO_FN(VIO_CKO),
GPIO_FN(VIO_STEX),
GPIO_FN(VIO_STEM),
GPIO_FN(VIO_VD2),
GPIO_FN(VIO_HD2),
GPIO_FN(VIO_CLK2),
/* LCDC */
GPIO_FN(LCDD23),
GPIO_FN(LCDD22),
GPIO_FN(LCDD21),
GPIO_FN(LCDD20),
GPIO_FN(LCDD19),
GPIO_FN(LCDD18),
GPIO_FN(LCDD17),
GPIO_FN(LCDD16),
GPIO_FN(LCDD15),
GPIO_FN(LCDD14),
GPIO_FN(LCDD13),
GPIO_FN(LCDD12),
GPIO_FN(LCDD11),
GPIO_FN(LCDD10),
GPIO_FN(LCDD9),
GPIO_FN(LCDD8),
GPIO_FN(LCDD7),
GPIO_FN(LCDD6),
GPIO_FN(LCDD5),
GPIO_FN(LCDD4),
GPIO_FN(LCDD3),
GPIO_FN(LCDD2),
GPIO_FN(LCDD1),
GPIO_FN(LCDD0),
GPIO_FN(LCDLCLK),
/* Main LCD */
GPIO_FN(LCDDON),
GPIO_FN(LCDVCPWC),
GPIO_FN(LCDVEPWC),
GPIO_FN(LCDVSYN),
/* Main LCD - RGB Mode */
GPIO_FN(LCDDCK),
GPIO_FN(LCDHSYN),
GPIO_FN(LCDDISP),
/* Main LCD - SYS Mode */
GPIO_FN(LCDRS),
GPIO_FN(LCDCS),
GPIO_FN(LCDWR),
GPIO_FN(LCDRD),
/* Sub LCD - SYS Mode */
GPIO_FN(LCDDON2),
GPIO_FN(LCDVCPWC2),
GPIO_FN(LCDVEPWC2),
GPIO_FN(LCDVSYN2),
GPIO_FN(LCDCS2),
/* BSC */
GPIO_FN(IOIS16),
GPIO_FN(A25),
GPIO_FN(A24),
GPIO_FN(A23),
GPIO_FN(A22),
GPIO_FN(BS),
GPIO_FN(CS6B_CE1B),
GPIO_FN(WAIT),
GPIO_FN(CS6A_CE2B),
/* SBSC */
GPIO_FN(HPD63),
GPIO_FN(HPD62),
GPIO_FN(HPD61),
GPIO_FN(HPD60),
GPIO_FN(HPD59),
GPIO_FN(HPD58),
GPIO_FN(HPD57),
GPIO_FN(HPD56),
GPIO_FN(HPD55),
GPIO_FN(HPD54),
GPIO_FN(HPD53),
GPIO_FN(HPD52),
GPIO_FN(HPD51),
GPIO_FN(HPD50),
GPIO_FN(HPD49),
GPIO_FN(HPD48),
GPIO_FN(HPDQM7),
GPIO_FN(HPDQM6),
GPIO_FN(HPDQM5),
GPIO_FN(HPDQM4),
/* IRQ */
GPIO_FN(IRQ0),
GPIO_FN(IRQ1),
GPIO_FN(IRQ2),
GPIO_FN(IRQ3),
GPIO_FN(IRQ4),
GPIO_FN(IRQ5),
GPIO_FN(IRQ6),
GPIO_FN(IRQ7),
/* SDHI */
GPIO_FN(SDHICD),
GPIO_FN(SDHIWP),
GPIO_FN(SDHID3),
GPIO_FN(SDHID2),
GPIO_FN(SDHID1),
GPIO_FN(SDHID0),
GPIO_FN(SDHICMD),
GPIO_FN(SDHICLK),
/* SIU - Port A */
GPIO_FN(SIUAOLR),
GPIO_FN(SIUAOBT),
GPIO_FN(SIUAISLD),
GPIO_FN(SIUAILR),
GPIO_FN(SIUAIBT),
GPIO_FN(SIUAOSLD),
GPIO_FN(SIUMCKA),
GPIO_FN(SIUFCKA),
/* SIU - Port B */
GPIO_FN(SIUBOLR),
GPIO_FN(SIUBOBT),
GPIO_FN(SIUBISLD),
GPIO_FN(SIUBILR),
GPIO_FN(SIUBIBT),
GPIO_FN(SIUBOSLD),
GPIO_FN(SIUMCKB),
GPIO_FN(SIUFCKB),
/* AUD */
GPIO_FN(AUDSYNC),
GPIO_FN(AUDATA3),
GPIO_FN(AUDATA2),
GPIO_FN(AUDATA1),
GPIO_FN(AUDATA0),
/* DMAC */
GPIO_FN(DACK),
GPIO_FN(DREQ0),
/* VOU */
GPIO_FN(DV_CLKI),
GPIO_FN(DV_CLK),
GPIO_FN(DV_HSYNC),
GPIO_FN(DV_VSYNC),
GPIO_FN(DV_D15),
GPIO_FN(DV_D14),
GPIO_FN(DV_D13),
GPIO_FN(DV_D12),
GPIO_FN(DV_D11),
GPIO_FN(DV_D10),
GPIO_FN(DV_D9),
GPIO_FN(DV_D8),
GPIO_FN(DV_D7),
GPIO_FN(DV_D6),
GPIO_FN(DV_D5),
GPIO_FN(DV_D4),
GPIO_FN(DV_D3),
GPIO_FN(DV_D2),
GPIO_FN(DV_D1),
GPIO_FN(DV_D0),
/* CPG */
GPIO_FN(STATUS0),
GPIO_FN(PDSTATUS),
/* SIOF0 */
GPIO_FN(SIOF0_MCK),
GPIO_FN(SIOF0_SCK),
GPIO_FN(SIOF0_SYNC),
GPIO_FN(SIOF0_SS1),
GPIO_FN(SIOF0_SS2),
GPIO_FN(SIOF0_TXD),
GPIO_FN(SIOF0_RXD),
/* SIOF1 */
GPIO_FN(SIOF1_MCK),
GPIO_FN(SIOF1_SCK),
GPIO_FN(SIOF1_SYNC),
GPIO_FN(SIOF1_SS1),
GPIO_FN(SIOF1_SS2),
GPIO_FN(SIOF1_TXD),
GPIO_FN(SIOF1_RXD),
/* SIM */
GPIO_FN(SIM_D),
GPIO_FN(SIM_CLK),
GPIO_FN(SIM_RST),
/* TSIF */
GPIO_FN(TS_SDAT),
GPIO_FN(TS_SCK),
GPIO_FN(TS_SDEN),
GPIO_FN(TS_SPSYNC),
/* IRDA */
GPIO_FN(IRDA_IN),
GPIO_FN(IRDA_OUT),
/* TPU */
GPIO_FN(TPUTO),
/* FLCTL */
GPIO_FN(FCE),
GPIO_FN(NAF7),
GPIO_FN(NAF6),
GPIO_FN(NAF5),
GPIO_FN(NAF4),
GPIO_FN(NAF3),
GPIO_FN(NAF2),
GPIO_FN(NAF1),
GPIO_FN(NAF0),
GPIO_FN(FCDE),
GPIO_FN(FOE),
GPIO_FN(FSC),
GPIO_FN(FWE),
GPIO_FN(FRB),
/* KEYSC */
GPIO_FN(KEYIN0),
GPIO_FN(KEYIN1),
GPIO_FN(KEYIN2),
GPIO_FN(KEYIN3),
GPIO_FN(KEYIN4),
GPIO_FN(KEYOUT0),
GPIO_FN(KEYOUT1),
GPIO_FN(KEYOUT2),
GPIO_FN(KEYOUT3),
GPIO_FN(KEYOUT4_IN6),
GPIO_FN(KEYOUT5_IN5),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN,
VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN,
@ -1660,7 +1664,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
static struct pinmux_data_reg pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@ -1756,21 +1760,19 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
struct sh_pfc_soc_info sh7722_pinmux_info = {
const struct sh_pfc_soc_info sh7722_pinmux_info = {
.name = "sh7722_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PTA7,
.last_gpio = GPIO_FN_KEYOUT5_IN5,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

764
drivers/pinctrl/sh-pfc/pfc-sh7723.c
View file

@ -350,7 +350,7 @@ enum {
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
static const pinmux_enum_t pinmux_data[] = {
/* PTA GPIO */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
@ -923,7 +923,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN),
};
static struct pinmux_gpio pinmux_gpios[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@ -1139,379 +1139,383 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
/* SCIF0 */
PINMUX_GPIO(GPIO_FN_SCIF0_PTT_TXD, SCIF0_PTT_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_PTT_RXD, SCIF0_PTT_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_PTT_SCK, SCIF0_PTT_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_PTU_TXD, SCIF0_PTU_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_PTU_RXD, SCIF0_PTU_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_PTU_SCK, SCIF0_PTU_SCK_MARK),
/* SCIF1 */
PINMUX_GPIO(GPIO_FN_SCIF1_PTS_TXD, SCIF1_PTS_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_PTS_RXD, SCIF1_PTS_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_PTS_SCK, SCIF1_PTS_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_PTV_TXD, SCIF1_PTV_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_PTV_RXD, SCIF1_PTV_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_PTV_SCK, SCIF1_PTV_SCK_MARK),
/* SCIF2 */
PINMUX_GPIO(GPIO_FN_SCIF2_PTT_TXD, SCIF2_PTT_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_PTT_RXD, SCIF2_PTT_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_PTT_SCK, SCIF2_PTT_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_PTU_TXD, SCIF2_PTU_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_PTU_RXD, SCIF2_PTU_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_PTU_SCK, SCIF2_PTU_SCK_MARK),
/* SCIF3 */
PINMUX_GPIO(GPIO_FN_SCIF3_PTS_TXD, SCIF3_PTS_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RXD, SCIF3_PTS_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_PTS_SCK, SCIF3_PTS_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RTS, SCIF3_PTS_RTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_PTS_CTS, SCIF3_PTS_CTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_PTV_TXD, SCIF3_PTV_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RXD, SCIF3_PTV_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_PTV_SCK, SCIF3_PTV_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RTS, SCIF3_PTV_RTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_PTV_CTS, SCIF3_PTV_CTS_MARK),
/* SCIF4 */
PINMUX_GPIO(GPIO_FN_SCIF4_PTE_TXD, SCIF4_PTE_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_PTE_RXD, SCIF4_PTE_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_PTE_SCK, SCIF4_PTE_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_PTN_TXD, SCIF4_PTN_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_PTN_RXD, SCIF4_PTN_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_PTN_SCK, SCIF4_PTN_SCK_MARK),
/* SCIF5 */
PINMUX_GPIO(GPIO_FN_SCIF5_PTE_TXD, SCIF5_PTE_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF5_PTE_RXD, SCIF5_PTE_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF5_PTE_SCK, SCIF5_PTE_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF5_PTN_TXD, SCIF5_PTN_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF5_PTN_RXD, SCIF5_PTN_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF5_PTN_SCK, SCIF5_PTN_SCK_MARK),
/* CEU */
PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK),
PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK),
PINMUX_GPIO(GPIO_FN_VIO_CLK1, VIO_CLK1_MARK),
PINMUX_GPIO(GPIO_FN_VIO_VD1, VIO_VD1_MARK),
PINMUX_GPIO(GPIO_FN_VIO_HD1, VIO_HD1_MARK),
PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK),
PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK),
PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK),
PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK),
PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK),
/* LCDC */
PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK),
PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK),
PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK),
PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK),
PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK),
PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK),
PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK),
PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK),
PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK),
PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK),
PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK),
PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK),
PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK),
PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK),
PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK),
PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK),
PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK),
PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK),
PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK),
PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK),
PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK),
PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK),
PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK),
PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK),
PINMUX_GPIO(GPIO_FN_LCDLCLK_PTR, LCDLCLK_PTR_MARK),
PINMUX_GPIO(GPIO_FN_LCDLCLK_PTW, LCDLCLK_PTW_MARK),
/* Main LCD */
PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK),
PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK),
PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK),
PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK),
/* Main LCD - RGB Mode */
PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK),
PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK),
PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK),
/* Main LCD - SYS Mode */
PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK),
PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK),
PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK),
PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK),
/* IRQ */
PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
/* AUD */
PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
/* SDHI0 (PTD) */
PINMUX_GPIO(GPIO_FN_SDHI0CD_PTD, SDHI0CD_PTD_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0WP_PTD, SDHI0WP_PTD_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0D3_PTD, SDHI0D3_PTD_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0D2_PTD, SDHI0D2_PTD_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0D1_PTD, SDHI0D1_PTD_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0D0_PTD, SDHI0D0_PTD_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTD, SDHI0CMD_PTD_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTD, SDHI0CLK_PTD_MARK),
/* SDHI0 (PTS) */
PINMUX_GPIO(GPIO_FN_SDHI0CD_PTS, SDHI0CD_PTS_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0WP_PTS, SDHI0WP_PTS_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0D3_PTS, SDHI0D3_PTS_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0D2_PTS, SDHI0D2_PTS_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0D1_PTS, SDHI0D1_PTS_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0D0_PTS, SDHI0D0_PTS_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTS, SDHI0CMD_PTS_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTS, SDHI0CLK_PTS_MARK),
/* SDHI1 */
PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK),
/* SIUA */
PINMUX_GPIO(GPIO_FN_SIUAFCK, SIUAFCK_MARK),
PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK),
PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK),
PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK),
PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK),
PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK),
PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK),
PINMUX_GPIO(GPIO_FN_SIUAMCK, SIUAMCK_MARK),
PINMUX_GPIO(GPIO_FN_SIUAISPD, SIUAISPD_MARK),
PINMUX_GPIO(GPIO_FN_SIUAOSPD, SIUAOSPD_MARK),
/* SIUB */
PINMUX_GPIO(GPIO_FN_SIUBFCK, SIUBFCK_MARK),
PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK),
PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK),
PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK),
PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK),
PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK),
PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK),
PINMUX_GPIO(GPIO_FN_SIUBMCK, SIUBMCK_MARK),
/* IRDA */
PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK),
PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK),
/* VOU */
PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK),
PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK),
PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK),
PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK),
PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK),
PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK),
PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK),
PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK),
PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK),
PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK),
PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK),
PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK),
PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK),
PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK),
PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK),
PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK),
PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK),
/* KEYSC */
PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK),
PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK),
PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK),
PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK),
PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK),
/* MSIOF0 (PTF) */
PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TXD, MSIOF0_PTF_TXD_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RXD, MSIOF0_PTF_RXD_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_MCK, MSIOF0_PTF_MCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSYNC, MSIOF0_PTF_TSYNC_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSCK, MSIOF0_PTF_TSCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSYNC, MSIOF0_PTF_RSYNC_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSCK, MSIOF0_PTF_RSCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS1, MSIOF0_PTF_SS1_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS2, MSIOF0_PTF_SS2_MARK),
/* MSIOF0 (PTT+PTX) */
PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TXD, MSIOF0_PTT_TXD_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RXD, MSIOF0_PTT_RXD_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTX_MCK, MSIOF0_PTX_MCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSYNC, MSIOF0_PTT_TSYNC_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSCK, MSIOF0_PTT_TSCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSYNC, MSIOF0_PTT_RSYNC_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSCK, MSIOF0_PTT_RSCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS1, MSIOF0_PTT_SS1_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS2, MSIOF0_PTT_SS2_MARK),
/* MSIOF1 */
PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK),
/* TSIF */
PINMUX_GPIO(GPIO_FN_TS0_SDAT, TS0_SDAT_MARK),
PINMUX_GPIO(GPIO_FN_TS0_SCK, TS0_SCK_MARK),
PINMUX_GPIO(GPIO_FN_TS0_SDEN, TS0_SDEN_MARK),
PINMUX_GPIO(GPIO_FN_TS0_SPSYNC, TS0_SPSYNC_MARK),
/* FLCTL */
PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK),
PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK),
PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK),
PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK),
PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK),
PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK),
PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK),
PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK),
PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK),
PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK),
PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK),
PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
/* DMAC */
PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
/* ADC */
PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK),
PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK),
PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK),
PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK),
PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
/* CPG */
PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK),
/* TPU */
PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK),
PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK),
PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK),
PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK),
/* BSC */
PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK),
PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK),
PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK),
PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK),
PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK),
/* ATAPI */
PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK),
PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK),
PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK),
PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK),
PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK),
PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK),
PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK),
PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK),
PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK),
PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK),
PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK),
PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK),
PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK),
PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK),
PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK),
PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK),
PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK),
PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK),
PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK),
PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK),
PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK),
PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK),
PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK),
PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK),
PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK),
PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK),
PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK),
PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK),
PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK),
PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
/* SCIF0 */
GPIO_FN(SCIF0_PTT_TXD),
GPIO_FN(SCIF0_PTT_RXD),
GPIO_FN(SCIF0_PTT_SCK),
GPIO_FN(SCIF0_PTU_TXD),
GPIO_FN(SCIF0_PTU_RXD),
GPIO_FN(SCIF0_PTU_SCK),
/* SCIF1 */
GPIO_FN(SCIF1_PTS_TXD),
GPIO_FN(SCIF1_PTS_RXD),
GPIO_FN(SCIF1_PTS_SCK),
GPIO_FN(SCIF1_PTV_TXD),
GPIO_FN(SCIF1_PTV_RXD),
GPIO_FN(SCIF1_PTV_SCK),
/* SCIF2 */
GPIO_FN(SCIF2_PTT_TXD),
GPIO_FN(SCIF2_PTT_RXD),
GPIO_FN(SCIF2_PTT_SCK),
GPIO_FN(SCIF2_PTU_TXD),
GPIO_FN(SCIF2_PTU_RXD),
GPIO_FN(SCIF2_PTU_SCK),
/* SCIF3 */
GPIO_FN(SCIF3_PTS_TXD),
GPIO_FN(SCIF3_PTS_RXD),
GPIO_FN(SCIF3_PTS_SCK),
GPIO_FN(SCIF3_PTS_RTS),
GPIO_FN(SCIF3_PTS_CTS),
GPIO_FN(SCIF3_PTV_TXD),
GPIO_FN(SCIF3_PTV_RXD),
GPIO_FN(SCIF3_PTV_SCK),
GPIO_FN(SCIF3_PTV_RTS),
GPIO_FN(SCIF3_PTV_CTS),
/* SCIF4 */
GPIO_FN(SCIF4_PTE_TXD),
GPIO_FN(SCIF4_PTE_RXD),
GPIO_FN(SCIF4_PTE_SCK),
GPIO_FN(SCIF4_PTN_TXD),
GPIO_FN(SCIF4_PTN_RXD),
GPIO_FN(SCIF4_PTN_SCK),
/* SCIF5 */
GPIO_FN(SCIF5_PTE_TXD),
GPIO_FN(SCIF5_PTE_RXD),
GPIO_FN(SCIF5_PTE_SCK),
GPIO_FN(SCIF5_PTN_TXD),
GPIO_FN(SCIF5_PTN_RXD),
GPIO_FN(SCIF5_PTN_SCK),
/* CEU */
GPIO_FN(VIO_D15),
GPIO_FN(VIO_D14),
GPIO_FN(VIO_D13),
GPIO_FN(VIO_D12),
GPIO_FN(VIO_D11),
GPIO_FN(VIO_D10),
GPIO_FN(VIO_D9),
GPIO_FN(VIO_D8),
GPIO_FN(VIO_D7),
GPIO_FN(VIO_D6),
GPIO_FN(VIO_D5),
GPIO_FN(VIO_D4),
GPIO_FN(VIO_D3),
GPIO_FN(VIO_D2),
GPIO_FN(VIO_D1),
GPIO_FN(VIO_D0),
GPIO_FN(VIO_CLK1),
GPIO_FN(VIO_VD1),
GPIO_FN(VIO_HD1),
GPIO_FN(VIO_FLD),
GPIO_FN(VIO_CKO),
GPIO_FN(VIO_VD2),
GPIO_FN(VIO_HD2),
GPIO_FN(VIO_CLK2),
/* LCDC */
GPIO_FN(LCDD23),
GPIO_FN(LCDD22),
GPIO_FN(LCDD21),
GPIO_FN(LCDD20),
GPIO_FN(LCDD19),
GPIO_FN(LCDD18),
GPIO_FN(LCDD17),
GPIO_FN(LCDD16),
GPIO_FN(LCDD15),
GPIO_FN(LCDD14),
GPIO_FN(LCDD13),
GPIO_FN(LCDD12),
GPIO_FN(LCDD11),
GPIO_FN(LCDD10),
GPIO_FN(LCDD9),
GPIO_FN(LCDD8),
GPIO_FN(LCDD7),
GPIO_FN(LCDD6),
GPIO_FN(LCDD5),
GPIO_FN(LCDD4),
GPIO_FN(LCDD3),
GPIO_FN(LCDD2),
GPIO_FN(LCDD1),
GPIO_FN(LCDD0),
GPIO_FN(LCDLCLK_PTR),
GPIO_FN(LCDLCLK_PTW),
/* Main LCD */
GPIO_FN(LCDDON),
GPIO_FN(LCDVCPWC),
GPIO_FN(LCDVEPWC),
GPIO_FN(LCDVSYN),
/* Main LCD - RGB Mode */
GPIO_FN(LCDDCK),
GPIO_FN(LCDHSYN),
GPIO_FN(LCDDISP),
/* Main LCD - SYS Mode */
GPIO_FN(LCDRS),
GPIO_FN(LCDCS),
GPIO_FN(LCDWR),
GPIO_FN(LCDRD),
/* IRQ */
GPIO_FN(IRQ0),
GPIO_FN(IRQ1),
GPIO_FN(IRQ2),
GPIO_FN(IRQ3),
GPIO_FN(IRQ4),
GPIO_FN(IRQ5),
GPIO_FN(IRQ6),
GPIO_FN(IRQ7),
/* AUD */
GPIO_FN(AUDCK),
GPIO_FN(AUDSYNC),
GPIO_FN(AUDATA3),
GPIO_FN(AUDATA2),
GPIO_FN(AUDATA1),
GPIO_FN(AUDATA0),
/* SDHI0 (PTD) */
GPIO_FN(SDHI0CD_PTD),
GPIO_FN(SDHI0WP_PTD),
GPIO_FN(SDHI0D3_PTD),
GPIO_FN(SDHI0D2_PTD),
GPIO_FN(SDHI0D1_PTD),
GPIO_FN(SDHI0D0_PTD),
GPIO_FN(SDHI0CMD_PTD),
GPIO_FN(SDHI0CLK_PTD),
/* SDHI0 (PTS) */
GPIO_FN(SDHI0CD_PTS),
GPIO_FN(SDHI0WP_PTS),
GPIO_FN(SDHI0D3_PTS),
GPIO_FN(SDHI0D2_PTS),
GPIO_FN(SDHI0D1_PTS),
GPIO_FN(SDHI0D0_PTS),
GPIO_FN(SDHI0CMD_PTS),
GPIO_FN(SDHI0CLK_PTS),
/* SDHI1 */
GPIO_FN(SDHI1CD),
GPIO_FN(SDHI1WP),
GPIO_FN(SDHI1D3),
GPIO_FN(SDHI1D2),
GPIO_FN(SDHI1D1),
GPIO_FN(SDHI1D0),
GPIO_FN(SDHI1CMD),
GPIO_FN(SDHI1CLK),
/* SIUA */
GPIO_FN(SIUAFCK),
GPIO_FN(SIUAILR),
GPIO_FN(SIUAIBT),
GPIO_FN(SIUAISLD),
GPIO_FN(SIUAOLR),
GPIO_FN(SIUAOBT),
GPIO_FN(SIUAOSLD),
GPIO_FN(SIUAMCK),
GPIO_FN(SIUAISPD),
GPIO_FN(SIUAOSPD),
/* SIUB */
GPIO_FN(SIUBFCK),
GPIO_FN(SIUBILR),
GPIO_FN(SIUBIBT),
GPIO_FN(SIUBISLD),
GPIO_FN(SIUBOLR),
GPIO_FN(SIUBOBT),
GPIO_FN(SIUBOSLD),
GPIO_FN(SIUBMCK),
/* IRDA */
GPIO_FN(IRDA_IN),
GPIO_FN(IRDA_OUT),
/* VOU */
GPIO_FN(DV_CLKI),
GPIO_FN(DV_CLK),
GPIO_FN(DV_HSYNC),
GPIO_FN(DV_VSYNC),
GPIO_FN(DV_D15),
GPIO_FN(DV_D14),
GPIO_FN(DV_D13),
GPIO_FN(DV_D12),
GPIO_FN(DV_D11),
GPIO_FN(DV_D10),
GPIO_FN(DV_D9),
GPIO_FN(DV_D8),
GPIO_FN(DV_D7),
GPIO_FN(DV_D6),
GPIO_FN(DV_D5),
GPIO_FN(DV_D4),
GPIO_FN(DV_D3),
GPIO_FN(DV_D2),
GPIO_FN(DV_D1),
GPIO_FN(DV_D0),
/* KEYSC */
GPIO_FN(KEYIN0),
GPIO_FN(KEYIN1),
GPIO_FN(KEYIN2),
GPIO_FN(KEYIN3),
GPIO_FN(KEYIN4),
GPIO_FN(KEYOUT0),
GPIO_FN(KEYOUT1),
GPIO_FN(KEYOUT2),
GPIO_FN(KEYOUT3),
GPIO_FN(KEYOUT4_IN6),
GPIO_FN(KEYOUT5_IN5),
/* MSIOF0 (PTF) */
GPIO_FN(MSIOF0_PTF_TXD),
GPIO_FN(MSIOF0_PTF_RXD),
GPIO_FN(MSIOF0_PTF_MCK),
GPIO_FN(MSIOF0_PTF_TSYNC),
GPIO_FN(MSIOF0_PTF_TSCK),
GPIO_FN(MSIOF0_PTF_RSYNC),
GPIO_FN(MSIOF0_PTF_RSCK),
GPIO_FN(MSIOF0_PTF_SS1),
GPIO_FN(MSIOF0_PTF_SS2),
/* MSIOF0 (PTT+PTX) */
GPIO_FN(MSIOF0_PTT_TXD),
GPIO_FN(MSIOF0_PTT_RXD),
GPIO_FN(MSIOF0_PTX_MCK),
GPIO_FN(MSIOF0_PTT_TSYNC),
GPIO_FN(MSIOF0_PTT_TSCK),
GPIO_FN(MSIOF0_PTT_RSYNC),
GPIO_FN(MSIOF0_PTT_RSCK),
GPIO_FN(MSIOF0_PTT_SS1),
GPIO_FN(MSIOF0_PTT_SS2),
/* MSIOF1 */
GPIO_FN(MSIOF1_TXD),
GPIO_FN(MSIOF1_RXD),
GPIO_FN(MSIOF1_MCK),
GPIO_FN(MSIOF1_TSYNC),
GPIO_FN(MSIOF1_TSCK),
GPIO_FN(MSIOF1_RSYNC),
GPIO_FN(MSIOF1_RSCK),
GPIO_FN(MSIOF1_SS1),
GPIO_FN(MSIOF1_SS2),
/* TSIF */
GPIO_FN(TS0_SDAT),
GPIO_FN(TS0_SCK),
GPIO_FN(TS0_SDEN),
GPIO_FN(TS0_SPSYNC),
/* FLCTL */
GPIO_FN(FCE),
GPIO_FN(NAF7),
GPIO_FN(NAF6),
GPIO_FN(NAF5),
GPIO_FN(NAF4),
GPIO_FN(NAF3),
GPIO_FN(NAF2),
GPIO_FN(NAF1),
GPIO_FN(NAF0),
GPIO_FN(FCDE),
GPIO_FN(FOE),
GPIO_FN(FSC),
GPIO_FN(FWE),
GPIO_FN(FRB),
/* DMAC */
GPIO_FN(DACK1),
GPIO_FN(DREQ1),
GPIO_FN(DACK0),
GPIO_FN(DREQ0),
/* ADC */
GPIO_FN(AN3),
GPIO_FN(AN2),
GPIO_FN(AN1),
GPIO_FN(AN0),
GPIO_FN(ADTRG),
/* CPG */
GPIO_FN(STATUS0),
GPIO_FN(PDSTATUS),
/* TPU */
GPIO_FN(TPUTO0),
GPIO_FN(TPUTO1),
GPIO_FN(TPUTO2),
GPIO_FN(TPUTO3),
/* BSC */
GPIO_FN(D31),
GPIO_FN(D30),
GPIO_FN(D29),
GPIO_FN(D28),
GPIO_FN(D27),
GPIO_FN(D26),
GPIO_FN(D25),
GPIO_FN(D24),
GPIO_FN(D23),
GPIO_FN(D22),
GPIO_FN(D21),
GPIO_FN(D20),
GPIO_FN(D19),
GPIO_FN(D18),
GPIO_FN(D17),
GPIO_FN(D16),
GPIO_FN(IOIS16),
GPIO_FN(WAIT),
GPIO_FN(BS),
GPIO_FN(A25),
GPIO_FN(A24),
GPIO_FN(A23),
GPIO_FN(A22),
GPIO_FN(CS6B_CE1B),
GPIO_FN(CS6A_CE2B),
GPIO_FN(CS5B_CE1A),
GPIO_FN(CS5A_CE2A),
GPIO_FN(WE3_ICIOWR),
GPIO_FN(WE2_ICIORD),
/* ATAPI */
GPIO_FN(IDED15),
GPIO_FN(IDED14),
GPIO_FN(IDED13),
GPIO_FN(IDED12),
GPIO_FN(IDED11),
GPIO_FN(IDED10),
GPIO_FN(IDED9),
GPIO_FN(IDED8),
GPIO_FN(IDED7),
GPIO_FN(IDED6),
GPIO_FN(IDED5),
GPIO_FN(IDED4),
GPIO_FN(IDED3),
GPIO_FN(IDED2),
GPIO_FN(IDED1),
GPIO_FN(IDED0),
GPIO_FN(DIRECTION),
GPIO_FN(EXBUF_ENB),
GPIO_FN(IDERST),
GPIO_FN(IODACK),
GPIO_FN(IODREQ),
GPIO_FN(IDEIORDY),
GPIO_FN(IDEINT),
GPIO_FN(IDEIOWR),
GPIO_FN(IDEIORD),
GPIO_FN(IDECS1),
GPIO_FN(IDECS0),
GPIO_FN(IDEA2),
GPIO_FN(IDEA1),
GPIO_FN(IDEA0),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
PTA7_FN, PTA7_OUT, 0, PTA7_IN,
PTA6_FN, PTA6_OUT, 0, PTA6_IN,
@ -1785,7 +1789,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
static struct pinmux_data_reg pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@ -1881,20 +1885,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
struct sh_pfc_soc_info sh7723_pinmux_info = {
const struct sh_pfc_soc_info sh7723_pinmux_info = {
.name = "sh7723_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PTA7,
.last_gpio = GPIO_FN_IDEA0,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

750
drivers/pinctrl/sh-pfc/pfc-sh7724.c
View file

@ -572,7 +572,7 @@ enum {
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
static const pinmux_enum_t pinmux_data[] = {
/* PTA GPIO */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
@ -1192,7 +1192,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN),
};
static struct pinmux_gpio pinmux_gpios[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@ -1418,372 +1418,376 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
/* BSC */
PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK),
PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK),
PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK),
PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK),
PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK),
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
/* KEYSC */
PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK),
PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK),
PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK),
PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK),
PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK),
PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK),
PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK),
/* ATAPI */
PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK),
PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK),
PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK),
PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK),
PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK),
PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK),
PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK),
PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK),
PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK),
PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK),
PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK),
PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK),
PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK),
PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK),
PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK),
PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK),
PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK),
PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK),
PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK),
PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK),
PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK),
PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK),
PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK),
PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK),
PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK),
PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK),
PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK),
PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK),
PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK),
PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK),
/* TPU */
PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK),
PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK),
PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK),
PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK),
PINMUX_GPIO(GPIO_FN_TPUTI3, TPUTI3_MARK),
PINMUX_GPIO(GPIO_FN_TPUTI2, TPUTI2_MARK),
/* LCDC */
PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK),
PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK),
PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK),
PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK),
PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK),
PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK),
PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK),
PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK),
PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK),
PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK),
PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK),
PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK),
PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK),
PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK),
PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK),
PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK),
PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK),
PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK),
PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK),
PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK),
PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK),
PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK),
PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK),
PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK),
PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK),
PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK),
PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK),
PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK),
PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK),
PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK),
PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK),
PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK),
PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK),
PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK),
PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK),
PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK),
/* SCIF0 */
PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
/* SCIF1 */
PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
/* SCIF2 */
PINMUX_GPIO(GPIO_FN_SCIF2_L_TXD, SCIF2_L_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_L_SCK, SCIF2_L_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_L_RXD, SCIF2_L_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_V_TXD, SCIF2_V_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_V_SCK, SCIF2_V_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_V_RXD, SCIF2_V_RXD_MARK),
/* SCIF3 */
PINMUX_GPIO(GPIO_FN_SCIF3_V_SCK, SCIF3_V_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_V_RXD, SCIF3_V_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_V_TXD, SCIF3_V_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_V_CTS, SCIF3_V_CTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_V_RTS, SCIF3_V_RTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_I_SCK, SCIF3_I_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_I_RXD, SCIF3_I_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_I_TXD, SCIF3_I_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_I_CTS, SCIF3_I_CTS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_I_RTS, SCIF3_I_RTS_MARK),
/* SCIF4 */
PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
/* SCIF5 */
PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
/* FSI */
PINMUX_GPIO(GPIO_FN_FSIMCKB, FSIMCKB_MARK),
PINMUX_GPIO(GPIO_FN_FSIMCKA, FSIMCKA_MARK),
PINMUX_GPIO(GPIO_FN_FSIOASD, FSIOASD_MARK),
PINMUX_GPIO(GPIO_FN_FSIIABCK, FSIIABCK_MARK),
PINMUX_GPIO(GPIO_FN_FSIIALRCK, FSIIALRCK_MARK),
PINMUX_GPIO(GPIO_FN_FSIOABCK, FSIOABCK_MARK),
PINMUX_GPIO(GPIO_FN_FSIOALRCK, FSIOALRCK_MARK),
PINMUX_GPIO(GPIO_FN_CLKAUDIOAO, CLKAUDIOAO_MARK),
PINMUX_GPIO(GPIO_FN_FSIIBSD, FSIIBSD_MARK),
PINMUX_GPIO(GPIO_FN_FSIOBSD, FSIOBSD_MARK),
PINMUX_GPIO(GPIO_FN_FSIIBBCK, FSIIBBCK_MARK),
PINMUX_GPIO(GPIO_FN_FSIIBLRCK, FSIIBLRCK_MARK),
PINMUX_GPIO(GPIO_FN_FSIOBBCK, FSIOBBCK_MARK),
PINMUX_GPIO(GPIO_FN_FSIOBLRCK, FSIOBLRCK_MARK),
PINMUX_GPIO(GPIO_FN_CLKAUDIOBO, CLKAUDIOBO_MARK),
PINMUX_GPIO(GPIO_FN_FSIIASD, FSIIASD_MARK),
/* AUD */
PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
/* VIO */
PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK),
/* VIO0 */
PINMUX_GPIO(GPIO_FN_VIO0_D15, VIO0_D15_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D14, VIO0_D14_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D13, VIO0_D13_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D12, VIO0_D12_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D11, VIO0_D11_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D10, VIO0_D10_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D9, VIO0_D9_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D8, VIO0_D8_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D7, VIO0_D7_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D6, VIO0_D6_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D5, VIO0_D5_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D4, VIO0_D4_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D3, VIO0_D3_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D2, VIO0_D2_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D1, VIO0_D1_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_D0, VIO0_D0_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_VD, VIO0_VD_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_CLK, VIO0_CLK_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_FLD, VIO0_FLD_MARK),
PINMUX_GPIO(GPIO_FN_VIO0_HD, VIO0_HD_MARK),
/* VIO1 */
PINMUX_GPIO(GPIO_FN_VIO1_D7, VIO1_D7_MARK),
PINMUX_GPIO(GPIO_FN_VIO1_D6, VIO1_D6_MARK),
PINMUX_GPIO(GPIO_FN_VIO1_D5, VIO1_D5_MARK),
PINMUX_GPIO(GPIO_FN_VIO1_D4, VIO1_D4_MARK),
PINMUX_GPIO(GPIO_FN_VIO1_D3, VIO1_D3_MARK),
PINMUX_GPIO(GPIO_FN_VIO1_D2, VIO1_D2_MARK),
PINMUX_GPIO(GPIO_FN_VIO1_D1, VIO1_D1_MARK),
PINMUX_GPIO(GPIO_FN_VIO1_D0, VIO1_D0_MARK),
PINMUX_GPIO(GPIO_FN_VIO1_FLD, VIO1_FLD_MARK),
PINMUX_GPIO(GPIO_FN_VIO1_HD, VIO1_HD_MARK),
PINMUX_GPIO(GPIO_FN_VIO1_VD, VIO1_VD_MARK),
PINMUX_GPIO(GPIO_FN_VIO1_CLK, VIO1_CLK_MARK),
/* Eth */
PINMUX_GPIO(GPIO_FN_RMII_RXD0, RMII_RXD0_MARK),
PINMUX_GPIO(GPIO_FN_RMII_RXD1, RMII_RXD1_MARK),
PINMUX_GPIO(GPIO_FN_RMII_TXD0, RMII_TXD0_MARK),
PINMUX_GPIO(GPIO_FN_RMII_TXD1, RMII_TXD1_MARK),
PINMUX_GPIO(GPIO_FN_RMII_REF_CLK, RMII_REF_CLK_MARK),
PINMUX_GPIO(GPIO_FN_RMII_TX_EN, RMII_TX_EN_MARK),
PINMUX_GPIO(GPIO_FN_RMII_RX_ER, RMII_RX_ER_MARK),
PINMUX_GPIO(GPIO_FN_RMII_CRS_DV, RMII_CRS_DV_MARK),
PINMUX_GPIO(GPIO_FN_LNKSTA, LNKSTA_MARK),
PINMUX_GPIO(GPIO_FN_MDIO, MDIO_MARK),
PINMUX_GPIO(GPIO_FN_MDC, MDC_MARK),
/* System */
PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK),
PINMUX_GPIO(GPIO_FN_STATUS2, STATUS2_MARK),
PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
/* VOU */
PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK),
PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK),
PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK),
PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK),
PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK),
PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK),
PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK),
PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK),
PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK),
PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK),
PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK),
PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK),
PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK),
PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK),
PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK),
PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK),
PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK),
PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
/* MSIOF0 */
PINMUX_GPIO(GPIO_FN_MSIOF0_RXD, MSIOF0_RXD_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_TXD, MSIOF0_TXD_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_MCK, MSIOF0_MCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_TSCK, MSIOF0_TSCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_SS1, MSIOF0_SS1_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_SS2, MSIOF0_SS2_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_TSYNC, MSIOF0_TSYNC_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_RSCK, MSIOF0_RSCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF0_RSYNC, MSIOF0_RSYNC_MARK),
/* MSIOF1 */
PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK),
PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK),
/* DMAC */
PINMUX_GPIO(GPIO_FN_DMAC_DACK0, DMAC_DACK0_MARK),
PINMUX_GPIO(GPIO_FN_DMAC_DREQ0, DMAC_DREQ0_MARK),
PINMUX_GPIO(GPIO_FN_DMAC_DACK1, DMAC_DACK1_MARK),
PINMUX_GPIO(GPIO_FN_DMAC_DREQ1, DMAC_DREQ1_MARK),
/* SDHI0 */
PINMUX_GPIO(GPIO_FN_SDHI0CD, SDHI0CD_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0WP, SDHI0WP_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0CMD, SDHI0CMD_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0CLK, SDHI0CLK_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0D3, SDHI0D3_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0D2, SDHI0D2_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0D1, SDHI0D1_MARK),
PINMUX_GPIO(GPIO_FN_SDHI0D0, SDHI0D0_MARK),
/* SDHI1 */
PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK),
PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK),
/* MMC */
PINMUX_GPIO(GPIO_FN_MMC_D7, MMC_D7_MARK),
PINMUX_GPIO(GPIO_FN_MMC_D6, MMC_D6_MARK),
PINMUX_GPIO(GPIO_FN_MMC_D5, MMC_D5_MARK),
PINMUX_GPIO(GPIO_FN_MMC_D4, MMC_D4_MARK),
PINMUX_GPIO(GPIO_FN_MMC_D3, MMC_D3_MARK),
PINMUX_GPIO(GPIO_FN_MMC_D2, MMC_D2_MARK),
PINMUX_GPIO(GPIO_FN_MMC_D1, MMC_D1_MARK),
PINMUX_GPIO(GPIO_FN_MMC_D0, MMC_D0_MARK),
PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK),
PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK),
/* IrDA */
PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK),
PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK),
/* TSIF */
PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDAT, TSIF_TS0_SDAT_MARK),
PINMUX_GPIO(GPIO_FN_TSIF_TS0_SCK, TSIF_TS0_SCK_MARK),
PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDEN, TSIF_TS0_SDEN_MARK),
PINMUX_GPIO(GPIO_FN_TSIF_TS0_SPSYNC, TSIF_TS0_SPSYNC_MARK),
/* IRQ */
PINMUX_GPIO(GPIO_FN_INTC_IRQ7, INTC_IRQ7_MARK),
PINMUX_GPIO(GPIO_FN_INTC_IRQ6, INTC_IRQ6_MARK),
PINMUX_GPIO(GPIO_FN_INTC_IRQ5, INTC_IRQ5_MARK),
PINMUX_GPIO(GPIO_FN_INTC_IRQ4, INTC_IRQ4_MARK),
PINMUX_GPIO(GPIO_FN_INTC_IRQ3, INTC_IRQ3_MARK),
PINMUX_GPIO(GPIO_FN_INTC_IRQ2, INTC_IRQ2_MARK),
PINMUX_GPIO(GPIO_FN_INTC_IRQ1, INTC_IRQ1_MARK),
PINMUX_GPIO(GPIO_FN_INTC_IRQ0, INTC_IRQ0_MARK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
/* BSC */
GPIO_FN(D31),
GPIO_FN(D30),
GPIO_FN(D29),
GPIO_FN(D28),
GPIO_FN(D27),
GPIO_FN(D26),
GPIO_FN(D25),
GPIO_FN(D24),
GPIO_FN(D23),
GPIO_FN(D22),
GPIO_FN(D21),
GPIO_FN(D20),
GPIO_FN(D19),
GPIO_FN(D18),
GPIO_FN(D17),
GPIO_FN(D16),
GPIO_FN(D15),
GPIO_FN(D14),
GPIO_FN(D13),
GPIO_FN(D12),
GPIO_FN(D11),
GPIO_FN(D10),
GPIO_FN(D9),
GPIO_FN(D8),
GPIO_FN(D7),
GPIO_FN(D6),
GPIO_FN(D5),
GPIO_FN(D4),
GPIO_FN(D3),
GPIO_FN(D2),
GPIO_FN(D1),
GPIO_FN(D0),
GPIO_FN(A25),
GPIO_FN(A24),
GPIO_FN(A23),
GPIO_FN(A22),
GPIO_FN(CS6B_CE1B),
GPIO_FN(CS6A_CE2B),
GPIO_FN(CS5B_CE1A),
GPIO_FN(CS5A_CE2A),
GPIO_FN(WE3_ICIOWR),
GPIO_FN(WE2_ICIORD),
GPIO_FN(IOIS16),
GPIO_FN(WAIT),
GPIO_FN(BS),
/* KEYSC */
GPIO_FN(KEYOUT5_IN5),
GPIO_FN(KEYOUT4_IN6),
GPIO_FN(KEYIN4),
GPIO_FN(KEYIN3),
GPIO_FN(KEYIN2),
GPIO_FN(KEYIN1),
GPIO_FN(KEYIN0),
GPIO_FN(KEYOUT3),
GPIO_FN(KEYOUT2),
GPIO_FN(KEYOUT1),
GPIO_FN(KEYOUT0),
/* ATAPI */
GPIO_FN(IDED15),
GPIO_FN(IDED14),
GPIO_FN(IDED13),
GPIO_FN(IDED12),
GPIO_FN(IDED11),
GPIO_FN(IDED10),
GPIO_FN(IDED9),
GPIO_FN(IDED8),
GPIO_FN(IDED7),
GPIO_FN(IDED6),
GPIO_FN(IDED5),
GPIO_FN(IDED4),
GPIO_FN(IDED3),
GPIO_FN(IDED2),
GPIO_FN(IDED1),
GPIO_FN(IDED0),
GPIO_FN(IDEA2),
GPIO_FN(IDEA1),
GPIO_FN(IDEA0),
GPIO_FN(IDEIOWR),
GPIO_FN(IODREQ),
GPIO_FN(IDECS0),
GPIO_FN(IDECS1),
GPIO_FN(IDEIORD),
GPIO_FN(DIRECTION),
GPIO_FN(EXBUF_ENB),
GPIO_FN(IDERST),
GPIO_FN(IODACK),
GPIO_FN(IDEINT),
GPIO_FN(IDEIORDY),
/* TPU */
GPIO_FN(TPUTO3),
GPIO_FN(TPUTO2),
GPIO_FN(TPUTO1),
GPIO_FN(TPUTO0),
GPIO_FN(TPUTI3),
GPIO_FN(TPUTI2),
/* LCDC */
GPIO_FN(LCDD23),
GPIO_FN(LCDD22),
GPIO_FN(LCDD21),
GPIO_FN(LCDD20),
GPIO_FN(LCDD19),
GPIO_FN(LCDD18),
GPIO_FN(LCDD17),
GPIO_FN(LCDD16),
GPIO_FN(LCDD15),
GPIO_FN(LCDD14),
GPIO_FN(LCDD13),
GPIO_FN(LCDD12),
GPIO_FN(LCDD11),
GPIO_FN(LCDD10),
GPIO_FN(LCDD9),
GPIO_FN(LCDD8),
GPIO_FN(LCDD7),
GPIO_FN(LCDD6),
GPIO_FN(LCDD5),
GPIO_FN(LCDD4),
GPIO_FN(LCDD3),
GPIO_FN(LCDD2),
GPIO_FN(LCDD1),
GPIO_FN(LCDD0),
GPIO_FN(LCDVSYN),
GPIO_FN(LCDDISP),
GPIO_FN(LCDRS),
GPIO_FN(LCDHSYN),
GPIO_FN(LCDCS),
GPIO_FN(LCDDON),
GPIO_FN(LCDDCK),
GPIO_FN(LCDWR),
GPIO_FN(LCDVEPWC),
GPIO_FN(LCDVCPWC),
GPIO_FN(LCDRD),
GPIO_FN(LCDLCLK),
/* SCIF0 */
GPIO_FN(SCIF0_TXD),
GPIO_FN(SCIF0_RXD),
GPIO_FN(SCIF0_SCK),
/* SCIF1 */
GPIO_FN(SCIF1_SCK),
GPIO_FN(SCIF1_RXD),
GPIO_FN(SCIF1_TXD),
/* SCIF2 */
GPIO_FN(SCIF2_L_TXD),
GPIO_FN(SCIF2_L_SCK),
GPIO_FN(SCIF2_L_RXD),
GPIO_FN(SCIF2_V_TXD),
GPIO_FN(SCIF2_V_SCK),
GPIO_FN(SCIF2_V_RXD),
/* SCIF3 */
GPIO_FN(SCIF3_V_SCK),
GPIO_FN(SCIF3_V_RXD),
GPIO_FN(SCIF3_V_TXD),
GPIO_FN(SCIF3_V_CTS),
GPIO_FN(SCIF3_V_RTS),
GPIO_FN(SCIF3_I_SCK),
GPIO_FN(SCIF3_I_RXD),
GPIO_FN(SCIF3_I_TXD),
GPIO_FN(SCIF3_I_CTS),
GPIO_FN(SCIF3_I_RTS),
/* SCIF4 */
GPIO_FN(SCIF4_SCK),
GPIO_FN(SCIF4_RXD),
GPIO_FN(SCIF4_TXD),
/* SCIF5 */
GPIO_FN(SCIF5_SCK),
GPIO_FN(SCIF5_RXD),
GPIO_FN(SCIF5_TXD),
/* FSI */
GPIO_FN(FSIMCKB),
GPIO_FN(FSIMCKA),
GPIO_FN(FSIOASD),
GPIO_FN(FSIIABCK),
GPIO_FN(FSIIALRCK),
GPIO_FN(FSIOABCK),
GPIO_FN(FSIOALRCK),
GPIO_FN(CLKAUDIOAO),
GPIO_FN(FSIIBSD),
GPIO_FN(FSIOBSD),
GPIO_FN(FSIIBBCK),
GPIO_FN(FSIIBLRCK),
GPIO_FN(FSIOBBCK),
GPIO_FN(FSIOBLRCK),
GPIO_FN(CLKAUDIOBO),
GPIO_FN(FSIIASD),
/* AUD */
GPIO_FN(AUDCK),
GPIO_FN(AUDSYNC),
GPIO_FN(AUDATA3),
GPIO_FN(AUDATA2),
GPIO_FN(AUDATA1),
GPIO_FN(AUDATA0),
/* VIO */
GPIO_FN(VIO_CKO),
/* VIO0 */
GPIO_FN(VIO0_D15),
GPIO_FN(VIO0_D14),
GPIO_FN(VIO0_D13),
GPIO_FN(VIO0_D12),
GPIO_FN(VIO0_D11),
GPIO_FN(VIO0_D10),
GPIO_FN(VIO0_D9),
GPIO_FN(VIO0_D8),
GPIO_FN(VIO0_D7),
GPIO_FN(VIO0_D6),
GPIO_FN(VIO0_D5),
GPIO_FN(VIO0_D4),
GPIO_FN(VIO0_D3),
GPIO_FN(VIO0_D2),
GPIO_FN(VIO0_D1),
GPIO_FN(VIO0_D0),
GPIO_FN(VIO0_VD),
GPIO_FN(VIO0_CLK),
GPIO_FN(VIO0_FLD),
GPIO_FN(VIO0_HD),
/* VIO1 */
GPIO_FN(VIO1_D7),
GPIO_FN(VIO1_D6),
GPIO_FN(VIO1_D5),
GPIO_FN(VIO1_D4),
GPIO_FN(VIO1_D3),
GPIO_FN(VIO1_D2),
GPIO_FN(VIO1_D1),
GPIO_FN(VIO1_D0),
GPIO_FN(VIO1_FLD),
GPIO_FN(VIO1_HD),
GPIO_FN(VIO1_VD),
GPIO_FN(VIO1_CLK),
/* Eth */
GPIO_FN(RMII_RXD0),
GPIO_FN(RMII_RXD1),
GPIO_FN(RMII_TXD0),
GPIO_FN(RMII_TXD1),
GPIO_FN(RMII_REF_CLK),
GPIO_FN(RMII_TX_EN),
GPIO_FN(RMII_RX_ER),
GPIO_FN(RMII_CRS_DV),
GPIO_FN(LNKSTA),
GPIO_FN(MDIO),
GPIO_FN(MDC),
/* System */
GPIO_FN(PDSTATUS),
GPIO_FN(STATUS2),
GPIO_FN(STATUS0),
/* VOU */
GPIO_FN(DV_D15),
GPIO_FN(DV_D14),
GPIO_FN(DV_D13),
GPIO_FN(DV_D12),
GPIO_FN(DV_D11),
GPIO_FN(DV_D10),
GPIO_FN(DV_D9),
GPIO_FN(DV_D8),
GPIO_FN(DV_D7),
GPIO_FN(DV_D6),
GPIO_FN(DV_D5),
GPIO_FN(DV_D4),
GPIO_FN(DV_D3),
GPIO_FN(DV_D2),
GPIO_FN(DV_D1),
GPIO_FN(DV_D0),
GPIO_FN(DV_CLKI),
GPIO_FN(DV_CLK),
GPIO_FN(DV_VSYNC),
GPIO_FN(DV_HSYNC),
/* MSIOF0 */
GPIO_FN(MSIOF0_RXD),
GPIO_FN(MSIOF0_TXD),
GPIO_FN(MSIOF0_MCK),
GPIO_FN(MSIOF0_TSCK),
GPIO_FN(MSIOF0_SS1),
GPIO_FN(MSIOF0_SS2),
GPIO_FN(MSIOF0_TSYNC),
GPIO_FN(MSIOF0_RSCK),
GPIO_FN(MSIOF0_RSYNC),
/* MSIOF1 */
GPIO_FN(MSIOF1_RXD),
GPIO_FN(MSIOF1_TXD),
GPIO_FN(MSIOF1_MCK),
GPIO_FN(MSIOF1_TSCK),
GPIO_FN(MSIOF1_SS1),
GPIO_FN(MSIOF1_SS2),
GPIO_FN(MSIOF1_TSYNC),
GPIO_FN(MSIOF1_RSCK),
GPIO_FN(MSIOF1_RSYNC),
/* DMAC */
GPIO_FN(DMAC_DACK0),
GPIO_FN(DMAC_DREQ0),
GPIO_FN(DMAC_DACK1),
GPIO_FN(DMAC_DREQ1),
/* SDHI0 */
GPIO_FN(SDHI0CD),
GPIO_FN(SDHI0WP),
GPIO_FN(SDHI0CMD),
GPIO_FN(SDHI0CLK),
GPIO_FN(SDHI0D3),
GPIO_FN(SDHI0D2),
GPIO_FN(SDHI0D1),
GPIO_FN(SDHI0D0),
/* SDHI1 */
GPIO_FN(SDHI1CD),
GPIO_FN(SDHI1WP),
GPIO_FN(SDHI1CMD),
GPIO_FN(SDHI1CLK),
GPIO_FN(SDHI1D3),
GPIO_FN(SDHI1D2),
GPIO_FN(SDHI1D1),
GPIO_FN(SDHI1D0),
/* MMC */
GPIO_FN(MMC_D7),
GPIO_FN(MMC_D6),
GPIO_FN(MMC_D5),
GPIO_FN(MMC_D4),
GPIO_FN(MMC_D3),
GPIO_FN(MMC_D2),
GPIO_FN(MMC_D1),
GPIO_FN(MMC_D0),
GPIO_FN(MMC_CLK),
GPIO_FN(MMC_CMD),
/* IrDA */
GPIO_FN(IRDA_OUT),
GPIO_FN(IRDA_IN),
/* TSIF */
GPIO_FN(TSIF_TS0_SDAT),
GPIO_FN(TSIF_TS0_SCK),
GPIO_FN(TSIF_TS0_SDEN),
GPIO_FN(TSIF_TS0_SPSYNC),
/* IRQ */
GPIO_FN(INTC_IRQ7),
GPIO_FN(INTC_IRQ6),
GPIO_FN(INTC_IRQ5),
GPIO_FN(INTC_IRQ4),
GPIO_FN(INTC_IRQ3),
GPIO_FN(INTC_IRQ2),
GPIO_FN(INTC_IRQ1),
GPIO_FN(INTC_IRQ0),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
@ -2107,7 +2111,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
static struct pinmux_data_reg pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@ -2203,20 +2207,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
struct sh_pfc_soc_info sh7724_pinmux_info = {
const struct sh_pfc_soc_info sh7724_pinmux_info = {
.name = "sh7724_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PTA7,
.last_gpio = GPIO_FN_INTC_IRQ0,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

55
drivers/pinctrl/sh-pfc/pfc-sh7734.c
View file

@ -14,11 +14,6 @@
#include "sh_pfc.h"
#define CPU_32_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
PORT_1(fn, pfx##31, sfx)
#define CPU_32_PORT5(fn, pfx, sfx) \
PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
@ -29,11 +24,11 @@
/* GPSR0 - GPSR5 */
#define CPU_ALL_PORT(fn, pfx, sfx) \
CPU_32_PORT(fn, pfx##_0_, sfx), \
CPU_32_PORT(fn, pfx##_1_, sfx), \
CPU_32_PORT(fn, pfx##_2_, sfx), \
CPU_32_PORT(fn, pfx##_3_, sfx), \
CPU_32_PORT(fn, pfx##_4_, sfx), \
PORT_32(fn, pfx##_0_, sfx), \
PORT_32(fn, pfx##_1_, sfx), \
PORT_32(fn, pfx##_2_, sfx), \
PORT_32(fn, pfx##_3_, sfx), \
PORT_32(fn, pfx##_4_, sfx), \
CPU_32_PORT5(fn, pfx##_5_, sfx)
#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
@ -47,20 +42,8 @@
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
#define PORT_10_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
#define CPU_32_PORT_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
PORT_10_REV(fn, pfx, sfx)
#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused)
#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
@ -609,7 +592,7 @@ enum {
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT),
@ -1384,9 +1367,13 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
};
static struct pinmux_gpio pinmux_gpios[] = {
static struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
@ -1665,7 +1652,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) {
GP_0_31_FN, FN_IP2_2_0,
GP_0_30_FN, FN_IP1_31_29,
@ -2434,7 +2421,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
static struct pinmux_data_reg pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
/* GPIO 0 - 5*/
{ PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } },
{ PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } },
@ -2451,22 +2438,20 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
struct sh_pfc_soc_info sh7734_pinmux_info = {
const struct sh_pfc_soc_info sh7734_pinmux_info = {
.name = "sh7734_pfc",
.unlock_reg = 0xFFFC0000,
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_GP_0_0,
.last_gpio = GPIO_FN_ST_CLKOUT,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

620
drivers/pinctrl/sh-pfc/pfc-sh7757.c
View file

@ -526,7 +526,7 @@ enum {
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
static const pinmux_enum_t pinmux_data[] = {
/* PTA GPIO */
PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
@ -1114,7 +1114,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN),
};
static struct pinmux_gpio pinmux_gpios[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PTA */
PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@ -1370,359 +1370,363 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
/* PTA (mobule: LBSC, RGMII) */
PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK),
PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK),
PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK),
PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK),
PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK),
PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK),
GPIO_FN(BS),
GPIO_FN(RDWR),
GPIO_FN(WE1),
GPIO_FN(RDY),
GPIO_FN(ET0_MDC),
GPIO_FN(ET0_MDIO),
GPIO_FN(ET1_MDC),
GPIO_FN(ET1_MDIO),
/* PTB (mobule: INTC, ONFI, TMU) */
PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK),
PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK),
PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK),
PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK),
PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK),
PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK),
PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK),
PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK),
PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK),
PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK),
PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK),
PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK),
PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK),
PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK),
PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK),
PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
GPIO_FN(IRQ15),
GPIO_FN(IRQ14),
GPIO_FN(IRQ13),
GPIO_FN(IRQ12),
GPIO_FN(IRQ11),
GPIO_FN(IRQ10),
GPIO_FN(IRQ9),
GPIO_FN(IRQ8),
GPIO_FN(ON_NRE),
GPIO_FN(ON_NWE),
GPIO_FN(ON_NWP),
GPIO_FN(ON_NCE0),
GPIO_FN(ON_R_B0),
GPIO_FN(ON_ALE),
GPIO_FN(ON_CLE),
GPIO_FN(TCLK),
/* PTC (mobule: IRQ, PWMU) */
PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK),
PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK),
PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK),
PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK),
PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK),
PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK),
GPIO_FN(IRQ7),
GPIO_FN(IRQ6),
GPIO_FN(IRQ5),
GPIO_FN(IRQ4),
GPIO_FN(IRQ3),
GPIO_FN(IRQ2),
GPIO_FN(IRQ1),
GPIO_FN(IRQ0),
GPIO_FN(PWMU0),
GPIO_FN(PWMU1),
GPIO_FN(PWMU2),
GPIO_FN(PWMU3),
GPIO_FN(PWMU4),
GPIO_FN(PWMU5),
/* PTD (mobule: SPI0, DMAC) */
PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK),
PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK),
PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK),
PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK),
PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK),
PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK),
PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK),
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
GPIO_FN(SP0_MOSI),
GPIO_FN(SP0_MISO),
GPIO_FN(SP0_SCK),
GPIO_FN(SP0_SCK_FB),
GPIO_FN(SP0_SS0),
GPIO_FN(SP0_SS1),
GPIO_FN(SP0_SS2),
GPIO_FN(SP0_SS3),
GPIO_FN(DREQ0),
GPIO_FN(DACK0),
GPIO_FN(TEND0),
/* PTE (mobule: RMII) */
PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK),
PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK),
PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK),
PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK),
PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK),
PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK),
PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK),
PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK),
GPIO_FN(RMII0_CRS_DV),
GPIO_FN(RMII0_TXD1),
GPIO_FN(RMII0_TXD0),
GPIO_FN(RMII0_TXEN),
GPIO_FN(RMII0_REFCLK),
GPIO_FN(RMII0_RXD1),
GPIO_FN(RMII0_RXD0),
GPIO_FN(RMII0_RX_ER),
/* PTF (mobule: RMII, SerMux) */
PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK),
PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK),
PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK),
PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK),
PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK),
PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK),
PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK),
PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK),
PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK),
GPIO_FN(RMII1_CRS_DV),
GPIO_FN(RMII1_TXD1),
GPIO_FN(RMII1_TXD0),
GPIO_FN(RMII1_TXEN),
GPIO_FN(RMII1_REFCLK),
GPIO_FN(RMII1_RXD1),
GPIO_FN(RMII1_RXD0),
GPIO_FN(RMII1_RX_ER),
GPIO_FN(RAC_RI),
/* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK),
PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK),
PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK),
PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK),
PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK),
PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK),
PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK),
GPIO_FN(BOOTFMS),
GPIO_FN(BOOTWP),
GPIO_FN(A25),
GPIO_FN(A24),
GPIO_FN(SERIRQ),
GPIO_FN(WDTOVF),
GPIO_FN(LPCPD),
GPIO_FN(LDRQ),
GPIO_FN(MMCCLK),
GPIO_FN(MMCCMD),
/* PTH (mobule: SPI1, LPC, DMAC, ADC) */
PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK),
PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK),
PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK),
PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK),
PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK),
PINMUX_GPIO(GPIO_FN_WP, WP_MARK),
PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK),
PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK),
PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK),
GPIO_FN(SP1_MOSI),
GPIO_FN(SP1_MISO),
GPIO_FN(SP1_SCK),
GPIO_FN(SP1_SCK_FB),
GPIO_FN(SP1_SS0),
GPIO_FN(SP1_SS1),
GPIO_FN(WP),
GPIO_FN(FMS0),
GPIO_FN(TEND1),
GPIO_FN(DREQ1),
GPIO_FN(DACK1),
GPIO_FN(ADTRG1),
GPIO_FN(ADTRG0),
/* PTI (mobule: LBSC, SDHI) */
PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK),
PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK),
PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK),
PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK),
PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK),
PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK),
PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK),
PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK),
GPIO_FN(D15),
GPIO_FN(D14),
GPIO_FN(D13),
GPIO_FN(D12),
GPIO_FN(D11),
GPIO_FN(D10),
GPIO_FN(D9),
GPIO_FN(D8),
GPIO_FN(SD_WP),
GPIO_FN(SD_CD),
GPIO_FN(SD_CLK),
GPIO_FN(SD_CMD),
GPIO_FN(SD_D3),
GPIO_FN(SD_D2),
GPIO_FN(SD_D1),
GPIO_FN(SD_D0),
/* PTJ (mobule: SCIF234, SERMUX) */
PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK),
PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
GPIO_FN(RTS3),
GPIO_FN(CTS3),
GPIO_FN(TXD3),
GPIO_FN(RXD3),
GPIO_FN(RTS4),
GPIO_FN(RXD4),
GPIO_FN(TXD4),
/* PTK (mobule: SERMUX, LBSC, SCIF) */
PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK),
PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK),
PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK),
PINMUX_GPIO(GPIO_FN_COM2_CTS, COM2_CTS_MARK),
PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK),
PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK),
PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK),
PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK),
PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
GPIO_FN(COM2_TXD),
GPIO_FN(COM2_RXD),
GPIO_FN(COM2_RTS),
GPIO_FN(COM2_CTS),
GPIO_FN(COM2_DTR),
GPIO_FN(COM2_DSR),
GPIO_FN(COM2_DCD),
GPIO_FN(CLKOUT),
GPIO_FN(SCK2),
GPIO_FN(SCK4),
GPIO_FN(SCK3),
/* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK),
PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK),
PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK),
PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK),
PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK),
PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK),
PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK),
PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
GPIO_FN(RAC_RXD),
GPIO_FN(RAC_RTS),
GPIO_FN(RAC_CTS),
GPIO_FN(RAC_DTR),
GPIO_FN(RAC_DSR),
GPIO_FN(RAC_DCD),
GPIO_FN(RAC_TXD),
GPIO_FN(RXD2),
GPIO_FN(CS5),
GPIO_FN(CS6),
GPIO_FN(AUDSYNC),
GPIO_FN(AUDCK),
GPIO_FN(TXD2),
/* PTM (mobule: LBSC, IIC) */
PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK),
PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK),
PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK),
PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK),
PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK),
GPIO_FN(CS4),
GPIO_FN(RD),
GPIO_FN(WE0),
GPIO_FN(CS0),
GPIO_FN(SDA6),
GPIO_FN(SCL6),
GPIO_FN(SDA7),
GPIO_FN(SCL7),
/* PTN (mobule: USB, JMC, SGPIO, WDT) */
PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK),
PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK),
PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK),
PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK),
PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK),
PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK),
PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK),
PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK),
PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK),
PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK),
PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK),
PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK),
GPIO_FN(VBUS_EN),
GPIO_FN(VBUS_OC),
GPIO_FN(JMCTCK),
GPIO_FN(JMCTMS),
GPIO_FN(JMCTDO),
GPIO_FN(JMCTDI),
GPIO_FN(JMCTRST),
GPIO_FN(SGPIO1_CLK),
GPIO_FN(SGPIO1_LOAD),
GPIO_FN(SGPIO1_DI),
GPIO_FN(SGPIO1_DO),
GPIO_FN(SUB_CLKIN),
/* PTO (mobule: SGPIO, SerMux) */
PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK),
PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK),
PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK),
PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK),
PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK),
PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK),
PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK),
PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK),
PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK),
PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK),
PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK),
PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK),
GPIO_FN(SGPIO0_CLK),
GPIO_FN(SGPIO0_LOAD),
GPIO_FN(SGPIO0_DI),
GPIO_FN(SGPIO0_DO),
GPIO_FN(SGPIO2_CLK),
GPIO_FN(SGPIO2_LOAD),
GPIO_FN(SGPIO2_DI),
GPIO_FN(SGPIO2_DO),
GPIO_FN(COM1_TXD),
GPIO_FN(COM1_RXD),
GPIO_FN(COM1_RTS),
GPIO_FN(COM1_CTS),
/* PTP (mobule: EVC, ADC) */
/* PTQ (mobule: LPC) */
PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK),
PINMUX_GPIO(GPIO_FN_LAD2, LAD2_MARK),
PINMUX_GPIO(GPIO_FN_LAD1, LAD1_MARK),
PINMUX_GPIO(GPIO_FN_LAD0, LAD0_MARK),
PINMUX_GPIO(GPIO_FN_LFRAME, LFRAME_MARK),
PINMUX_GPIO(GPIO_FN_LRESET, LRESET_MARK),
PINMUX_GPIO(GPIO_FN_LCLK, LCLK_MARK),
GPIO_FN(LAD3),
GPIO_FN(LAD2),
GPIO_FN(LAD1),
GPIO_FN(LAD0),
GPIO_FN(LFRAME),
GPIO_FN(LRESET),
GPIO_FN(LCLK),
/* PTR (mobule: GRA, IIC) */
PINMUX_GPIO(GPIO_FN_DDC3, DDC3_MARK),
PINMUX_GPIO(GPIO_FN_DDC2, DDC2_MARK),
PINMUX_GPIO(GPIO_FN_SDA8, SDA8_MARK),
PINMUX_GPIO(GPIO_FN_SCL8, SCL8_MARK),
PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
GPIO_FN(DDC3),
GPIO_FN(DDC2),
GPIO_FN(SDA8),
GPIO_FN(SCL8),
GPIO_FN(SDA2),
GPIO_FN(SCL2),
GPIO_FN(SDA1),
GPIO_FN(SCL1),
GPIO_FN(SDA0),
GPIO_FN(SCL0),
/* PTS (mobule: GRA, IIC) */
PINMUX_GPIO(GPIO_FN_DDC1, DDC1_MARK),
PINMUX_GPIO(GPIO_FN_DDC0, DDC0_MARK),
PINMUX_GPIO(GPIO_FN_SDA9, SDA9_MARK),
PINMUX_GPIO(GPIO_FN_SCL9, SCL9_MARK),
PINMUX_GPIO(GPIO_FN_SDA5, SDA5_MARK),
PINMUX_GPIO(GPIO_FN_SCL5, SCL5_MARK),
PINMUX_GPIO(GPIO_FN_SDA4, SDA4_MARK),
PINMUX_GPIO(GPIO_FN_SCL4, SCL4_MARK),
PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
GPIO_FN(DDC1),
GPIO_FN(DDC0),
GPIO_FN(SDA9),
GPIO_FN(SCL9),
GPIO_FN(SDA5),
GPIO_FN(SCL5),
GPIO_FN(SDA4),
GPIO_FN(SCL4),
GPIO_FN(SDA3),
GPIO_FN(SCL3),
/* PTT (mobule: PWMX, AUD) */
PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK),
PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK),
PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK),
PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK),
PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK),
PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK),
PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK),
PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
GPIO_FN(PWMX7),
GPIO_FN(PWMX6),
GPIO_FN(PWMX5),
GPIO_FN(PWMX4),
GPIO_FN(PWMX3),
GPIO_FN(PWMX2),
GPIO_FN(PWMX1),
GPIO_FN(PWMX0),
GPIO_FN(AUDATA3),
GPIO_FN(AUDATA2),
GPIO_FN(AUDATA1),
GPIO_FN(AUDATA0),
GPIO_FN(STATUS1),
GPIO_FN(STATUS0),
/* PTU (mobule: LPC, APM) */
PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK),
PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK),
PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK),
PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK),
PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK),
PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK),
PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK),
PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK),
PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK),
PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK),
PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK),
PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK),
PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK),
PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK),
PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK),
PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK),
GPIO_FN(LGPIO7),
GPIO_FN(LGPIO6),
GPIO_FN(LGPIO5),
GPIO_FN(LGPIO4),
GPIO_FN(LGPIO3),
GPIO_FN(LGPIO2),
GPIO_FN(LGPIO1),
GPIO_FN(LGPIO0),
GPIO_FN(APMONCTL_O),
GPIO_FN(APMPWBTOUT_O),
GPIO_FN(APMSCI_O),
GPIO_FN(APMVDDON),
GPIO_FN(APMSLPBTN),
GPIO_FN(APMPWRBTN),
GPIO_FN(APMS5N),
GPIO_FN(APMS3N),
/* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK),
PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK),
PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK),
PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK),
PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK),
PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK),
PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK),
PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK),
PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK),
PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK),
PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK),
PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK),
GPIO_FN(A23),
GPIO_FN(A22),
GPIO_FN(A21),
GPIO_FN(A20),
GPIO_FN(A19),
GPIO_FN(A18),
GPIO_FN(A17),
GPIO_FN(A16),
GPIO_FN(COM2_RI),
GPIO_FN(R_SPI_MOSI),
GPIO_FN(R_SPI_MISO),
GPIO_FN(R_SPI_RSPCK),
GPIO_FN(R_SPI_SSL0),
GPIO_FN(R_SPI_SSL1),
GPIO_FN(EVENT7),
GPIO_FN(EVENT6),
GPIO_FN(VBIOS_DI),
GPIO_FN(VBIOS_DO),
GPIO_FN(VBIOS_CLK),
GPIO_FN(VBIOS_CS),
/* PTW (mobule: LBSC, EVC, SCIF) */
PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK),
PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK),
PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK),
PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK),
PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK),
PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK),
PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK),
PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK),
GPIO_FN(A16),
GPIO_FN(A15),
GPIO_FN(A14),
GPIO_FN(A13),
GPIO_FN(A12),
GPIO_FN(A11),
GPIO_FN(A10),
GPIO_FN(A9),
GPIO_FN(A8),
GPIO_FN(EVENT5),
GPIO_FN(EVENT4),
GPIO_FN(EVENT3),
GPIO_FN(EVENT2),
GPIO_FN(EVENT1),
GPIO_FN(EVENT0),
GPIO_FN(CTS4),
GPIO_FN(CTS2),
/* PTX (mobule: LBSC) */
PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK),
PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK),
PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK),
PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK),
GPIO_FN(A7),
GPIO_FN(A6),
GPIO_FN(A5),
GPIO_FN(A4),
GPIO_FN(A3),
GPIO_FN(A2),
GPIO_FN(A1),
GPIO_FN(A0),
GPIO_FN(RTS2),
GPIO_FN(SIM_D),
GPIO_FN(SIM_CLK),
GPIO_FN(SIM_RST),
/* PTY (mobule: LBSC) */
PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
GPIO_FN(D7),
GPIO_FN(D6),
GPIO_FN(D5),
GPIO_FN(D4),
GPIO_FN(D3),
GPIO_FN(D2),
GPIO_FN(D1),
GPIO_FN(D0),
/* PTZ (mobule: eMMC, ONFI) */
PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK),
PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK),
PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK),
PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK),
PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK),
PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK),
PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK),
PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK),
PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK),
PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK),
PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK),
PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK),
PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK),
PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK),
PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK),
PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK),
GPIO_FN(MMCDAT7),
GPIO_FN(MMCDAT6),
GPIO_FN(MMCDAT5),
GPIO_FN(MMCDAT4),
GPIO_FN(MMCDAT3),
GPIO_FN(MMCDAT2),
GPIO_FN(MMCDAT1),
GPIO_FN(MMCDAT0),
GPIO_FN(ON_DQ7),
GPIO_FN(ON_DQ6),
GPIO_FN(ON_DQ5),
GPIO_FN(ON_DQ4),
GPIO_FN(ON_DQ3),
GPIO_FN(ON_DQ2),
GPIO_FN(ON_DQ1),
GPIO_FN(ON_DQ0),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU,
PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU,
@ -2152,7 +2156,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
static struct pinmux_data_reg pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xffec0034, 8) {
PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@ -2260,20 +2264,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
struct sh_pfc_soc_info sh7757_pinmux_info = {
const struct sh_pfc_soc_info sh7757_pinmux_info = {
.name = "sh7757_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PTA0,
.last_gpio = GPIO_FN_ON_DQ0,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

358
drivers/pinctrl/sh-pfc/pfc-sh7785.c
View file

@ -355,7 +355,7 @@ enum {
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
static const pinmux_enum_t pinmux_data[] = {
/* PA GPIO */
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@ -702,7 +702,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1),
};
static struct pinmux_gpio pinmux_gpios[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@ -845,176 +845,180 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PR2, PR2_DATA),
PINMUX_GPIO(GPIO_PR1, PR1_DATA),
PINMUX_GPIO(GPIO_PR0, PR0_DATA),
/* FN */
PINMUX_GPIO(GPIO_FN_D63_AD31, D63_AD31_MARK),
PINMUX_GPIO(GPIO_FN_D62_AD30, D62_AD30_MARK),
PINMUX_GPIO(GPIO_FN_D61_AD29, D61_AD29_MARK),
PINMUX_GPIO(GPIO_FN_D60_AD28, D60_AD28_MARK),
PINMUX_GPIO(GPIO_FN_D59_AD27, D59_AD27_MARK),
PINMUX_GPIO(GPIO_FN_D58_AD26, D58_AD26_MARK),
PINMUX_GPIO(GPIO_FN_D57_AD25, D57_AD25_MARK),
PINMUX_GPIO(GPIO_FN_D56_AD24, D56_AD24_MARK),
PINMUX_GPIO(GPIO_FN_D55_AD23, D55_AD23_MARK),
PINMUX_GPIO(GPIO_FN_D54_AD22, D54_AD22_MARK),
PINMUX_GPIO(GPIO_FN_D53_AD21, D53_AD21_MARK),
PINMUX_GPIO(GPIO_FN_D52_AD20, D52_AD20_MARK),
PINMUX_GPIO(GPIO_FN_D51_AD19, D51_AD19_MARK),
PINMUX_GPIO(GPIO_FN_D50_AD18, D50_AD18_MARK),
PINMUX_GPIO(GPIO_FN_D49_AD17_DB5, D49_AD17_DB5_MARK),
PINMUX_GPIO(GPIO_FN_D48_AD16_DB4, D48_AD16_DB4_MARK),
PINMUX_GPIO(GPIO_FN_D47_AD15_DB3, D47_AD15_DB3_MARK),
PINMUX_GPIO(GPIO_FN_D46_AD14_DB2, D46_AD14_DB2_MARK),
PINMUX_GPIO(GPIO_FN_D45_AD13_DB1, D45_AD13_DB1_MARK),
PINMUX_GPIO(GPIO_FN_D44_AD12_DB0, D44_AD12_DB0_MARK),
PINMUX_GPIO(GPIO_FN_D43_AD11_DG5, D43_AD11_DG5_MARK),
PINMUX_GPIO(GPIO_FN_D42_AD10_DG4, D42_AD10_DG4_MARK),
PINMUX_GPIO(GPIO_FN_D41_AD9_DG3, D41_AD9_DG3_MARK),
PINMUX_GPIO(GPIO_FN_D40_AD8_DG2, D40_AD8_DG2_MARK),
PINMUX_GPIO(GPIO_FN_D39_AD7_DG1, D39_AD7_DG1_MARK),
PINMUX_GPIO(GPIO_FN_D38_AD6_DG0, D38_AD6_DG0_MARK),
PINMUX_GPIO(GPIO_FN_D37_AD5_DR5, D37_AD5_DR5_MARK),
PINMUX_GPIO(GPIO_FN_D36_AD4_DR4, D36_AD4_DR4_MARK),
PINMUX_GPIO(GPIO_FN_D35_AD3_DR3, D35_AD3_DR3_MARK),
PINMUX_GPIO(GPIO_FN_D34_AD2_DR2, D34_AD2_DR2_MARK),
PINMUX_GPIO(GPIO_FN_D33_AD1_DR1, D33_AD1_DR1_MARK),
PINMUX_GPIO(GPIO_FN_D32_AD0_DR0, D32_AD0_DR0_MARK),
PINMUX_GPIO(GPIO_FN_REQ1, REQ1_MARK),
PINMUX_GPIO(GPIO_FN_REQ2, REQ2_MARK),
PINMUX_GPIO(GPIO_FN_REQ3, REQ3_MARK),
PINMUX_GPIO(GPIO_FN_GNT1, GNT1_MARK),
PINMUX_GPIO(GPIO_FN_GNT2, GNT2_MARK),
PINMUX_GPIO(GPIO_FN_GNT3, GNT3_MARK),
PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK),
PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
PINMUX_GPIO(GPIO_FN_INTD, INTD_MARK),
PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK),
PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK),
PINMUX_GPIO(GPIO_FN_FRE, FRE_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK),
PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK),
PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK),
PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK),
PINMUX_GPIO(GPIO_FN_SIOF_TXD_PJ, SIOF_TXD_PJ_MARK),
PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK),
PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK),
PINMUX_GPIO(GPIO_FN_SIOF_RXD_PJ, SIOF_RXD_PJ_MARK),
PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK),
PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SIOF_SYNC_PJ, SIOF_SYNC_PJ_MARK),
PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK),
PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK),
PINMUX_GPIO(GPIO_FN_SIOF_MCLK_PJ, SIOF_MCLK_PJ_MARK),
PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK),
PINMUX_GPIO(GPIO_FN_SIOF_SCK_PJ, SIOF_SCK_PJ_MARK),
PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK),
PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK),
PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK),
PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK),
PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
PINMUX_GPIO(GPIO_FN_DRAK0_PK3, DRAK0_PK3_MARK),
PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
PINMUX_GPIO(GPIO_FN_DRAK1_PK2, DRAK1_PK2_MARK),
PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK),
PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK),
PINMUX_GPIO(GPIO_FN_SIOF_TXD_PK, SIOF_TXD_PK_MARK),
PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK),
PINMUX_GPIO(GPIO_FN_MMCDAT, MMCDAT_MARK),
PINMUX_GPIO(GPIO_FN_SIOF_SCK_PK, SIOF_SCK_PK_MARK),
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
PINMUX_GPIO(GPIO_FN_DRAK0_PK1, DRAK0_PK1_MARK),
PINMUX_GPIO(GPIO_FN_DRAK1_PK0, DRAK1_PK0_MARK),
PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
PINMUX_GPIO(GPIO_FN_INTB, INTB_MARK),
PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
PINMUX_GPIO(GPIO_FN_INTC, INTC_MARK),
PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK),
PINMUX_GPIO(GPIO_FN_FD4, FD4_MARK),
PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK),
PINMUX_GPIO(GPIO_FN_FD5, FD5_MARK),
PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK),
PINMUX_GPIO(GPIO_FN_FD6, FD6_MARK),
PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK),
PINMUX_GPIO(GPIO_FN_FD7, FD7_MARK),
PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
PINMUX_GPIO(GPIO_FN_BREQ_BSACK, BREQ_BSACK_MARK),
PINMUX_GPIO(GPIO_FN_BACK_BSREQ, BACK_BSREQ_MARK),
PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK),
PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK),
PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK),
PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK),
PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK),
PINMUX_GPIO(GPIO_FN_FD0, FD0_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
PINMUX_GPIO(GPIO_FN_FD1, FD1_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
PINMUX_GPIO(GPIO_FN_FD2, FD2_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
PINMUX_GPIO(GPIO_FN_FD3, FD3_MARK),
PINMUX_GPIO(GPIO_FN_DEVSEL_DCLKOUT, DEVSEL_DCLKOUT_MARK),
PINMUX_GPIO(GPIO_FN_STOP_CDE, STOP_CDE_MARK),
PINMUX_GPIO(GPIO_FN_LOCK_ODDF, LOCK_ODDF_MARK),
PINMUX_GPIO(GPIO_FN_TRDY_DISPL, TRDY_DISPL_MARK),
PINMUX_GPIO(GPIO_FN_IRDY_HSYNC, IRDY_HSYNC_MARK),
PINMUX_GPIO(GPIO_FN_PCIFRAME_VSYNC, PCIFRAME_VSYNC_MARK),
PINMUX_GPIO(GPIO_FN_INTA, INTA_MARK),
PINMUX_GPIO(GPIO_FN_GNT0_GNTIN, GNT0_GNTIN_MARK),
PINMUX_GPIO(GPIO_FN_REQ0_REQOUT, REQ0_REQOUT_MARK),
PINMUX_GPIO(GPIO_FN_PERR, PERR_MARK),
PINMUX_GPIO(GPIO_FN_SERR, SERR_MARK),
PINMUX_GPIO(GPIO_FN_WE7_CBE3, WE7_CBE3_MARK),
PINMUX_GPIO(GPIO_FN_WE6_CBE2, WE6_CBE2_MARK),
PINMUX_GPIO(GPIO_FN_WE5_CBE1, WE5_CBE1_MARK),
PINMUX_GPIO(GPIO_FN_WE4_CBE0, WE4_CBE0_MARK),
PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOF_RXD, SIOF_RXD_MARK),
PINMUX_GPIO(GPIO_FN_MRESETOUT, MRESETOUT_MARK),
PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
/* FN */
GPIO_FN(D63_AD31),
GPIO_FN(D62_AD30),
GPIO_FN(D61_AD29),
GPIO_FN(D60_AD28),
GPIO_FN(D59_AD27),
GPIO_FN(D58_AD26),
GPIO_FN(D57_AD25),
GPIO_FN(D56_AD24),
GPIO_FN(D55_AD23),
GPIO_FN(D54_AD22),
GPIO_FN(D53_AD21),
GPIO_FN(D52_AD20),
GPIO_FN(D51_AD19),
GPIO_FN(D50_AD18),
GPIO_FN(D49_AD17_DB5),
GPIO_FN(D48_AD16_DB4),
GPIO_FN(D47_AD15_DB3),
GPIO_FN(D46_AD14_DB2),
GPIO_FN(D45_AD13_DB1),
GPIO_FN(D44_AD12_DB0),
GPIO_FN(D43_AD11_DG5),
GPIO_FN(D42_AD10_DG4),
GPIO_FN(D41_AD9_DG3),
GPIO_FN(D40_AD8_DG2),
GPIO_FN(D39_AD7_DG1),
GPIO_FN(D38_AD6_DG0),
GPIO_FN(D37_AD5_DR5),
GPIO_FN(D36_AD4_DR4),
GPIO_FN(D35_AD3_DR3),
GPIO_FN(D34_AD2_DR2),
GPIO_FN(D33_AD1_DR1),
GPIO_FN(D32_AD0_DR0),
GPIO_FN(REQ1),
GPIO_FN(REQ2),
GPIO_FN(REQ3),
GPIO_FN(GNT1),
GPIO_FN(GNT2),
GPIO_FN(GNT3),
GPIO_FN(MMCCLK),
GPIO_FN(D31),
GPIO_FN(D30),
GPIO_FN(D29),
GPIO_FN(D28),
GPIO_FN(D27),
GPIO_FN(D26),
GPIO_FN(D25),
GPIO_FN(D24),
GPIO_FN(D23),
GPIO_FN(D22),
GPIO_FN(D21),
GPIO_FN(D20),
GPIO_FN(D19),
GPIO_FN(D18),
GPIO_FN(D17),
GPIO_FN(D16),
GPIO_FN(SCIF1_SCK),
GPIO_FN(SCIF1_RXD),
GPIO_FN(SCIF1_TXD),
GPIO_FN(SCIF0_CTS),
GPIO_FN(INTD),
GPIO_FN(FCE),
GPIO_FN(SCIF0_RTS),
GPIO_FN(HSPI_CS),
GPIO_FN(FSE),
GPIO_FN(SCIF0_SCK),
GPIO_FN(HSPI_CLK),
GPIO_FN(FRE),
GPIO_FN(SCIF0_RXD),
GPIO_FN(HSPI_RX),
GPIO_FN(FRB),
GPIO_FN(SCIF0_TXD),
GPIO_FN(HSPI_TX),
GPIO_FN(FWE),
GPIO_FN(SCIF5_TXD),
GPIO_FN(HAC1_SYNC),
GPIO_FN(SSI1_WS),
GPIO_FN(SIOF_TXD_PJ),
GPIO_FN(HAC0_SDOUT),
GPIO_FN(SSI0_SDATA),
GPIO_FN(SIOF_RXD_PJ),
GPIO_FN(HAC0_SDIN),
GPIO_FN(SSI0_SCK),
GPIO_FN(SIOF_SYNC_PJ),
GPIO_FN(HAC0_SYNC),
GPIO_FN(SSI0_WS),
GPIO_FN(SIOF_MCLK_PJ),
GPIO_FN(HAC_RES),
GPIO_FN(SIOF_SCK_PJ),
GPIO_FN(HAC0_BITCLK),
GPIO_FN(SSI0_CLK),
GPIO_FN(HAC1_BITCLK),
GPIO_FN(SSI1_CLK),
GPIO_FN(TCLK),
GPIO_FN(IOIS16),
GPIO_FN(STATUS0),
GPIO_FN(DRAK0_PK3),
GPIO_FN(STATUS1),
GPIO_FN(DRAK1_PK2),
GPIO_FN(DACK2),
GPIO_FN(SCIF2_TXD),
GPIO_FN(MMCCMD),
GPIO_FN(SIOF_TXD_PK),
GPIO_FN(DACK3),
GPIO_FN(SCIF2_SCK),
GPIO_FN(MMCDAT),
GPIO_FN(SIOF_SCK_PK),
GPIO_FN(DREQ0),
GPIO_FN(DREQ1),
GPIO_FN(DRAK0_PK1),
GPIO_FN(DRAK1_PK0),
GPIO_FN(DREQ2),
GPIO_FN(INTB),
GPIO_FN(DREQ3),
GPIO_FN(INTC),
GPIO_FN(DRAK2),
GPIO_FN(CE2A),
GPIO_FN(IRL4),
GPIO_FN(FD4),
GPIO_FN(IRL5),
GPIO_FN(FD5),
GPIO_FN(IRL6),
GPIO_FN(FD6),
GPIO_FN(IRL7),
GPIO_FN(FD7),
GPIO_FN(DRAK3),
GPIO_FN(CE2B),
GPIO_FN(BREQ_BSACK),
GPIO_FN(BACK_BSREQ),
GPIO_FN(SCIF5_RXD),
GPIO_FN(HAC1_SDIN),
GPIO_FN(SSI1_SCK),
GPIO_FN(SCIF5_SCK),
GPIO_FN(HAC1_SDOUT),
GPIO_FN(SSI1_SDATA),
GPIO_FN(SCIF3_TXD),
GPIO_FN(FCLE),
GPIO_FN(SCIF3_RXD),
GPIO_FN(FALE),
GPIO_FN(SCIF3_SCK),
GPIO_FN(FD0),
GPIO_FN(SCIF4_TXD),
GPIO_FN(FD1),
GPIO_FN(SCIF4_RXD),
GPIO_FN(FD2),
GPIO_FN(SCIF4_SCK),
GPIO_FN(FD3),
GPIO_FN(DEVSEL_DCLKOUT),
GPIO_FN(STOP_CDE),
GPIO_FN(LOCK_ODDF),
GPIO_FN(TRDY_DISPL),
GPIO_FN(IRDY_HSYNC),
GPIO_FN(PCIFRAME_VSYNC),
GPIO_FN(INTA),
GPIO_FN(GNT0_GNTIN),
GPIO_FN(REQ0_REQOUT),
GPIO_FN(PERR),
GPIO_FN(SERR),
GPIO_FN(WE7_CBE3),
GPIO_FN(WE6_CBE2),
GPIO_FN(WE5_CBE1),
GPIO_FN(WE4_CBE0),
GPIO_FN(SCIF2_RXD),
GPIO_FN(SIOF_RXD),
GPIO_FN(MRESETOUT),
GPIO_FN(IRQOUT),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) {
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@ -1214,7 +1218,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
static struct pinmux_data_reg pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xffe70020, 8) {
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
@ -1282,20 +1286,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
struct sh_pfc_soc_info sh7785_pinmux_info = {
const struct sh_pfc_soc_info sh7785_pinmux_info = {
.name = "sh7785_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PA7,
.last_gpio = GPIO_FN_IRQOUT,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

300
drivers/pinctrl/sh-pfc/pfc-sh7786.c
View file

@ -191,7 +191,7 @@ enum {
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
static const pinmux_enum_t pinmux_data[] = {
/* PA GPIO */
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@ -427,7 +427,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
};
static struct pinmux_gpio pinmux_gpios[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@ -505,147 +505,151 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
/* FN */
PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK),
PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK),
PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK),
PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK),
PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK),
PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK),
PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK),
PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK),
PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK),
PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK),
PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK),
PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK),
PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK),
PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK),
PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK),
PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK),
PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK),
PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK),
PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK),
PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK),
PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK),
PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK),
PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK),
PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK),
PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK),
PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK),
PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK),
PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK),
PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK),
PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK),
PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK),
PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK),
PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK),
PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK),
PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK),
PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK),
PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK),
PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK),
PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK),
PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK),
PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK),
PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK),
PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK),
PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK),
PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK),
PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK),
PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK),
PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK),
PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK),
PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK),
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK),
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK),
PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK),
PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK),
PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK),
PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK),
PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK),
PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK),
PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK),
PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK),
PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK),
PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK),
PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK),
PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK),
PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK),
PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK),
PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK),
PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK),
PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK),
PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK),
PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK),
PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK),
PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK),
PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK),
PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK),
PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK),
PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK),
PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK),
PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK),
PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK),
PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK),
PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK),
PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK),
PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK),
PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK),
PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK),
PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK),
PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK),
PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK),
PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK),
PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK),
PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK),
PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
static const struct pinmux_func pinmux_func_gpios[] = {
/* FN */
GPIO_FN(CDE),
GPIO_FN(ETH_MAGIC),
GPIO_FN(DISP),
GPIO_FN(ETH_LINK),
GPIO_FN(DR5),
GPIO_FN(ETH_TX_ER),
GPIO_FN(DR4),
GPIO_FN(ETH_TX_EN),
GPIO_FN(DR3),
GPIO_FN(ETH_TXD3),
GPIO_FN(DR2),
GPIO_FN(ETH_TXD2),
GPIO_FN(DR1),
GPIO_FN(ETH_TXD1),
GPIO_FN(DR0),
GPIO_FN(ETH_TXD0),
GPIO_FN(VSYNC),
GPIO_FN(HSPI_CLK),
GPIO_FN(ODDF),
GPIO_FN(HSPI_CS),
GPIO_FN(DG5),
GPIO_FN(ETH_MDIO),
GPIO_FN(DG4),
GPIO_FN(ETH_RX_CLK),
GPIO_FN(DG3),
GPIO_FN(ETH_MDC),
GPIO_FN(DG2),
GPIO_FN(ETH_COL),
GPIO_FN(DG1),
GPIO_FN(ETH_TX_CLK),
GPIO_FN(DG0),
GPIO_FN(ETH_CRS),
GPIO_FN(DCLKIN),
GPIO_FN(HSPI_RX),
GPIO_FN(HSYNC),
GPIO_FN(HSPI_TX),
GPIO_FN(DB5),
GPIO_FN(ETH_RXD3),
GPIO_FN(DB4),
GPIO_FN(ETH_RXD2),
GPIO_FN(DB3),
GPIO_FN(ETH_RXD1),
GPIO_FN(DB2),
GPIO_FN(ETH_RXD0),
GPIO_FN(DB1),
GPIO_FN(ETH_RX_DV),
GPIO_FN(DB0),
GPIO_FN(ETH_RX_ER),
GPIO_FN(DCLKOUT),
GPIO_FN(SCIF1_SCK),
GPIO_FN(SCIF1_RXD),
GPIO_FN(SCIF1_TXD),
GPIO_FN(DACK1),
GPIO_FN(BACK),
GPIO_FN(FALE),
GPIO_FN(DACK0),
GPIO_FN(FCLE),
GPIO_FN(DREQ1),
GPIO_FN(BREQ),
GPIO_FN(USB_OVC1),
GPIO_FN(DREQ0),
GPIO_FN(USB_OVC0),
GPIO_FN(USB_PENC1),
GPIO_FN(USB_PENC0),
GPIO_FN(HAC1_SDOUT),
GPIO_FN(SSI1_SDATA),
GPIO_FN(SDIF1CMD),
GPIO_FN(HAC1_SDIN),
GPIO_FN(SSI1_SCK),
GPIO_FN(SDIF1CD),
GPIO_FN(HAC1_SYNC),
GPIO_FN(SSI1_WS),
GPIO_FN(SDIF1WP),
GPIO_FN(HAC1_BITCLK),
GPIO_FN(SSI1_CLK),
GPIO_FN(SDIF1CLK),
GPIO_FN(HAC0_SDOUT),
GPIO_FN(SSI0_SDATA),
GPIO_FN(SDIF1D3),
GPIO_FN(HAC0_SDIN),
GPIO_FN(SSI0_SCK),
GPIO_FN(SDIF1D2),
GPIO_FN(HAC0_SYNC),
GPIO_FN(SSI0_WS),
GPIO_FN(SDIF1D1),
GPIO_FN(HAC0_BITCLK),
GPIO_FN(SSI0_CLK),
GPIO_FN(SDIF1D0),
GPIO_FN(SCIF3_SCK),
GPIO_FN(SSI2_SDATA),
GPIO_FN(SCIF3_RXD),
GPIO_FN(TCLK),
GPIO_FN(SSI2_SCK),
GPIO_FN(SCIF3_TXD),
GPIO_FN(HAC_RES),
GPIO_FN(SSI2_WS),
GPIO_FN(DACK3),
GPIO_FN(SDIF0CMD),
GPIO_FN(DACK2),
GPIO_FN(SDIF0CD),
GPIO_FN(DREQ3),
GPIO_FN(SDIF0WP),
GPIO_FN(SCIF0_CTS),
GPIO_FN(DREQ2),
GPIO_FN(SDIF0CLK),
GPIO_FN(SCIF0_RTS),
GPIO_FN(IRL7),
GPIO_FN(SDIF0D3),
GPIO_FN(SCIF0_SCK),
GPIO_FN(IRL6),
GPIO_FN(SDIF0D2),
GPIO_FN(SCIF0_RXD),
GPIO_FN(IRL5),
GPIO_FN(SDIF0D1),
GPIO_FN(SCIF0_TXD),
GPIO_FN(IRL4),
GPIO_FN(SDIF0D0),
GPIO_FN(SCIF5_SCK),
GPIO_FN(FRB),
GPIO_FN(SCIF5_RXD),
GPIO_FN(IOIS16),
GPIO_FN(SCIF5_TXD),
GPIO_FN(CE2B),
GPIO_FN(DRAK3),
GPIO_FN(CE2A),
GPIO_FN(SCIF4_SCK),
GPIO_FN(DRAK2),
GPIO_FN(SSI3_WS),
GPIO_FN(SCIF4_RXD),
GPIO_FN(DRAK1),
GPIO_FN(SSI3_SDATA),
GPIO_FN(FSTATUS),
GPIO_FN(SCIF4_TXD),
GPIO_FN(DRAK0),
GPIO_FN(SSI3_SCK),
GPIO_FN(FSE),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@ -775,7 +779,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
static struct pinmux_data_reg pinmux_data_regs[] = {
static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
@ -815,20 +819,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
struct sh_pfc_soc_info sh7786_pinmux_info = {
const struct sh_pfc_soc_info sh7786_pinmux_info = {
.name = "sh7786_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PA7,
.last_gpio = GPIO_FN_IRL4,
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.func_gpios = pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,

152
drivers/pinctrl/sh-pfc/pfc-shx3.c
View file

@ -147,7 +147,7 @@ enum {
PINMUX_MARK_END,
};
static pinmux_enum_t shx3_pinmux_data[] = {
static const pinmux_enum_t shx3_pinmux_data[] = {
/* PA GPIO */
PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@ -306,7 +306,7 @@ static pinmux_enum_t shx3_pinmux_data[] = {
PINMUX_DATA(IRQOUT_MARK, PH0_FN),
};
static struct pinmux_gpio shx3_pinmux_gpios[] = {
static struct sh_pfc_pin shx3_pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@ -384,73 +384,77 @@ static struct pinmux_gpio shx3_pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PH2, PH2_DATA),
PINMUX_GPIO(GPIO_PH1, PH1_DATA),
PINMUX_GPIO(GPIO_PH0, PH0_DATA),
/* FN */
PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
PINMUX_GPIO(GPIO_FN_WE3, WE3_MARK),
PINMUX_GPIO(GPIO_FN_WE2, WE2_MARK),
PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
PINMUX_GPIO(GPIO_FN_CLKOUTENB, CLKOUTENB_MARK),
PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK),
PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK),
PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK),
PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK),
PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
PINMUX_GPIO(GPIO_FN_IRL3, IRL3_MARK),
PINMUX_GPIO(GPIO_FN_IRL2, IRL2_MARK),
PINMUX_GPIO(GPIO_FN_IRL1, IRL1_MARK),
PINMUX_GPIO(GPIO_FN_IRL0, IRL0_MARK),
PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
};
static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
#define PINMUX_FN_BASE ARRAY_SIZE(shx3_pinmux_pins)
static const struct pinmux_func shx3_pinmux_func_gpios[] = {
/* FN */
GPIO_FN(D31),
GPIO_FN(D30),
GPIO_FN(D29),
GPIO_FN(D28),
GPIO_FN(D27),
GPIO_FN(D26),
GPIO_FN(D25),
GPIO_FN(D24),
GPIO_FN(D23),
GPIO_FN(D22),
GPIO_FN(D21),
GPIO_FN(D20),
GPIO_FN(D19),
GPIO_FN(D18),
GPIO_FN(D17),
GPIO_FN(D16),
GPIO_FN(BACK),
GPIO_FN(BREQ),
GPIO_FN(WE3),
GPIO_FN(WE2),
GPIO_FN(CS6),
GPIO_FN(CS5),
GPIO_FN(CS4),
GPIO_FN(CLKOUTENB),
GPIO_FN(DACK3),
GPIO_FN(DACK2),
GPIO_FN(DACK1),
GPIO_FN(DACK0),
GPIO_FN(DREQ3),
GPIO_FN(DREQ2),
GPIO_FN(DREQ1),
GPIO_FN(DREQ0),
GPIO_FN(IRQ3),
GPIO_FN(IRQ2),
GPIO_FN(IRQ1),
GPIO_FN(IRQ0),
GPIO_FN(DRAK3),
GPIO_FN(DRAK2),
GPIO_FN(DRAK1),
GPIO_FN(DRAK0),
GPIO_FN(SCK3),
GPIO_FN(SCK2),
GPIO_FN(SCK1),
GPIO_FN(SCK0),
GPIO_FN(IRL3),
GPIO_FN(IRL2),
GPIO_FN(IRL1),
GPIO_FN(IRL0),
GPIO_FN(TXD3),
GPIO_FN(TXD2),
GPIO_FN(TXD1),
GPIO_FN(TXD0),
GPIO_FN(RXD3),
GPIO_FN(RXD2),
GPIO_FN(RXD1),
GPIO_FN(RXD0),
GPIO_FN(CE2B),
GPIO_FN(CE2A),
GPIO_FN(IOIS16),
GPIO_FN(STATUS1),
GPIO_FN(STATUS0),
GPIO_FN(IRQOUT),
};
static const struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@ -526,7 +530,7 @@ static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
{ },
};
static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
static const struct pinmux_data_reg shx3_pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
0, 0, 0, 0, 0, 0, 0, 0,
PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
@ -562,19 +566,17 @@ static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
{ },
};
struct sh_pfc_soc_info shx3_pinmux_info = {
const struct sh_pfc_soc_info shx3_pinmux_info = {
.name = "shx3_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
PINMUX_INPUT_PULLUP_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PA7,
.last_gpio = GPIO_FN_STATUS0,
.gpios = shx3_pinmux_gpios,
.pins = shx3_pinmux_pins,
.nr_pins = ARRAY_SIZE(shx3_pinmux_pins),
.func_gpios = shx3_pinmux_func_gpios,
.nr_func_gpios = ARRAY_SIZE(shx3_pinmux_func_gpios),
.gpio_data = shx3_pinmux_data,
.gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
.cfg_regs = shx3_pinmux_config_regs,

512
drivers/pinctrl/sh-pfc/pinctrl.c
View file

@ -9,7 +9,6 @@
*/
#define DRV_NAME "sh-pfc"
#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt
#include <linux/device.h>
#include <linux/err.h>
@ -24,25 +23,28 @@
#include <linux/spinlock.h>
#include "core.h"
#include "../core.h"
#include "../pinconf.h"
struct sh_pfc_pin_config {
u32 type;
};
struct sh_pfc_pinctrl {
struct pinctrl_dev *pctl;
struct pinctrl_desc pctl_desc;
struct sh_pfc *pfc;
struct pinmux_gpio **functions;
unsigned int nr_functions;
struct pinctrl_pin_desc *pads;
unsigned int nr_pads;
spinlock_t lock;
struct pinctrl_pin_desc *pins;
struct sh_pfc_pin_config *configs;
};
static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
return pmx->nr_pads;
return pmx->pfc->info->nr_groups;
}
static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
@ -50,16 +52,16 @@ static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
return pmx->pads[selector].name;
return pmx->pfc->info->groups[selector].name;
}
static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
const unsigned **pins, unsigned *num_pins)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
*pins = &pmx->pads[group].number;
*num_pins = 1;
*pins = pmx->pfc->info->groups[selector].pins;
*num_pins = pmx->pfc->info->groups[selector].nr_pins;
return 0;
}
@ -70,7 +72,7 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
seq_printf(s, "%s", DRV_NAME);
}
static struct pinctrl_ops sh_pfc_pinctrl_ops = {
static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
.get_groups_count = sh_pfc_get_groups_count,
.get_group_name = sh_pfc_get_group_name,
.get_group_pins = sh_pfc_get_group_pins,
@ -81,7 +83,7 @@ static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
return pmx->nr_functions;
return pmx->pfc->info->nr_functions;
}
static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
@ -89,99 +91,75 @@ static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
return pmx->functions[selector]->name;
return pmx->pfc->info->functions[selector].name;
}
static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func,
static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
*groups = &pmx->functions[func]->name;
*num_groups = 1;
*groups = pmx->pfc->info->functions[selector].groups;
*num_groups = pmx->pfc->info->functions[selector].nr_groups;
return 0;
}
static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func,
static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
return 0;
}
static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
unsigned group)
{
}
static int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset)
{
if (sh_pfc_config_gpio(pfc, offset,
PINMUX_TYPE_FUNCTION,
GPIO_CFG_DRYRUN) != 0)
return -EINVAL;
if (sh_pfc_config_gpio(pfc, offset,
PINMUX_TYPE_FUNCTION,
GPIO_CFG_REQ) != 0)
return -EINVAL;
return 0;
}
static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
int new_type)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
unsigned long flags;
int pinmux_type;
int ret = -EINVAL;
unsigned int i;
int ret = 0;
spin_lock_irqsave(&pfc->lock, flags);
pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
for (i = 0; i < grp->nr_pins; ++i) {
int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
/*
* See if the present config needs to first be de-configured.
*/
switch (pinmux_type) {
case PINMUX_TYPE_GPIO:
break;
case PINMUX_TYPE_OUTPUT:
case PINMUX_TYPE_INPUT:
case PINMUX_TYPE_INPUT_PULLUP:
case PINMUX_TYPE_INPUT_PULLDOWN:
sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
break;
default:
goto err;
if (cfg->type != PINMUX_TYPE_NONE) {
ret = -EBUSY;
goto done;
}
}
/*
* Dry run
*/
if (sh_pfc_config_gpio(pfc, offset, new_type,
GPIO_CFG_DRYRUN) != 0)
goto err;
for (i = 0; i < grp->nr_pins; ++i) {
ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
if (ret < 0)
break;
}
/*
* Request
*/
if (sh_pfc_config_gpio(pfc, offset, new_type,
GPIO_CFG_REQ) != 0)
goto err;
pfc->info->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
pfc->info->gpios[offset].flags |= new_type;
ret = 0;
err:
done:
spin_unlock_irqrestore(&pfc->lock, flags);
return ret;
}
static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
unsigned long flags;
unsigned int i;
spin_lock_irqsave(&pfc->lock, flags);
for (i = 0; i < grp->nr_pins; ++i) {
int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
cfg->type = PINMUX_TYPE_NONE;
}
spin_unlock_irqrestore(&pfc->lock, flags);
}
static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
@ -189,36 +167,26 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
int idx = sh_pfc_get_pin_index(pfc, offset);
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
unsigned long flags;
int ret, pinmux_type;
int ret;
spin_lock_irqsave(&pfc->lock, flags);
pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
switch (pinmux_type) {
case PINMUX_TYPE_FUNCTION:
pr_notice_once("Use of GPIO API for function requests is "
"deprecated, convert to pinctrl\n");
/* handle for now */
ret = sh_pfc_config_function(pfc, offset);
if (unlikely(ret < 0))
goto err;
break;
case PINMUX_TYPE_GPIO:
case PINMUX_TYPE_INPUT:
case PINMUX_TYPE_OUTPUT:
break;
default:
pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
ret = -ENOTSUPP;
goto err;
if (cfg->type != PINMUX_TYPE_NONE) {
dev_err(pfc->dev,
"Pin %u is busy, can't configure it as GPIO.\n",
offset);
ret = -EBUSY;
goto done;
}
cfg->type = PINMUX_TYPE_GPIO;
ret = 0;
err:
done:
spin_unlock_irqrestore(&pfc->lock, flags);
return ret;
@ -230,15 +198,12 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
int idx = sh_pfc_get_pin_index(pfc, offset);
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
unsigned long flags;
int pinmux_type;
spin_lock_irqsave(&pfc->lock, flags);
pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
cfg->type = PINMUX_TYPE_NONE;
spin_unlock_irqrestore(&pfc->lock, flags);
}
@ -247,207 +212,242 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
unsigned offset, bool input)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
struct sh_pfc *pfc = pmx->pfc;
int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
int idx = sh_pfc_get_pin_index(pfc, offset);
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
unsigned long flags;
unsigned int dir;
int ret;
return sh_pfc_reconfig_pin(pmx->pfc, offset, type);
/* Check if the requested direction is supported by the pin. Not all SoC
* provide pin config data, so perform the check conditionally.
*/
if (pin->configs) {
dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
if (!(pin->configs & dir))
return -EINVAL;
}
spin_lock_irqsave(&pfc->lock, flags);
ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
if (ret < 0)
goto done;
cfg->type = new_type;
done:
spin_unlock_irqrestore(&pfc->lock, flags);
return ret;
}
static struct pinmux_ops sh_pfc_pinmux_ops = {
static const struct pinmux_ops sh_pfc_pinmux_ops = {
.get_functions_count = sh_pfc_get_functions_count,
.get_function_name = sh_pfc_get_function_name,
.get_function_groups = sh_pfc_get_function_groups,
.enable = sh_pfc_noop_enable,
.disable = sh_pfc_noop_disable,
.enable = sh_pfc_func_enable,
.disable = sh_pfc_func_disable,
.gpio_request_enable = sh_pfc_gpio_request_enable,
.gpio_disable_free = sh_pfc_gpio_disable_free,
.gpio_set_direction = sh_pfc_gpio_set_direction,
};
static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
/* Check whether the requested parameter is supported for a pin. */
static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
enum pin_config_param param)
{
int idx = sh_pfc_get_pin_index(pfc, _pin);
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
return true;
case PIN_CONFIG_BIAS_PULL_UP:
return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
case PIN_CONFIG_BIAS_PULL_DOWN:
return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
default:
return false;
}
}
static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
unsigned long *config)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
enum pin_config_param param = pinconf_to_config_param(*config);
unsigned long flags;
unsigned int bias;
*config = pfc->info->gpios[pin].flags & PINMUX_FLAG_TYPE;
if (!sh_pfc_pinconf_validate(pfc, _pin, param))
return -ENOTSUPP;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
if (!pfc->info->ops || !pfc->info->ops->get_bias)
return -ENOTSUPP;
spin_lock_irqsave(&pfc->lock, flags);
bias = pfc->info->ops->get_bias(pfc, _pin);
spin_unlock_irqrestore(&pfc->lock, flags);
if (bias != param)
return -EINVAL;
*config = 0;
break;
default:
return -ENOTSUPP;
}
return 0;
}
static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
unsigned long config)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
/* Validate the new type */
if (config >= PINMUX_FLAG_TYPE)
return -EINVAL;
return sh_pfc_reconfig_pin(pmx->pfc, pin, config);
}
static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin)
{
const char *pinmux_type_str[] = {
[PINMUX_TYPE_NONE] = "none",
[PINMUX_TYPE_FUNCTION] = "function",
[PINMUX_TYPE_GPIO] = "gpio",
[PINMUX_TYPE_OUTPUT] = "output",
[PINMUX_TYPE_INPUT] = "input",
[PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up",
[PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down",
};
unsigned long config;
int rc;
rc = sh_pfc_pinconf_get(pctldev, pin, &config);
if (unlikely(rc != 0))
return;
seq_printf(s, " %s", pinmux_type_str[config]);
}
static struct pinconf_ops sh_pfc_pinconf_ops = {
.pin_config_get = sh_pfc_pinconf_get,
.pin_config_set = sh_pfc_pinconf_set,
.pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
};
static struct pinctrl_gpio_range sh_pfc_gpio_range = {
.name = DRV_NAME,
.id = 0,
};
static struct pinctrl_desc sh_pfc_pinctrl_desc = {
.name = DRV_NAME,
.owner = THIS_MODULE,
.pctlops = &sh_pfc_pinctrl_ops,
.pmxops = &sh_pfc_pinmux_ops,
.confops = &sh_pfc_pinconf_ops,
};
static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx,
struct pinmux_gpio *gpio, unsigned offset)
{
struct pinmux_data_reg *dummy;
struct sh_pfc *pfc = pmx->pfc;
enum pin_config_param param = pinconf_to_config_param(config);
unsigned long flags;
int bit;
gpio->flags &= ~PINMUX_FLAG_TYPE;
if (!sh_pfc_pinconf_validate(pfc, _pin, param))
return -ENOTSUPP;
if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0)
gpio->flags |= PINMUX_TYPE_GPIO;
else {
gpio->flags |= PINMUX_TYPE_FUNCTION;
switch (param) {
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_DISABLE:
if (!pfc->info->ops || !pfc->info->ops->set_bias)
return -ENOTSUPP;
spin_lock_irqsave(&pmx->lock, flags);
pmx->nr_functions++;
spin_unlock_irqrestore(&pmx->lock, flags);
spin_lock_irqsave(&pfc->lock, flags);
pfc->info->ops->set_bias(pfc, _pin, param);
spin_unlock_irqrestore(&pfc->lock, flags);
break;
default:
return -ENOTSUPP;
}
return 0;
}
/* pinmux ranges -> pinctrl pin descs */
static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
unsigned long config)
{
unsigned long flags;
int i;
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
const unsigned int *pins;
unsigned int num_pins;
unsigned int i;
pmx->nr_pads = pfc->info->last_gpio - pfc->info->first_gpio + 1;
pins = pmx->pfc->info->groups[group].pins;
num_pins = pmx->pfc->info->groups[group].nr_pins;
pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads,
for (i = 0; i < num_pins; ++i)
sh_pfc_pinconf_set(pctldev, pins[i], config);
return 0;
}
static const struct pinconf_ops sh_pfc_pinconf_ops = {
.is_generic = true,
.pin_config_get = sh_pfc_pinconf_get,
.pin_config_set = sh_pfc_pinconf_set,
.pin_config_group_set = sh_pfc_pinconf_group_set,
.pin_config_config_dbg_show = pinconf_generic_dump_config,
};
/* PFC ranges -> pinctrl pin descs */
static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
const struct pinmux_range *ranges;
struct pinmux_range def_range;
unsigned int nr_ranges;
unsigned int nr_pins;
unsigned int i;
if (pfc->info->ranges == NULL) {
def_range.begin = 0;
def_range.end = pfc->info->nr_pins - 1;
ranges = &def_range;
nr_ranges = 1;
} else {
ranges = pfc->info->ranges;
nr_ranges = pfc->info->nr_ranges;
}
pmx->pins = devm_kzalloc(pfc->dev,
sizeof(*pmx->pins) * pfc->info->nr_pins,
GFP_KERNEL);
if (unlikely(!pmx->pads)) {
pmx->nr_pads = 0;
return -ENOMEM;
}
spin_lock_irqsave(&pfc->lock, flags);
/*
* We don't necessarily have a 1:1 mapping between pin and linux
* GPIO number, as the latter maps to the associated enum_id.
* Care needs to be taken to translate back to pin space when
* dealing with any pin configurations.
*/
for (i = 0; i < pmx->nr_pads; i++) {
struct pinctrl_pin_desc *pin = pmx->pads + i;
struct pinmux_gpio *gpio = pfc->info->gpios + i;
pin->number = pfc->info->first_gpio + i;
pin->name = gpio->name;
/* XXX */
if (unlikely(!gpio->enum_id))
continue;
sh_pfc_map_one_gpio(pfc, pmx, gpio, i);
}
spin_unlock_irqrestore(&pfc->lock, flags);
sh_pfc_pinctrl_desc.pins = pmx->pads;
sh_pfc_pinctrl_desc.npins = pmx->nr_pads;
return 0;
}
static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
unsigned long flags;
int i, fn;
pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions *
sizeof(*pmx->functions), GFP_KERNEL);
if (unlikely(!pmx->functions))
if (unlikely(!pmx->pins))
return -ENOMEM;
spin_lock_irqsave(&pmx->lock, flags);
pmx->configs = devm_kzalloc(pfc->dev,
sizeof(*pmx->configs) * pfc->info->nr_pins,
GFP_KERNEL);
if (unlikely(!pmx->configs))
return -ENOMEM;
for (i = fn = 0; i < pmx->nr_pads; i++) {
struct pinmux_gpio *gpio = pfc->info->gpios + i;
for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
const struct pinmux_range *range = &ranges[i];
unsigned int number;
if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
pmx->functions[fn++] = gpio;
for (number = range->begin; number <= range->end;
number++, nr_pins++) {
struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
const struct sh_pfc_pin *info =
&pfc->info->pins[nr_pins];
pin->number = number;
pin->name = info->name;
cfg->type = PINMUX_TYPE_NONE;
}
}
spin_unlock_irqrestore(&pmx->lock, flags);
pfc->nr_pins = ranges[nr_ranges-1].end + 1;
return 0;
return nr_ranges;
}
int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
{
struct sh_pfc_pinctrl *pmx;
int ret;
int nr_ranges;
pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
if (unlikely(!pmx))
return -ENOMEM;
spin_lock_init(&pmx->lock);
pmx->pfc = pfc;
pfc->pinctrl = pmx;
ret = sh_pfc_map_gpios(pfc, pmx);
if (unlikely(ret != 0))
return ret;
nr_ranges = sh_pfc_map_pins(pfc, pmx);
if (unlikely(nr_ranges < 0))
return nr_ranges;
ret = sh_pfc_map_functions(pfc, pmx);
if (unlikely(ret != 0))
return ret;
pmx->pctl_desc.name = DRV_NAME;
pmx->pctl_desc.owner = THIS_MODULE;
pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
pmx->pctl_desc.pins = pmx->pins;
pmx->pctl_desc.npins = pfc->info->nr_pins;
pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, pfc->dev, pmx);
if (IS_ERR(pmx->pctl))
return PTR_ERR(pmx->pctl);
sh_pfc_gpio_range.npins = pfc->info->last_gpio
- pfc->info->first_gpio + 1;
sh_pfc_gpio_range.base = pfc->info->first_gpio;
sh_pfc_gpio_range.pin_base = pfc->info->first_gpio;
pinctrl_add_gpio_range(pmx->pctl, &sh_pfc_gpio_range);
pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
if (pmx->pctl == NULL)
return -EINVAL;
return 0;
}

135
drivers/pinctrl/sh-pfc/sh_pfc.h
View file

@ -15,7 +15,8 @@
#include <asm-generic/gpio.h>
typedef unsigned short pinmux_enum_t;
typedef unsigned short pinmux_flag_t;
#define SH_PFC_MARK_INVALID ((pinmux_enum_t)-1)
enum {
PINMUX_TYPE_NONE,
@ -30,44 +31,81 @@ enum {
PINMUX_FLAG_TYPE, /* must be last */
};
#define PINMUX_FLAG_DBIT_SHIFT 5
#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT)
#define PINMUX_FLAG_DREG_SHIFT 10
#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT)
#define SH_PFC_PIN_CFG_INPUT (1 << 0)
#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
struct pinmux_gpio {
pinmux_enum_t enum_id;
pinmux_flag_t flags;
struct sh_pfc_pin {
const pinmux_enum_t enum_id;
const char *name;
unsigned int configs;
};
#define SH_PFC_PIN_GROUP(n) \
{ \
.name = #n, \
.pins = n##_pins, \
.mux = n##_mux, \
.nr_pins = ARRAY_SIZE(n##_pins), \
}
struct sh_pfc_pin_group {
const char *name;
const unsigned int *pins;
const unsigned int *mux;
unsigned int nr_pins;
};
#define SH_PFC_FUNCTION(n) \
{ \
.name = #n, \
.groups = n##_groups, \
.nr_groups = ARRAY_SIZE(n##_groups), \
}
struct sh_pfc_function {
const char *name;
const char * const *groups;
unsigned int nr_groups;
};
struct pinmux_func {
const pinmux_enum_t enum_id;
const char *name;
};
#define PINMUX_GPIO(gpio, data_or_mark) \
[gpio] = { .name = __stringify(gpio), .enum_id = data_or_mark, .flags = PINMUX_TYPE_NONE }
#define PINMUX_GPIO(gpio, data_or_mark) \
[gpio] = { \
.name = __stringify(gpio), \
.enum_id = data_or_mark, \
}
#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
[gpio - (base)] = { \
.name = __stringify(gpio), \
.enum_id = data_or_mark, \
}
#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
struct pinmux_cfg_reg {
unsigned long reg, reg_width, field_width;
unsigned long *cnt;
pinmux_enum_t *enum_ids;
unsigned long *var_field_width;
const pinmux_enum_t *enum_ids;
const unsigned long *var_field_width;
};
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
.reg = r, .reg_width = r_width, .field_width = f_width, \
.cnt = (unsigned long [r_width / f_width]) {}, \
.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
.reg = r, .reg_width = r_width, \
.cnt = (unsigned long [r_width]) {}, \
.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
.enum_ids = (pinmux_enum_t [])
struct pinmux_data_reg {
unsigned long reg, reg_width, reg_shadow;
pinmux_enum_t *enum_ids;
void __iomem *mapped_reg;
unsigned long reg, reg_width;
const pinmux_enum_t *enum_ids;
};
#define PINMUX_DATA_REG(name, r, r_width) \
@ -76,11 +114,11 @@ struct pinmux_data_reg {
struct pinmux_irq {
int irq;
pinmux_enum_t *enum_ids;
unsigned short *gpios;
};
#define PINMUX_IRQ(irq_nr, ids...) \
{ .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } } \
{ .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \
struct pinmux_range {
pinmux_enum_t begin;
@ -88,33 +126,49 @@ struct pinmux_range {
pinmux_enum_t force;
};
struct sh_pfc;
struct sh_pfc_soc_operations {
unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias);
};
struct sh_pfc_soc_info {
char *name;
pinmux_enum_t reserved_id;
struct pinmux_range data;
const char *name;
const struct sh_pfc_soc_operations *ops;
struct pinmux_range input;
struct pinmux_range input_pd;
struct pinmux_range input_pu;
struct pinmux_range output;
struct pinmux_range mark;
struct pinmux_range function;
unsigned first_gpio, last_gpio;
const struct sh_pfc_pin *pins;
unsigned int nr_pins;
const struct pinmux_range *ranges;
unsigned int nr_ranges;
const struct sh_pfc_pin_group *groups;
unsigned int nr_groups;
const struct sh_pfc_function *functions;
unsigned int nr_functions;
struct pinmux_gpio *gpios;
struct pinmux_cfg_reg *cfg_regs;
struct pinmux_data_reg *data_regs;
const struct pinmux_func *func_gpios;
unsigned int nr_func_gpios;
pinmux_enum_t *gpio_data;
const struct pinmux_cfg_reg *cfg_regs;
const struct pinmux_data_reg *data_regs;
const pinmux_enum_t *gpio_data;
unsigned int gpio_data_size;
struct pinmux_irq *gpio_irq;
const struct pinmux_irq *gpio_irq;
unsigned int gpio_irq_size;
unsigned long unlock_reg;
};
enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
enum { GPIO_CFG_REQ, GPIO_CFG_FREE };
/* helper macro for port */
#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
@ -126,6 +180,23 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
#define PORT_10_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
#define PORT_32(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
PORT_1(fn, pfx##31, sfx)
#define PORT_32_REV(fn, pfx, sfx) \
PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
PORT_10_REV(fn, pfx, sfx)
#define PORT_90(fn, pfx, sfx) \
PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
@ -137,7 +208,7 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
/* helper macro for pinmux_enum_t */
#define PORT_DATA_I(nr) \