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pinctrl: rockchip: fix offset of mux registers for rk3188

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The correct value of .mux_offset for rk3188 seems to be 0x60
instead of 0x68.

Heiko adds:

GPIO0 only has the second two IOMUX registers:
- GRF_GPIO0C_IOMUX at 0x68
- GRF_GPIO0D_IOMUX at 0x6c
which I guess is where my mistake comes from.

It looks like there does no iomux register exist at all
for the first 16 pins.

In any case, the current number is wrong, and the 0x60
offset is the correct one, but I guess we need to
determine what the affected pins do - do they always have a
gpio mux or such?

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Beniamino Galvani 2014-03-24 23:36:01 +01:00 committed by Linus Walleij
parent c9eaa447e7
commit 22c0d7e36f
1 changed files with 1 additions and 1 deletions
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2
drivers/pinctrl/pinctrl-rockchip.c
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@ -1534,7 +1534,7 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
.label = "RK3188-GPIO",
.type = RK3188,
.mux_offset = 0x68,
.mux_offset = 0x60,
.pull_calc_reg = rk3188_calc_pull_reg_and_bit,
};