mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 01:10:04 +00:00
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] Replace 40c7869b69
kludge
[MIPS] Lasat: Fix built in separate object directory.
[MIPS] Malta: Fix software reset on big endian
[MIPS] pnx8xxx: move to clocksource
[MIPS] Wrong CONFIG option prevents setup of DMA zone.
This commit is contained in:
commit
22fb53c943
6 changed files with 85 additions and 51 deletions
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@ -269,7 +269,7 @@ static void __init bootmem_init(void)
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static void __init bootmem_init(void)
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{
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unsigned long init_begin, reserved_end;
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unsigned long reserved_end;
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unsigned long mapstart = ~0UL;
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unsigned long bootmap_size;
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int i;
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@ -344,7 +344,6 @@ static void __init bootmem_init(void)
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min_low_pfn, max_low_pfn);
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init_begin = PFN_UP(__pa_symbol(&__init_begin));
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for (i = 0; i < boot_mem_map.nr_map; i++) {
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unsigned long start, end;
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@ -352,8 +351,8 @@ static void __init bootmem_init(void)
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end = PFN_DOWN(boot_mem_map.map[i].addr
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+ boot_mem_map.map[i].size);
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if (start <= init_begin)
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start = init_begin;
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if (start <= min_low_pfn)
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start = min_low_pfn;
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if (start >= end)
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continue;
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@ -12,11 +12,11 @@ endif
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MKLASATIMG = mklasatimg
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MKLASATIMG_ARCH = mq2,mqpro,sp100,sp200
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KERNEL_IMAGE = $(TOPDIR)/vmlinux
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KERNEL_IMAGE = vmlinux
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KERNEL_START = $(shell $(NM) $(KERNEL_IMAGE) | grep " _text" | cut -f1 -d\ )
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KERNEL_ENTRY = $(shell $(NM) $(KERNEL_IMAGE) | grep kernel_entry | cut -f1 -d\ )
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LDSCRIPT= -L$(obj) -Tromscript.normal
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LDSCRIPT= -L$(srctree)/$(src) -Tromscript.normal
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HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \
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-D_kernel_entry=0x$(KERNEL_ENTRY) \
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@ -24,7 +24,7 @@ HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \
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-D TIMESTAMP=$(shell date +%s)
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$(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE)
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$(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $<
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$(CC) -fno-pic $(HEAD_DEFINES) $(LINUXINCLUDE) -c -o $@ $<
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OBJECTS = head.o kImage.o
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@ -169,7 +169,6 @@ void __init prom_meminit(void)
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void __init prom_free_prom_memory(void)
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{
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#if 0 /* for now ... */
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unsigned long addr;
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int i;
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@ -181,5 +180,4 @@ void __init prom_free_prom_memory(void)
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free_init_pages("prom memory",
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addr, addr + boot_mem_map.map[i].size);
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}
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#endif
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}
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@ -39,16 +39,18 @@ static void atlas_machine_power_off(void);
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static void mips_machine_restart(char *command)
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{
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unsigned int __iomem *softres_reg = ioremap(SOFTRES_REG, sizeof(unsigned int));
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unsigned int __iomem *softres_reg =
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ioremap(SOFTRES_REG, sizeof(unsigned int));
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writew(GORESET, softres_reg);
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__raw_writel(GORESET, softres_reg);
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}
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static void mips_machine_halt(void)
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{
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unsigned int __iomem *softres_reg = ioremap(SOFTRES_REG, sizeof(unsigned int));
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unsigned int __iomem *softres_reg =
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ioremap(SOFTRES_REG, sizeof(unsigned int));
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writew(GORESET, softres_reg);
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__raw_writel(GORESET, softres_reg);
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}
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#if defined(CONFIG_MIPS_ATLAS)
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@ -45,7 +45,7 @@ static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp)
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/* ignore region specifiers */
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gfp &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
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#ifdef CONFIG_ZONE_DMA32
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#ifdef CONFIG_ZONE_DMA
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if (dev == NULL)
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gfp |= __GFP_DMA;
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else if (dev->coherent_dma_mask < DMA_BIT_MASK(24))
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@ -22,7 +22,6 @@
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#include <linux/kernel_stat.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/bootinfo.h>
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#include <asm/cpu.h>
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@ -41,11 +40,60 @@ static cycle_t hpt_read(void)
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return read_c0_count2();
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}
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static struct clocksource pnx_clocksource = {
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.name = "pnx8xxx",
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.rating = 200,
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.read = hpt_read,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void timer_ack(void)
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{
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write_c0_compare(cpj);
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}
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static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *c = dev_id;
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/* clear MATCH, signal the event */
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c->event_handler(c);
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return IRQ_HANDLED;
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}
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static struct irqaction pnx8xxx_timer_irq = {
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.handler = pnx8xxx_timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_PERCPU,
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.name = "pnx8xxx_timer",
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};
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static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
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{
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/* Timer 2 clear interrupt */
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write_c0_compare2(-1);
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return IRQ_HANDLED;
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}
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static struct irqaction monotonic_irqaction = {
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.handler = monotonic_interrupt,
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.flags = IRQF_DISABLED,
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.name = "Monotonic timer",
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};
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static int pnx8xxx_set_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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write_c0_compare(delta);
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return 0;
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}
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static struct clock_event_device pnx8xxx_clockevent = {
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.name = "pnx8xxx_clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = pnx8xxx_set_next_event,
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};
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/*
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* plat_time_init() - it does the following things:
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*
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@ -58,11 +106,34 @@ static void timer_ack(void)
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__init void plat_time_init(void)
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{
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unsigned int configPR;
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unsigned int n;
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unsigned int m;
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unsigned int p;
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unsigned int pow2p;
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clockevents_register_device(&pnx8xxx_clockevent);
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clocksource_register(&pnx_clocksource);
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setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq);
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setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
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/* Timer 1 start */
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configPR = read_c0_config7();
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configPR &= ~0x00000008;
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write_c0_config7(configPR);
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/* Timer 2 start */
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configPR = read_c0_config7();
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configPR &= ~0x00000010;
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write_c0_config7(configPR);
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/* Timer 3 stop */
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configPR = read_c0_config7();
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configPR |= 0x00000020;
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write_c0_config7(configPR);
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/* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */
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/* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1: FIXME) */
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@ -87,42 +158,6 @@ __init void plat_time_init(void)
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write_c0_count2(0);
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write_c0_compare2(0xffffffff);
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clocksource_mips.read = hpt_read;
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mips_timer_ack = timer_ack;
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}
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static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
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{
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/* Timer 2 clear interrupt */
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write_c0_compare2(-1);
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return IRQ_HANDLED;
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}
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static struct irqaction monotonic_irqaction = {
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.handler = monotonic_interrupt,
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.flags = IRQF_DISABLED,
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.name = "Monotonic timer",
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};
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void __init plat_timer_setup(struct irqaction *irq)
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{
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int configPR;
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setup_irq(PNX8550_INT_TIMER1, irq);
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setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
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/* Timer 1 start */
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configPR = read_c0_config7();
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configPR &= ~0x00000008;
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write_c0_config7(configPR);
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/* Timer 2 start */
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configPR = read_c0_config7();
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configPR &= ~0x00000010;
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write_c0_config7(configPR);
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/* Timer 3 stop */
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configPR = read_c0_config7();
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configPR |= 0x00000020;
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write_c0_config7(configPR);
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}
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