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scsi: cxlflash: Setup LISNs for user contexts

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The SISLite specification has been updated for OCXL to support communicating
data to generate AFU interrupts to the AFU. This includes a new capability bit
that is advertised for OCXL AFUs and new registers to hold the object handle
and translation PASID of each interrupt. For Power, the object handle is the
mapped trigger page. Note that because these mappings are kernel only, the
PASID of a kernel context must be used to satisfy the translation.

Signed-off-by: Uma Krishnan <ukrishn@linux.vnet.ibm.com>
Acked-by: Matthew R. Ochs <mrochs@linux.vnet.ibm.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Uma Krishnan 2018-03-26 11:34:42 -05:00 committed by Martin K. Petersen
parent 402a55ea47
commit 23239eeccb
3 changed files with 24 additions and 0 deletions
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5
drivers/scsi/cxlflash/common.h
View file

@ -273,6 +273,11 @@ static inline bool afu_has_cap(struct afu *afu, u64 cap)
return afu_cap & cap;
}
static inline bool afu_is_ocxl_lisn(struct afu *afu)
{
return afu_has_cap(afu, SISL_INTVER_CAP_OCXL_LISN);
}
static inline bool afu_is_afu_debug(struct afu *afu)
{
return afu_has_cap(afu, SISL_INTVER_CAP_AFU_DEBUG);

5
drivers/scsi/cxlflash/sislite.h
View file

@ -310,6 +310,10 @@ struct sisl_ctrl_map {
#define SISL_CTX_CAP_WRITE_CMD 0x0000000000000002ULL /* afu_rc 0x21 */
#define SISL_CTX_CAP_READ_CMD 0x0000000000000001ULL /* afu_rc 0x21 */
__be64 mbox_r;
__be64 lisn_pasid[2];
/* pasid _a arg must be ULL */
#define SISL_LISN_PASID(_a, _b) (((_a) << 32) | (_b))
__be64 lisn_ea[3];
};
/* single copy global regs */
@ -416,6 +420,7 @@ struct sisl_global_regs {
#define SISL_INTVER_CAP_RESERVED_CMD_MODE_B 0x100000000000ULL
#define SISL_INTVER_CAP_LUN_PROVISION 0x080000000000ULL
#define SISL_INTVER_CAP_AFU_DEBUG 0x040000000000ULL
#define SISL_INTVER_CAP_OCXL_LISN 0x020000000000ULL
};
#define CXLFLASH_NUM_FC_PORTS_PER_BANK 2 /* fixed # of ports per bank */

14
drivers/scsi/cxlflash/superpipe.c
View file

@ -269,6 +269,7 @@ static int afu_attach(struct cxlflash_cfg *cfg, struct ctx_info *ctxi)
int rc = 0;
struct hwq *hwq = get_hwq(afu, PRIMARY_HWQ);
u64 val;
int i;
/* Unlock cap and restrict user to read/write cmds in translated mode */
readq_be(&ctrl_map->mbox_r);
@ -282,6 +283,19 @@ static int afu_attach(struct cxlflash_cfg *cfg, struct ctx_info *ctxi)
goto out;
}
if (afu_is_ocxl_lisn(afu)) {
/* Set up the LISN effective address for each interrupt */
for (i = 0; i < ctxi->irqs; i++) {
val = cfg->ops->get_irq_objhndl(ctxi->ctx, i);
writeq_be(val, &ctrl_map->lisn_ea[i]);
}
/* Use primary HWQ PASID as identifier for all interrupts */
val = hwq->ctx_hndl;
writeq_be(SISL_LISN_PASID(val, val), &ctrl_map->lisn_pasid[0]);
writeq_be(SISL_LISN_PASID(0UL, val), &ctrl_map->lisn_pasid[1]);
}
/* Set up MMIO registers pointing to the RHT */
writeq_be((u64)ctxi->rht_start, &ctrl_map->rht_start);
val = SISL_RHT_CNT_ID((u64)MAX_RHT_PER_CONTEXT, (u64)(hwq->ctx_hndl));