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net/mlx4_core: Use firmware driven flow steering hash mode
The Firmware dynamically changes flow steering hash configuration from covering L2 only to "full" L2/L3/L4 mode needed. The dynamic change allows the driver to set hard coded hash configuration which is changed by the firmware from L2 to L2/L3/L4 when attaching the first L3/L4 flow steering rule and back to L2 when there are no more such rules. Signed-off-by: Hadar Hen Zion <hadarh@mellanox.com> Signed-off-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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0d256c0e93
commit
23537b732f
4 changed files with 2 additions and 24 deletions
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@ -1287,14 +1287,14 @@ int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
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/* Enable Ethernet flow steering
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* with udp unicast and tcp unicast
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*/
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MLX4_PUT(inbox, param->fs_hash_enable_bits,
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MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
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INIT_HCA_FS_ETH_BITS_OFFSET);
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MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
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INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
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/* Enable IPoIB flow steering
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* with udp unicast and tcp unicast
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*/
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MLX4_PUT(inbox, param->fs_hash_enable_bits,
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MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
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INIT_HCA_FS_IB_BITS_OFFSET);
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MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
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INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
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@ -171,7 +171,6 @@ struct mlx4_init_hca_param {
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u8 log_mpt_sz;
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u8 log_uar_sz;
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u8 uar_page_sz; /* log pg sz in 4k chunks */
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u8 fs_hash_enable_bits;
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u8 steering_mode; /* for QUERY_HCA */
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u64 dev_cap_enabled;
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};
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@ -1415,22 +1415,6 @@ static int mlx4_init_hca(struct mlx4_dev *dev)
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if (mlx4_is_master(dev))
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mlx4_parav_master_pf_caps(dev);
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priv->fs_hash_mode = MLX4_FS_L2_HASH;
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switch (priv->fs_hash_mode) {
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case MLX4_FS_L2_HASH:
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init_hca.fs_hash_enable_bits = 0;
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break;
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case MLX4_FS_L2_L3_L4_HASH:
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/* Enable flow steering with
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* udp unicast and tcp unicast
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*/
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init_hca.fs_hash_enable_bits =
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MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN;
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break;
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}
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profile = default_profile;
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if (dev->caps.steering_mode ==
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MLX4_STEERING_MODE_DEVICE_MANAGED)
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@ -60,11 +60,6 @@
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#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
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#define MLX4_FS_NUM_MCG (1 << 17)
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enum {
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MLX4_FS_L2_HASH = 0,
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MLX4_FS_L2_L3_L4_HASH,
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};
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#define MLX4_NUM_UP 8
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#define MLX4_NUM_TC 8
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#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
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