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drm/amdgpu: fix VCE buffer placement restrictions v2
Turned out that VCE still has a placement restriction that BOs can't cross a 4GB boundary. Fix this by adding a command submission parser prepass to correctly place the buffers. v2: add function description Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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235943189d
1 changed files with 99 additions and 2 deletions
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@ -543,6 +543,54 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
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return r;
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}
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/**
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* amdgpu_vce_cs_validate_bo - make sure not to cross 4GB boundary
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*
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* @p: parser context
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* @lo: address of lower dword
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* @hi: address of higher dword
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* @size: minimum size
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* @index: bs/fb index
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*
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* Make sure that no BO cross a 4GB boundary.
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*/
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static int amdgpu_vce_validate_bo(struct amdgpu_cs_parser *p, uint32_t ib_idx,
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int lo, int hi, unsigned size, int32_t index)
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{
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int64_t offset = ((uint64_t)size) * ((int64_t)index);
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struct amdgpu_bo_va_mapping *mapping;
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unsigned i, fpfn, lpfn;
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struct amdgpu_bo *bo;
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uint64_t addr;
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int r;
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addr = ((uint64_t)amdgpu_get_ib_value(p, ib_idx, lo)) |
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((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
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if (index >= 0) {
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addr += offset;
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fpfn = PAGE_ALIGN(offset) >> PAGE_SHIFT;
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lpfn = 0x100000000ULL >> PAGE_SHIFT;
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} else {
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fpfn = 0;
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lpfn = (0x100000000ULL - PAGE_ALIGN(offset)) >> PAGE_SHIFT;
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}
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r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
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if (r) {
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DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
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addr, lo, hi, size, index);
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return r;
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}
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for (i = 0; i < bo->placement.num_placement; ++i) {
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bo->placements[i].fpfn = max(bo->placements[i].fpfn, fpfn);
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bo->placements[i].lpfn = bo->placements[i].fpfn ?
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min(bo->placements[i].fpfn, lpfn) : lpfn;
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}
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return ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
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}
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/**
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* amdgpu_vce_cs_reloc - command submission relocation
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*
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@ -648,12 +696,13 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
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uint32_t allocated = 0;
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uint32_t tmp, handle = 0;
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uint32_t *size = &tmp;
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int i, r = 0, idx = 0;
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unsigned idx;
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int i, r = 0;
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p->job->vm = NULL;
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ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
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while (idx < ib->length_dw) {
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for (idx = 0; idx < ib->length_dw;) {
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uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
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uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
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@ -663,6 +712,54 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
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goto out;
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}
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switch (cmd) {
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case 0x00000002: /* task info */
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fb_idx = amdgpu_get_ib_value(p, ib_idx, idx + 6);
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bs_idx = amdgpu_get_ib_value(p, ib_idx, idx + 7);
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break;
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case 0x03000001: /* encode */
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r = amdgpu_vce_validate_bo(p, ib_idx, idx + 10,
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idx + 9, 0, 0);
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if (r)
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goto out;
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r = amdgpu_vce_validate_bo(p, ib_idx, idx + 12,
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idx + 11, 0, 0);
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if (r)
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goto out;
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break;
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case 0x05000001: /* context buffer */
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r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3,
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idx + 2, 0, 0);
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if (r)
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goto out;
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break;
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case 0x05000004: /* video bitstream buffer */
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tmp = amdgpu_get_ib_value(p, ib_idx, idx + 4);
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r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
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tmp, bs_idx);
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if (r)
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goto out;
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break;
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case 0x05000005: /* feedback buffer */
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r = amdgpu_vce_validate_bo(p, ib_idx, idx + 3, idx + 2,
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4096, fb_idx);
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if (r)
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goto out;
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break;
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}
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idx += len / 4;
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}
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for (idx = 0; idx < ib->length_dw;) {
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uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
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uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
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switch (cmd) {
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case 0x00000001: /* session */
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handle = amdgpu_get_ib_value(p, ib_idx, idx + 2);
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