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ARM: imx6sl: Add missing pll4_audio_div to the clock tree
There's a dividor for pll4_audio clock missing in clock tree, thus add it. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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4390e62260
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2 changed files with 5 additions and 3 deletions
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@ -29,14 +29,14 @@ static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf"
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static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
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static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
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static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
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static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", };
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static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
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static const char const *perclk_sels[] = { "ipg", "osc", };
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static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
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static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
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static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
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static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
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static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
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static const char const *audio_sels[] = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
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static const char const *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
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static const char const *ecspi_sels[] = { "pll3_60m", "osc", };
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static const char const *uart_sels[] = { "pll3_80m", "osc", };
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@ -104,6 +104,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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/* dev name parent_name flags reg shift width div: flags, div_table lock */
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clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
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clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
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clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
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clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
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clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
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@ -143,6 +143,7 @@
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#define IMX6SL_CLK_USDHC2 130
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#define IMX6SL_CLK_USDHC3 131
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#define IMX6SL_CLK_USDHC4 132
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#define IMX6SL_CLK_END 133
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#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
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#define IMX6SL_CLK_END 134
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#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
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