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drm/i915/display: Implement new combo phy initialization step
This is new step that was recently added to the combo phy initialization. v2: - using intel_de_rmw() v3: - going back to read() modify and write() as group register can't be read BSpec: 49291 Cc: Clinton A Taylor <clinton.a.taylor@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200625195252.39312-1-jose.souza@intel.com
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2 changed files with 34 additions and 0 deletions
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@ -264,6 +264,18 @@ static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
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if (!icl_combo_phy_enabled(dev_priv, phy))
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return false;
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if (INTEL_GEN(dev_priv) >= 12) {
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ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN0(phy),
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ICL_PORT_TX_DW8_ODCC_CLK_SEL |
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ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK,
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ICL_PORT_TX_DW8_ODCC_CLK_SEL |
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ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2);
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ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN0(phy),
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DCC_MODE_SELECT_MASK,
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DCC_MODE_SELECT_CONTINUOSLY);
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}
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ret = cnl_verify_procmon_ref_values(dev_priv, phy);
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if (phy_is_master(dev_priv, phy)) {
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@ -375,6 +387,19 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
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intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);
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skip_phy_misc:
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if (INTEL_GEN(dev_priv) >= 12) {
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val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN0(phy));
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val &= ~ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK;
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val |= ICL_PORT_TX_DW8_ODCC_CLK_SEL;
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val |= ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2;
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intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val);
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val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
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val &= ~DCC_MODE_SELECT_MASK;
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val |= DCC_MODE_SELECT_CONTINUOSLY;
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intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
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}
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cnl_set_procmon_ref_values(dev_priv, phy);
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if (phy_is_master(dev_priv, phy)) {
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@ -1974,6 +1974,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
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#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
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#define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
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#define DCC_MODE_SELECT_MASK (0x3 << 20)
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#define DCC_MODE_SELECT_CONTINUOSLY (0x3 << 20)
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#define COMMON_KEEPER_EN (1 << 26)
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#define LATENCY_OPTIM_MASK (0x3 << 2)
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#define LATENCY_OPTIM_VAL(x) ((x) << 2)
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@ -2072,6 +2074,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define N_SCALAR(x) ((x) << 24)
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#define N_SCALAR_MASK (0x7F << 24)
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#define ICL_PORT_TX_DW8_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(8, phy))
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#define ICL_PORT_TX_DW8_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(8, phy))
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#define ICL_PORT_TX_DW8_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(8, 0, phy))
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#define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
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#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK REG_GENMASK(30, 29)
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#define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MASK, 0x1)
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#define _ICL_DPHY_CHKN_REG 0x194
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#define ICL_DPHY_CHKN(port) _MMIO(_ICL_COMBOPHY(port) + _ICL_DPHY_CHKN_REG)
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#define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
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