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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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linux-watchdog 4.16-fixes-2 merge window tag
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.14 (GNU/Linux) iEYEABECAAYFAlqjrhoACgkQ+iyteGJfRsqqSACfS2mtTsPzvxofsaKjlUgG0PUu GtEAoKNM20k8Ni145/eCeosboYspForw =8Tgb -----END PGP SIGNATURE----- Merge tag 'linux-watchdog-4.16-fixes-2' of git://www.linux-watchdog.org/linux-watchdog Pull watchdog fixes from Wim Van Sebroeck: - f71808e_wdt: Fix magic close handling - sbsa: 32-bit read fix for WCV - hpwdt: Remove legacy NMI sourcing * tag 'linux-watchdog-4.16-fixes-2' of git://www.linux-watchdog.org/linux-watchdog: watchdog: hpwdt: Remove legacy NMI sourcing. watchdog: sbsa: use 32-bit read for WCV watchdog: f71808e_wdt: Fix magic close handling
This commit is contained in:
commit
23b33acc5f
3 changed files with 15 additions and 496 deletions
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@ -566,7 +566,8 @@ static ssize_t watchdog_write(struct file *file, const char __user *buf,
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char c;
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if (get_user(c, buf + i))
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return -EFAULT;
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expect_close = (c == 'V');
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if (c == 'V')
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expect_close = true;
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}
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/* Properly order writes across fork()ed processes */
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@ -28,16 +28,7 @@
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#include <linux/types.h>
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#include <linux/uaccess.h>
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#include <linux/watchdog.h>
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#ifdef CONFIG_HPWDT_NMI_DECODING
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#include <linux/dmi.h>
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#include <linux/spinlock.h>
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#include <linux/nmi.h>
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#include <linux/kdebug.h>
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#include <linux/notifier.h>
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#include <asm/set_memory.h>
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#endif /* CONFIG_HPWDT_NMI_DECODING */
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#include <asm/nmi.h>
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#include <asm/frame.h>
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#define HPWDT_VERSION "1.4.0"
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#define SECS_TO_TICKS(secs) ((secs) * 1000 / 128)
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@ -48,6 +39,9 @@
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static unsigned int soft_margin = DEFAULT_MARGIN; /* in seconds */
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static unsigned int reload; /* the computed soft_margin */
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static bool nowayout = WATCHDOG_NOWAYOUT;
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#ifdef CONFIG_HPWDT_NMI_DECODING
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static unsigned int allow_kdump = 1;
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#endif
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static char expect_release;
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static unsigned long hpwdt_is_open;
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@ -63,373 +57,6 @@ static const struct pci_device_id hpwdt_devices[] = {
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};
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MODULE_DEVICE_TABLE(pci, hpwdt_devices);
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#ifdef CONFIG_HPWDT_NMI_DECODING
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#define PCI_BIOS32_SD_VALUE 0x5F32335F /* "_32_" */
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#define CRU_BIOS_SIGNATURE_VALUE 0x55524324
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#define PCI_BIOS32_PARAGRAPH_LEN 16
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#define PCI_ROM_BASE1 0x000F0000
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#define ROM_SIZE 0x10000
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struct bios32_service_dir {
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u32 signature;
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u32 entry_point;
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u8 revision;
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u8 length;
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u8 checksum;
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u8 reserved[5];
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};
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/* type 212 */
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struct smbios_cru64_info {
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u8 type;
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u8 byte_length;
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u16 handle;
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u32 signature;
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u64 physical_address;
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u32 double_length;
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u32 double_offset;
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};
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#define SMBIOS_CRU64_INFORMATION 212
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/* type 219 */
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struct smbios_proliant_info {
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u8 type;
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u8 byte_length;
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u16 handle;
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u32 power_features;
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u32 omega_features;
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u32 reserved;
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u32 misc_features;
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};
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#define SMBIOS_ICRU_INFORMATION 219
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struct cmn_registers {
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union {
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struct {
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u8 ral;
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u8 rah;
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u16 rea2;
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};
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u32 reax;
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} u1;
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union {
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struct {
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u8 rbl;
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u8 rbh;
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u8 reb2l;
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u8 reb2h;
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};
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u32 rebx;
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} u2;
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union {
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struct {
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u8 rcl;
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u8 rch;
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u16 rec2;
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};
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u32 recx;
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} u3;
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union {
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struct {
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u8 rdl;
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u8 rdh;
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u16 red2;
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};
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u32 redx;
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} u4;
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u32 resi;
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u32 redi;
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u16 rds;
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u16 res;
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u32 reflags;
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} __attribute__((packed));
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static unsigned int hpwdt_nmi_decoding;
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static unsigned int allow_kdump = 1;
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static unsigned int is_icru;
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static unsigned int is_uefi;
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static DEFINE_SPINLOCK(rom_lock);
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static void *cru_rom_addr;
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static struct cmn_registers cmn_regs;
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extern asmlinkage void asminline_call(struct cmn_registers *pi86Regs,
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unsigned long *pRomEntry);
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#ifdef CONFIG_X86_32
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/* --32 Bit Bios------------------------------------------------------------ */
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#define HPWDT_ARCH 32
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asm(".text \n\t"
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".align 4 \n\t"
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".globl asminline_call \n"
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"asminline_call: \n\t"
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"pushl %ebp \n\t"
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"movl %esp, %ebp \n\t"
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"pusha \n\t"
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"pushf \n\t"
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"push %es \n\t"
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"push %ds \n\t"
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"pop %es \n\t"
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"movl 8(%ebp),%eax \n\t"
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"movl 4(%eax),%ebx \n\t"
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"movl 8(%eax),%ecx \n\t"
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"movl 12(%eax),%edx \n\t"
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"movl 16(%eax),%esi \n\t"
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"movl 20(%eax),%edi \n\t"
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"movl (%eax),%eax \n\t"
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"push %cs \n\t"
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"call *12(%ebp) \n\t"
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"pushf \n\t"
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"pushl %eax \n\t"
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"movl 8(%ebp),%eax \n\t"
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"movl %ebx,4(%eax) \n\t"
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"movl %ecx,8(%eax) \n\t"
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"movl %edx,12(%eax) \n\t"
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"movl %esi,16(%eax) \n\t"
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"movl %edi,20(%eax) \n\t"
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"movw %ds,24(%eax) \n\t"
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"movw %es,26(%eax) \n\t"
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"popl %ebx \n\t"
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"movl %ebx,(%eax) \n\t"
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"popl %ebx \n\t"
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"movl %ebx,28(%eax) \n\t"
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"pop %es \n\t"
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"popf \n\t"
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"popa \n\t"
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"leave \n\t"
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"ret \n\t"
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".previous");
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/*
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* cru_detect
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*
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* Routine Description:
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* This function uses the 32-bit BIOS Service Directory record to
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* search for a $CRU record.
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*
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* Return Value:
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* 0 : SUCCESS
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* <0 : FAILURE
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*/
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static int cru_detect(unsigned long map_entry,
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unsigned long map_offset)
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{
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void *bios32_map;
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unsigned long *bios32_entrypoint;
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unsigned long cru_physical_address;
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unsigned long cru_length;
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unsigned long physical_bios_base = 0;
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unsigned long physical_bios_offset = 0;
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int retval = -ENODEV;
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bios32_map = ioremap(map_entry, (2 * PAGE_SIZE));
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if (bios32_map == NULL)
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return -ENODEV;
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bios32_entrypoint = bios32_map + map_offset;
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cmn_regs.u1.reax = CRU_BIOS_SIGNATURE_VALUE;
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set_memory_x((unsigned long)bios32_map, 2);
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asminline_call(&cmn_regs, bios32_entrypoint);
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if (cmn_regs.u1.ral != 0) {
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pr_warn("Call succeeded but with an error: 0x%x\n",
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cmn_regs.u1.ral);
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} else {
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physical_bios_base = cmn_regs.u2.rebx;
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physical_bios_offset = cmn_regs.u4.redx;
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cru_length = cmn_regs.u3.recx;
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cru_physical_address =
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physical_bios_base + physical_bios_offset;
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/* If the values look OK, then map it in. */
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if ((physical_bios_base + physical_bios_offset)) {
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cru_rom_addr =
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ioremap(cru_physical_address, cru_length);
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if (cru_rom_addr) {
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set_memory_x((unsigned long)cru_rom_addr & PAGE_MASK,
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(cru_length + PAGE_SIZE - 1) >> PAGE_SHIFT);
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retval = 0;
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}
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}
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pr_debug("CRU Base Address: 0x%lx\n", physical_bios_base);
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pr_debug("CRU Offset Address: 0x%lx\n", physical_bios_offset);
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pr_debug("CRU Length: 0x%lx\n", cru_length);
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pr_debug("CRU Mapped Address: %p\n", &cru_rom_addr);
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}
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iounmap(bios32_map);
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return retval;
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}
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/*
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* bios_checksum
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*/
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static int bios_checksum(const char __iomem *ptr, int len)
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{
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char sum = 0;
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int i;
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/*
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* calculate checksum of size bytes. This should add up
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* to zero if we have a valid header.
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*/
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for (i = 0; i < len; i++)
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sum += ptr[i];
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return ((sum == 0) && (len > 0));
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}
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/*
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* bios32_present
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*
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* Routine Description:
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* This function finds the 32-bit BIOS Service Directory
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*
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* Return Value:
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* 0 : SUCCESS
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* <0 : FAILURE
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*/
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static int bios32_present(const char __iomem *p)
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{
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struct bios32_service_dir *bios_32_ptr;
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int length;
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unsigned long map_entry, map_offset;
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bios_32_ptr = (struct bios32_service_dir *) p;
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/*
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* Search for signature by checking equal to the swizzled value
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* instead of calling another routine to perform a strcmp.
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*/
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if (bios_32_ptr->signature == PCI_BIOS32_SD_VALUE) {
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length = bios_32_ptr->length * PCI_BIOS32_PARAGRAPH_LEN;
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if (bios_checksum(p, length)) {
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/*
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* According to the spec, we're looking for the
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* first 4KB-aligned address below the entrypoint
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* listed in the header. The Service Directory code
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* is guaranteed to occupy no more than 2 4KB pages.
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*/
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map_entry = bios_32_ptr->entry_point & ~(PAGE_SIZE - 1);
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map_offset = bios_32_ptr->entry_point - map_entry;
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return cru_detect(map_entry, map_offset);
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}
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}
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return -ENODEV;
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}
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static int detect_cru_service(void)
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{
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char __iomem *p, *q;
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int rc = -1;
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/*
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* Search from 0x0f0000 through 0x0fffff, inclusive.
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*/
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p = ioremap(PCI_ROM_BASE1, ROM_SIZE);
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if (p == NULL)
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return -ENOMEM;
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for (q = p; q < p + ROM_SIZE; q += 16) {
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rc = bios32_present(q);
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if (!rc)
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break;
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}
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iounmap(p);
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return rc;
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}
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/* ------------------------------------------------------------------------- */
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#endif /* CONFIG_X86_32 */
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#ifdef CONFIG_X86_64
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/* --64 Bit Bios------------------------------------------------------------ */
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#define HPWDT_ARCH 64
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asm(".text \n\t"
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".align 4 \n\t"
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".globl asminline_call \n\t"
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".type asminline_call, @function \n\t"
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"asminline_call: \n\t"
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FRAME_BEGIN
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"pushq %rax \n\t"
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"pushq %rbx \n\t"
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"pushq %rdx \n\t"
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"pushq %r12 \n\t"
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"pushq %r9 \n\t"
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"movq %rsi, %r12 \n\t"
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"movq %rdi, %r9 \n\t"
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"movl 4(%r9),%ebx \n\t"
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"movl 8(%r9),%ecx \n\t"
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"movl 12(%r9),%edx \n\t"
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"movl 16(%r9),%esi \n\t"
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"movl 20(%r9),%edi \n\t"
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"movl (%r9),%eax \n\t"
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"call *%r12 \n\t"
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"pushfq \n\t"
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"popq %r12 \n\t"
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"movl %eax, (%r9) \n\t"
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"movl %ebx, 4(%r9) \n\t"
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"movl %ecx, 8(%r9) \n\t"
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"movl %edx, 12(%r9) \n\t"
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"movl %esi, 16(%r9) \n\t"
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"movl %edi, 20(%r9) \n\t"
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"movq %r12, %rax \n\t"
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"movl %eax, 28(%r9) \n\t"
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"popq %r9 \n\t"
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"popq %r12 \n\t"
|
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"popq %rdx \n\t"
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"popq %rbx \n\t"
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"popq %rax \n\t"
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FRAME_END
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"ret \n\t"
|
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".previous");
|
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|
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/*
|
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* dmi_find_cru
|
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*
|
||||
* Routine Description:
|
||||
* This function checks whether or not a SMBIOS/DMI record is
|
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* the 64bit CRU info or not
|
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*/
|
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static void dmi_find_cru(const struct dmi_header *dm, void *dummy)
|
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{
|
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struct smbios_cru64_info *smbios_cru64_ptr;
|
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unsigned long cru_physical_address;
|
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|
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if (dm->type == SMBIOS_CRU64_INFORMATION) {
|
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smbios_cru64_ptr = (struct smbios_cru64_info *) dm;
|
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if (smbios_cru64_ptr->signature == CRU_BIOS_SIGNATURE_VALUE) {
|
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cru_physical_address =
|
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smbios_cru64_ptr->physical_address +
|
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smbios_cru64_ptr->double_offset;
|
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cru_rom_addr = ioremap(cru_physical_address,
|
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smbios_cru64_ptr->double_length);
|
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set_memory_x((unsigned long)cru_rom_addr & PAGE_MASK,
|
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smbios_cru64_ptr->double_length >> PAGE_SHIFT);
|
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}
|
||||
}
|
||||
}
|
||||
|
||||
static int detect_cru_service(void)
|
||||
{
|
||||
cru_rom_addr = NULL;
|
||||
|
||||
dmi_walk(dmi_find_cru, NULL);
|
||||
|
||||
/* if cru_rom_addr has been set then we found a CRU service */
|
||||
return ((cru_rom_addr != NULL) ? 0 : -ENODEV);
|
||||
}
|
||||
/* ------------------------------------------------------------------------- */
|
||||
#endif /* CONFIG_X86_64 */
|
||||
#endif /* CONFIG_HPWDT_NMI_DECODING */
|
||||
|
||||
/*
|
||||
* Watchdog operations
|
||||
|
@ -486,30 +113,12 @@ static int hpwdt_my_nmi(void)
|
|||
*/
|
||||
static int hpwdt_pretimeout(unsigned int ulReason, struct pt_regs *regs)
|
||||
{
|
||||
unsigned long rom_pl;
|
||||
static int die_nmi_called;
|
||||
|
||||
if (!hpwdt_nmi_decoding)
|
||||
return NMI_DONE;
|
||||
|
||||
if ((ulReason == NMI_UNKNOWN) && !hpwdt_my_nmi())
|
||||
return NMI_DONE;
|
||||
|
||||
spin_lock_irqsave(&rom_lock, rom_pl);
|
||||
if (!die_nmi_called && !is_icru && !is_uefi)
|
||||
asminline_call(&cmn_regs, cru_rom_addr);
|
||||
die_nmi_called = 1;
|
||||
spin_unlock_irqrestore(&rom_lock, rom_pl);
|
||||
|
||||
if (allow_kdump)
|
||||
hpwdt_stop();
|
||||
|
||||
if (!is_icru && !is_uefi) {
|
||||
if (cmn_regs.u1.ral == 0) {
|
||||
nmi_panic(regs, "An NMI occurred, but unable to determine source.\n");
|
||||
return NMI_HANDLED;
|
||||
}
|
||||
}
|
||||
nmi_panic(regs, "An NMI occurred. Depending on your system the reason "
|
||||
"for the NMI is logged in any one of the following "
|
||||
"resources:\n"
|
||||
|
@ -675,84 +284,11 @@ static struct miscdevice hpwdt_miscdev = {
|
|||
* Init & Exit
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_HPWDT_NMI_DECODING
|
||||
#ifdef CONFIG_X86_LOCAL_APIC
|
||||
static void hpwdt_check_nmi_decoding(struct pci_dev *dev)
|
||||
{
|
||||
/*
|
||||
* If nmi_watchdog is turned off then we can turn on
|
||||
* our nmi decoding capability.
|
||||
*/
|
||||
hpwdt_nmi_decoding = 1;
|
||||
}
|
||||
#else
|
||||
static void hpwdt_check_nmi_decoding(struct pci_dev *dev)
|
||||
{
|
||||
dev_warn(&dev->dev, "NMI decoding is disabled. "
|
||||
"Your kernel does not support a NMI Watchdog.\n");
|
||||
}
|
||||
#endif /* CONFIG_X86_LOCAL_APIC */
|
||||
|
||||
/*
|
||||
* dmi_find_icru
|
||||
*
|
||||
* Routine Description:
|
||||
* This function checks whether or not we are on an iCRU-based server.
|
||||
* This check is independent of architecture and needs to be made for
|
||||
* any ProLiant system.
|
||||
*/
|
||||
static void dmi_find_icru(const struct dmi_header *dm, void *dummy)
|
||||
{
|
||||
struct smbios_proliant_info *smbios_proliant_ptr;
|
||||
|
||||
if (dm->type == SMBIOS_ICRU_INFORMATION) {
|
||||
smbios_proliant_ptr = (struct smbios_proliant_info *) dm;
|
||||
if (smbios_proliant_ptr->misc_features & 0x01)
|
||||
is_icru = 1;
|
||||
if (smbios_proliant_ptr->misc_features & 0x1400)
|
||||
is_uefi = 1;
|
||||
}
|
||||
}
|
||||
|
||||
static int hpwdt_init_nmi_decoding(struct pci_dev *dev)
|
||||
{
|
||||
#ifdef CONFIG_HPWDT_NMI_DECODING
|
||||
int retval;
|
||||
|
||||
/*
|
||||
* On typical CRU-based systems we need to map that service in
|
||||
* the BIOS. For 32 bit Operating Systems we need to go through
|
||||
* the 32 Bit BIOS Service Directory. For 64 bit Operating
|
||||
* Systems we get that service through SMBIOS.
|
||||
*
|
||||
* On systems that support the new iCRU service all we need to
|
||||
* do is call dmi_walk to get the supported flag value and skip
|
||||
* the old cru detect code.
|
||||
*/
|
||||
dmi_walk(dmi_find_icru, NULL);
|
||||
if (!is_icru && !is_uefi) {
|
||||
|
||||
/*
|
||||
* We need to map the ROM to get the CRU service.
|
||||
* For 32 bit Operating Systems we need to go through the 32 Bit
|
||||
* BIOS Service Directory
|
||||
* For 64 bit Operating Systems we get that service through SMBIOS.
|
||||
*/
|
||||
retval = detect_cru_service();
|
||||
if (retval < 0) {
|
||||
dev_warn(&dev->dev,
|
||||
"Unable to detect the %d Bit CRU Service.\n",
|
||||
HPWDT_ARCH);
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*
|
||||
* We know this is the only CRU call we need to make so lets keep as
|
||||
* few instructions as possible once the NMI comes in.
|
||||
*/
|
||||
cmn_regs.u1.rah = 0x0D;
|
||||
cmn_regs.u1.ral = 0x02;
|
||||
}
|
||||
|
||||
/*
|
||||
* Only one function can register for NMI_UNKNOWN
|
||||
*/
|
||||
|
@ -780,44 +316,25 @@ static int hpwdt_init_nmi_decoding(struct pci_dev *dev)
|
|||
dev_warn(&dev->dev,
|
||||
"Unable to register a die notifier (err=%d).\n",
|
||||
retval);
|
||||
if (cru_rom_addr)
|
||||
iounmap(cru_rom_addr);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static void hpwdt_exit_nmi_decoding(void)
|
||||
{
|
||||
unregister_nmi_handler(NMI_UNKNOWN, "hpwdt");
|
||||
unregister_nmi_handler(NMI_SERR, "hpwdt");
|
||||
unregister_nmi_handler(NMI_IO_CHECK, "hpwdt");
|
||||
if (cru_rom_addr)
|
||||
iounmap(cru_rom_addr);
|
||||
}
|
||||
#else /* !CONFIG_HPWDT_NMI_DECODING */
|
||||
static void hpwdt_check_nmi_decoding(struct pci_dev *dev)
|
||||
{
|
||||
}
|
||||
|
||||
static int hpwdt_init_nmi_decoding(struct pci_dev *dev)
|
||||
{
|
||||
#endif /* CONFIG_HPWDT_NMI_DECODING */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void hpwdt_exit_nmi_decoding(void)
|
||||
{
|
||||
#ifdef CONFIG_HPWDT_NMI_DECODING
|
||||
unregister_nmi_handler(NMI_UNKNOWN, "hpwdt");
|
||||
unregister_nmi_handler(NMI_SERR, "hpwdt");
|
||||
unregister_nmi_handler(NMI_IO_CHECK, "hpwdt");
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_HPWDT_NMI_DECODING */
|
||||
|
||||
static int hpwdt_init_one(struct pci_dev *dev,
|
||||
const struct pci_device_id *ent)
|
||||
{
|
||||
int retval;
|
||||
|
||||
/*
|
||||
* Check if we can do NMI decoding or not
|
||||
*/
|
||||
hpwdt_check_nmi_decoding(dev);
|
||||
|
||||
/*
|
||||
* First let's find out if we are on an iLO2+ server. We will
|
||||
* not run on a legacy ASM box.
|
||||
|
@ -922,6 +439,6 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
|
|||
#ifdef CONFIG_HPWDT_NMI_DECODING
|
||||
module_param(allow_kdump, int, 0);
|
||||
MODULE_PARM_DESC(allow_kdump, "Start a kernel dump after NMI occurs");
|
||||
#endif /* !CONFIG_HPWDT_NMI_DECODING */
|
||||
#endif /* CONFIG_HPWDT_NMI_DECODING */
|
||||
|
||||
module_pci_driver(hpwdt_driver);
|
||||
|
|
|
@ -50,6 +50,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/io-64-nonatomic-lo-hi.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/moduleparam.h>
|
||||
|
@ -159,7 +160,7 @@ static unsigned int sbsa_gwdt_get_timeleft(struct watchdog_device *wdd)
|
|||
!(readl(gwdt->control_base + SBSA_GWDT_WCS) & SBSA_GWDT_WCS_WS0))
|
||||
timeleft += readl(gwdt->control_base + SBSA_GWDT_WOR);
|
||||
|
||||
timeleft += readq(gwdt->control_base + SBSA_GWDT_WCV) -
|
||||
timeleft += lo_hi_readq(gwdt->control_base + SBSA_GWDT_WCV) -
|
||||
arch_counter_get_cntvct();
|
||||
|
||||
do_div(timeleft, gwdt->clk);
|
||||
|
|
Loading…
Reference in a new issue