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perf jevents: Add support for Yitian 710 DDR PMU (arm64) aliasing
Add alias support for T-HEAD Yitian 710 SoC DDR PMU events. Reviewed-by: John Garry <john.g.garry@oracle.com> Reviewed-by: Shuai Xue <xueshuai@linux.alibaba.com> Signed-off-by: Jing Zhang <renyu.zj@linux.alibaba.com> Acked-by: Ian Rogers <irogers@google.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Will Deacon <will@kernel.org> Cc: Zhuo Song <zhuo.song@linux.alibaba.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Link: https://lore.kernel.org/r/1690528175-2499-2-git-send-email-renyu.zj@linux.alibaba.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Jing Zhang
Arnaldo Carvalho de Melo
parent
404e077a16
commit
24069d8112
2 changed files with 374 additions and 0 deletions
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@ -0,0 +1,373 @@
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[
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{
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"BriefDescription": "A Write or Read Op at HIF interface. The unit is 64B.",
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"ConfigCode": "0x0",
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"EventName": "hif_rd_or_wr",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Write Op at HIF interface. The unit is 64B.",
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"ConfigCode": "0x1",
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"EventName": "hif_wr",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Read Op at HIF interface. The unit is 64B.",
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"ConfigCode": "0x2",
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"EventName": "hif_rd",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Read-Modify-Write Op at HIF interface. The unit is 64B.",
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"ConfigCode": "0x3",
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"EventName": "hif_rmw",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A high priority Read at HIF interface. The unit is 64B.",
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"ConfigCode": "0x4",
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"EventName": "hif_hi_pri_rd",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A write data cycle at DFI interface (to DRAM).",
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"ConfigCode": "0x7",
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"EventName": "dfi_wr_data_cycles",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A read data cycle at DFI interface (to DRAM).",
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"ConfigCode": "0x8",
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"EventName": "dfi_rd_data_cycles",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A high priority read becomes critical.",
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"ConfigCode": "0x9",
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"EventName": "hpr_xact_when_critical",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A low priority read becomes critical.",
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"ConfigCode": "0xA",
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"EventName": "lpr_xact_when_critical",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A write becomes critical.",
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"ConfigCode": "0xB",
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"EventName": "wr_xact_when_critical",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "An Activate(ACT) command to DRAM.",
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"ConfigCode": "0xC",
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"EventName": "op_is_activate",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Read or Write CAS command to DRAM.",
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"ConfigCode": "0xD",
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"EventName": "op_is_rd_or_wr",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "An Activate(ACT) command for read to DRAM.",
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"ConfigCode": "0xE",
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"EventName": "op_is_rd_activate",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Read CAS command to DRAM.",
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"ConfigCode": "0xF",
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"EventName": "op_is_rd",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Write CAS command to DRAM.",
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"ConfigCode": "0x10",
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"EventName": "op_is_wr",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Masked Write command to DRAM.",
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"ConfigCode": "0x11",
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"EventName": "op_is_mwr",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Precharge(PRE) command to DRAM.",
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"ConfigCode": "0x12",
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"EventName": "op_is_precharge",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Precharge(PRE) required by read or write.",
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"ConfigCode": "0x13",
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"EventName": "precharge_for_rdwr",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Precharge(PRE) required by other conditions.",
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"ConfigCode": "0x14",
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"EventName": "precharge_for_other",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A read-write turnaround.",
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"ConfigCode": "0x15",
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"EventName": "rdwr_transitions",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A write combine(merge) in write data buffer.",
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"ConfigCode": "0x16",
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"EventName": "write_combine",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Write-After-Read hazard.",
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"ConfigCode": "0x17",
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"EventName": "war_hazard",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Read-After-Write hazard.",
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"ConfigCode": "0x18",
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"EventName": "raw_hazard",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Write-After-Write hazard.",
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"ConfigCode": "0x19",
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"EventName": "waw_hazard",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "Rank0 enters self-refresh(SRE).",
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"ConfigCode": "0x1A",
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"EventName": "op_is_enter_selfref_rk0",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "Rank1 enters self-refresh(SRE).",
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"ConfigCode": "0x1B",
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"EventName": "op_is_enter_selfref_rk1",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "Rank2 enters self-refresh(SRE).",
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"ConfigCode": "0x1C",
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"EventName": "op_is_enter_selfref_rk2",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "Rank3 enters self-refresh(SRE).",
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"ConfigCode": "0x1D",
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"EventName": "op_is_enter_selfref_rk3",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "Rank0 enters power-down(PDE).",
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"ConfigCode": "0x1E",
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"EventName": "op_is_enter_powerdown_rk0",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "Rank1 enters power-down(PDE).",
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"ConfigCode": "0x1F",
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"EventName": "op_is_enter_powerdown_rk1",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "Rank2 enters power-down(PDE).",
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"ConfigCode": "0x20",
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"EventName": "op_is_enter_powerdown_rk2",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "Rank3 enters power-down(PDE).",
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"ConfigCode": "0x21",
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"EventName": "op_is_enter_powerdown_rk3",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A cycle that Rank0 stays in self-refresh mode.",
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"ConfigCode": "0x26",
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"EventName": "selfref_mode_rk0",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A cycle that Rank1 stays in self-refresh mode.",
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"ConfigCode": "0x27",
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"EventName": "selfref_mode_rk1",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A cycle that Rank2 stays in self-refresh mode.",
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"ConfigCode": "0x28",
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"EventName": "selfref_mode_rk2",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A cycle that Rank3 stays in self-refresh mode.",
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"ConfigCode": "0x29",
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"EventName": "selfref_mode_rk3",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "An auto-refresh(REF) command to DRAM.",
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"ConfigCode": "0x2A",
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"EventName": "op_is_refresh",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A critical auto-refresh(REF) command to DRAM.",
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"ConfigCode": "0x2B",
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"EventName": "op_is_crit_ref",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "An MRR or MRW command to DRAM.",
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"ConfigCode": "0x2D",
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"EventName": "op_is_load_mode",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A ZQCal command to DRAM.",
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"ConfigCode": "0x2E",
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"EventName": "op_is_zqcl",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "At least one entry in read queue reaches the visible window limit.",
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"ConfigCode": "0x30",
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"EventName": "visible_window_limit_reached_rd",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "At least one entry in write queue reaches the visible window limit.",
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"ConfigCode": "0x31",
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"EventName": "visible_window_limit_reached_wr",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A DQS Oscillator MPC command to DRAM.",
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"ConfigCode": "0x34",
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"EventName": "op_is_dqsosc_mpc",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A DQS Oscillator MRR command to DRAM.",
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"ConfigCode": "0x35",
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"EventName": "op_is_dqsosc_mrr",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A Temperature Compensated Refresh(TCR) MRR command to DRAM.",
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"ConfigCode": "0x36",
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"EventName": "op_is_tcr_mrr",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A ZQCal Start command to DRAM.",
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"ConfigCode": "0x37",
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"EventName": "op_is_zqstart",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A ZQCal Latch command to DRAM.",
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"ConfigCode": "0x38",
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"EventName": "op_is_zqlatch",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A packet at CHI TXREQ interface (request).",
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"ConfigCode": "0x39",
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"EventName": "chi_txreq",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A packet at CHI TXDAT interface (read data).",
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"ConfigCode": "0x3A",
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"EventName": "chi_txdat",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A packet at CHI RXDAT interface (write data).",
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"ConfigCode": "0x3B",
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"EventName": "chi_rxdat",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A packet at CHI RXRSP interface.",
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"ConfigCode": "0x3C",
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"EventName": "chi_rxrsp",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "A violation detected in TZC.",
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"ConfigCode": "0x3D",
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"EventName": "tsz_vio",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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},
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{
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"BriefDescription": "The ddr cycles.",
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"ConfigCode": "0x80",
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"EventName": "ddr_cycles",
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"Unit": "ali_drw",
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"Compat": "ali_drw_pmu"
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}
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]
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@ -274,6 +274,7 @@ class JsonEvent:
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'DFPMC': 'amd_df',
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'cpu_core': 'cpu_core',
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'cpu_atom': 'cpu_atom',
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'ali_drw': 'ali_drw',
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}
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return table[unit] if unit in table else f'uncore_{unit.lower()}'
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