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RISC-V DTS changes for v5.16

Browse source 
Cleanups of RISC-V SiFive and Microchip DTSes with dtschema.  These are
 few minor fixes to make DTSes pass the dtschema, without actual
 functional effect.
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Merge tag 'riscv-sifive-dt-5.16' of git://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into for-next

RISC-V DTS changes for v5.16

Cleanups of RISC-V SiFive and Microchip DTSes with dtschema.  These are
few minor fixes to make DTSes pass the dtschema, without actual
functional effect.

* tag 'riscv-sifive-dt-5.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  riscv: dts: sifive: add missing compatible for plic
  riscv: dts: microchip: add missing compatibles for clint and plic
  riscv: dts: sifive: drop duplicated nodes and properties in sifive
  riscv: dts: sifive: fix Unleashed board compatible
  riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible
This commit is contained in:
Palmer Dabbelt 2021-10-21 08:22:37 -07:00
commit 241527bb84
4 changed files with 7 additions and 16 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
View file

@ -161,7 +161,7 @@ cache-controller@2010000 {
};
clint@2000000 {
compatible = "sifive,clint0";
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7
@ -172,7 +172,7 @@ &cpu3_intc 3 &cpu3_intc 7
plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0";
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <186>;
interrupt-controller;

2
arch/riscv/boot/dts/sifive/fu540-c000.dtsi
View file

@ -141,7 +141,7 @@ soc {
ranges;
plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0";
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <53>;
interrupt-controller;

10
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
View file

@ -8,10 +8,9 @@
#define RTCCLK_FREQ 1000000
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "SiFive HiFive Unleashed A00";
compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
"sifive,fu540";
chosen {
stdout-path = "serial0";
@ -26,9 +25,6 @@ memory@80000000 {
reg = <0x0 0x80000000 0x2 0x00000000>;
};
soc {
};
hfclk: hfclk {
#clock-cells = <0>;
compatible = "fixed-clock";
@ -63,7 +59,7 @@ &i2c0 {
&qspi0 {
status = "okay";
flash@0 {
compatible = "issi,is25wp256", "jedec,spi-nor";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
m25p,fast-read;

7
arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
View file

@ -8,8 +8,6 @@
#define RTCCLK_FREQ 1000000
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "SiFive HiFive Unmatched A00";
compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
"sifive,fu740";
@ -27,9 +25,6 @@ memory@80000000 {
reg = <0x0 0x80000000 0x4 0x00000000>;
};
soc {
};
hfclk: hfclk {
#clock-cells = <0>;
compatible = "fixed-clock";
@ -211,7 +206,7 @@ vdd_ldo11: ldo11 {
&qspi0 {
status = "okay";
flash@0 {
compatible = "issi,is25wp256", "jedec,spi-nor";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
m25p,fast-read;