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net/mlx5: Unify device IPsec capabilities check
Merge two different function to one in order to provide coherent picture if the device is IPsec capable or not. Link: https://lore.kernel.org/r/8f10ea06ad19c6f651e9fb33921009658f01e1d5.1649232994.git.leonro@nvidia.com Reviewed-by: Raed Salem <raeds@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
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5a985aa3c9
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2451da081a
6 changed files with 32 additions and 57 deletions
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@ -6,9 +6,6 @@
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#include "lib/mlx5.h"
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#include "en_accel/ipsec_fs.h"
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#define MLX5_IPSEC_DEV_BASIC_CAPS (MLX5_ACCEL_IPSEC_CAP_DEVICE | MLX5_ACCEL_IPSEC_CAP_IPV6 | \
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MLX5_ACCEL_IPSEC_CAP_LSO)
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struct mlx5_ipsec_sa_ctx {
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struct rhash_head hash;
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u32 enc_key_id;
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@ -25,17 +22,31 @@ struct mlx5_ipsec_esp_xfrm {
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struct mlx5_accel_esp_xfrm accel_xfrm;
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};
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static u32 mlx5_ipsec_offload_device_caps(struct mlx5_core_dev *mdev)
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u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev)
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{
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u32 caps = MLX5_IPSEC_DEV_BASIC_CAPS;
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u32 caps;
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if (!mlx5_is_ipsec_device(mdev))
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if (!MLX5_CAP_GEN(mdev, ipsec_offload))
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return 0;
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if (!MLX5_CAP_GEN(mdev, log_max_dek))
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return 0;
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if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
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MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC))
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return 0;
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if (!MLX5_CAP_IPSEC(mdev, ipsec_crypto_offload) ||
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!MLX5_CAP_ETH(mdev, insert_trailer))
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return 0;
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if (!MLX5_CAP_FLOWTABLE_NIC_TX(mdev, ipsec_encrypt) ||
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!MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ipsec_decrypt))
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return 0;
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caps = MLX5_ACCEL_IPSEC_CAP_DEVICE | MLX5_ACCEL_IPSEC_CAP_IPV6 |
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MLX5_ACCEL_IPSEC_CAP_LSO;
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if (MLX5_CAP_IPSEC(mdev, ipsec_crypto_esp_aes_gcm_128_encrypt) &&
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MLX5_CAP_IPSEC(mdev, ipsec_crypto_esp_aes_gcm_128_decrypt))
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caps |= MLX5_ACCEL_IPSEC_CAP_ESP;
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@ -52,6 +63,7 @@ static u32 mlx5_ipsec_offload_device_caps(struct mlx5_core_dev *mdev)
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WARN_ON_ONCE(MLX5_CAP_IPSEC(mdev, log_max_ipsec_offload) > 24);
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return caps;
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}
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EXPORT_SYMBOL_GPL(mlx5_ipsec_device_caps);
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static int
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mlx5_ipsec_offload_esp_validate_xfrm_attrs(struct mlx5_core_dev *mdev,
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@ -367,7 +379,6 @@ static int mlx5_ipsec_offload_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
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}
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static const struct mlx5_accel_ipsec_ops ipsec_offload_ops = {
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.device_caps = mlx5_ipsec_offload_device_caps,
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.create_hw_context = mlx5_ipsec_offload_create_sa_ctx,
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.free_hw_context = mlx5_ipsec_offload_delete_sa_ctx,
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.init = mlx5_ipsec_offload_init,
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@ -379,7 +390,7 @@ static const struct mlx5_accel_ipsec_ops ipsec_offload_ops = {
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static const struct mlx5_accel_ipsec_ops *
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mlx5_ipsec_offload_ops(struct mlx5_core_dev *mdev)
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{
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if (!mlx5_ipsec_offload_device_caps(mdev))
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if (!mlx5_ipsec_device_caps(mdev))
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return NULL;
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return &ipsec_offload_ops;
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@ -416,17 +427,6 @@ void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev)
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ipsec_ops->cleanup(mdev);
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}
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u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev)
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{
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const struct mlx5_accel_ipsec_ops *ipsec_ops = mdev->ipsec_ops;
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if (!ipsec_ops || !ipsec_ops->device_caps)
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return 0;
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return ipsec_ops->device_caps(mdev);
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}
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EXPORT_SYMBOL_GPL(mlx5_accel_ipsec_device_caps);
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unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev)
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{
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const struct mlx5_accel_ipsec_ops *ipsec_ops = mdev->ipsec_ops;
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@ -9,9 +9,6 @@
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#ifdef CONFIG_MLX5_IPSEC
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#define MLX5_IPSEC_DEV(mdev) (mlx5_accel_ipsec_device_caps(mdev) & \
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MLX5_ACCEL_IPSEC_CAP_DEVICE)
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unsigned int mlx5_accel_ipsec_counters_count(struct mlx5_core_dev *mdev);
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int mlx5_accel_ipsec_counters_read(struct mlx5_core_dev *mdev, u64 *counters,
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unsigned int count);
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@ -25,7 +22,6 @@ void mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev);
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void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev);
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struct mlx5_accel_ipsec_ops {
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u32 (*device_caps)(struct mlx5_core_dev *mdev);
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unsigned int (*counters_count)(struct mlx5_core_dev *mdev);
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int (*counters_read)(struct mlx5_core_dev *mdev, u64 *counters,
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unsigned int count);
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@ -45,25 +41,8 @@ struct mlx5_accel_ipsec_ops {
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void (*esp_destroy_xfrm)(struct mlx5_accel_esp_xfrm *xfrm);
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};
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static inline bool mlx5_is_ipsec_device(struct mlx5_core_dev *mdev)
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{
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if (!MLX5_CAP_GEN(mdev, ipsec_offload))
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return false;
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if (!MLX5_CAP_GEN(mdev, log_max_dek))
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return false;
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if (!(MLX5_CAP_GEN_64(mdev, general_obj_types) &
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MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC))
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return false;
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return MLX5_CAP_IPSEC(mdev, ipsec_crypto_offload) &&
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MLX5_CAP_ETH(mdev, insert_trailer);
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}
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#else
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#define MLX5_IPSEC_DEV(mdev) false
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static inline void *
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mlx5_accel_esp_create_hw_context(struct mlx5_core_dev *mdev,
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struct mlx5_accel_esp_xfrm *xfrm,
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@ -80,10 +59,5 @@ static inline void mlx5_accel_esp_free_hw_context(struct mlx5_core_dev *mdev,
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static inline void mlx5_accel_ipsec_init(struct mlx5_core_dev *mdev) {}
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static inline void mlx5_accel_ipsec_cleanup(struct mlx5_core_dev *mdev) {}
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static inline bool mlx5_is_ipsec_device(struct mlx5_core_dev *mdev)
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{
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return false;
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}
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#endif /* CONFIG_MLX5_IPSEC */
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#endif /* __MLX5_IPSEC_OFFLOAD_H__ */
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@ -689,8 +689,8 @@ void mlx5e_build_sq_param(struct mlx5_core_dev *mdev,
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void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
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bool allow_swp;
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allow_swp = mlx5_geneve_tx_allowed(mdev) ||
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!!MLX5_IPSEC_DEV(mdev);
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allow_swp =
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mlx5_geneve_tx_allowed(mdev) || !!mlx5_ipsec_device_caps(mdev);
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mlx5e_build_sq_param_common(mdev, param);
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MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
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MLX5_SET(sqc, sqc, allow_swp, allow_swp);
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@ -226,8 +226,7 @@ static inline int mlx5e_xfrm_validate_state(struct xfrm_state *x)
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return -EINVAL;
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}
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if (x->props.flags & XFRM_STATE_ESN &&
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!(mlx5_accel_ipsec_device_caps(priv->mdev) &
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MLX5_ACCEL_IPSEC_CAP_ESN)) {
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!(mlx5_ipsec_device_caps(priv->mdev) & MLX5_ACCEL_IPSEC_CAP_ESN)) {
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netdev_info(netdev, "Cannot offload ESN xfrm states\n");
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return -EINVAL;
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}
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@ -275,8 +274,7 @@ static inline int mlx5e_xfrm_validate_state(struct xfrm_state *x)
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return -EINVAL;
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}
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if (x->props.family == AF_INET6 &&
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!(mlx5_accel_ipsec_device_caps(priv->mdev) &
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MLX5_ACCEL_IPSEC_CAP_IPV6)) {
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!(mlx5_ipsec_device_caps(priv->mdev) & MLX5_ACCEL_IPSEC_CAP_IPV6)) {
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netdev_info(netdev, "IPv6 xfrm state offload is not supported by this device\n");
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return -EINVAL;
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}
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@ -406,7 +404,7 @@ int mlx5e_ipsec_init(struct mlx5e_priv *priv)
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{
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struct mlx5e_ipsec *ipsec = NULL;
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if (!MLX5_IPSEC_DEV(priv->mdev)) {
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if (!mlx5_ipsec_device_caps(priv->mdev)) {
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netdev_dbg(priv->netdev, "Not an IPSec offload device\n");
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return 0;
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}
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@ -519,7 +517,7 @@ void mlx5e_ipsec_build_netdev(struct mlx5e_priv *priv)
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struct mlx5_core_dev *mdev = priv->mdev;
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struct net_device *netdev = priv->netdev;
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if (!(mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_ESP) ||
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if (!(mlx5_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_ESP) ||
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!MLX5_CAP_ETH(mdev, swp)) {
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mlx5_core_dbg(mdev, "mlx5e: ESP and SWP offload not supported\n");
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return;
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netdev->features |= NETIF_F_HW_ESP_TX_CSUM;
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netdev->hw_enc_features |= NETIF_F_HW_ESP_TX_CSUM;
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if (!(mlx5_accel_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_LSO) ||
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if (!(mlx5_ipsec_device_caps(mdev) & MLX5_ACCEL_IPSEC_CAP_LSO) ||
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!MLX5_CAP_ETH(mdev, swp_lso)) {
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mlx5_core_dbg(mdev, "mlx5e: ESP LSO not supported\n");
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return;
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@ -1329,7 +1329,7 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
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INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
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if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert))
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set_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state);
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if (MLX5_IPSEC_DEV(c->priv->mdev))
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if (mlx5_ipsec_device_caps(c->priv->mdev))
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set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
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if (param->is_mpw)
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set_bit(MLX5E_SQ_STATE_MPWQE, &sq->state);
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@ -124,7 +124,7 @@ enum mlx5_accel_ipsec_cap {
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#ifdef CONFIG_MLX5_ACCEL
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u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev);
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u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev);
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struct mlx5_accel_esp_xfrm *
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mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
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#else
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static inline u32 mlx5_accel_ipsec_device_caps(struct mlx5_core_dev *mdev) { return 0; }
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static inline u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev)
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{
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return 0;
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}
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static inline struct mlx5_accel_esp_xfrm *
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mlx5_accel_esp_create_xfrm(struct mlx5_core_dev *mdev,
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