mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
clk: renesas: r8a77980: Correct parent clock of PCIEC0
According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of
December 22, 2017, the parent clock of the PCIe module clock on R-Car
V3H is S2D2.
Fixes: ce15783c51
("clk: renesas: cpg-mssr: add R8A77980 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
parent
279ebbcae5
commit
246e232437
1 changed files with 1 additions and 1 deletions
|
@ -116,7 +116,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
|
|||
DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
|
||||
DEF_MOD("tpu0", 304, R8A77980_CLK_S3D4),
|
||||
DEF_MOD("sdif", 314, R8A77980_CLK_SD0),
|
||||
DEF_MOD("pciec0", 319, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("pciec0", 319, R8A77980_CLK_S2D2),
|
||||
DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
|
||||
DEF_MOD("hscif3", 517, R8A77980_CLK_S3D1),
|
||||
|
|
Loading…
Reference in a new issue