From 677b64577f818eb7edac82a61df5eacfd38c4179 Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Tue, 21 Feb 2023 10:42:53 -0800 Subject: [PATCH 01/42] drm/msm/dpu: Move TE setup to prepare_for_kickoff() Currently, DPU will enable TE during prepare_commit(). However, this will cause a crash and reboot to sahara when trying to read/write to register in get_autorefresh_config(), because the core clock rates aren't set at that time. This used to work because phys_enc->hw_pp is only initialized in mode set [1], so the first prepare_commit() will return before any register read/write as hw_pp would be NULL. However, when we try to implement support for INTF TE, we will run into the clock issue described above as hw_intf will *not* be NULL on the first prepare_commit(). This is because the initialization of dpu_enc->hw_intf has been moved to dpu_encoder_setup() [2]. To avoid this issue, let's enable TE during prepare_for_kickoff() instead as the core clock rates are guaranteed to be set then. Depends on: "Implement tearcheck support on INTF block" [3] Changes in V3: - Added function prototypes - Reordered function definitions to make change more legible - Removed prepare_commit() function from dpu_encoder_phys_cmd Changes in V4: - Reworded commit message to be more specific - Removed dpu_encoder_phys_cmd_is_ongoing_pptx() prototype [1] https://gitlab.freedesktop.org/drm/msm/-/blob/msm-next/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c#L1109 [2] https://gitlab.freedesktop.org/drm/msm/-/blob/msm-next/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c#L2339 [3] https://patchwork.freedesktop.org/series/112332/ Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/523602/ Link: https://lore.kernel.org/r/20230221184256.1436-2-quic_jesszhan@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index c8f4a62a9536..74470d068622 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -40,6 +40,8 @@ #define DPU_ENC_MAX_POLL_TIMEOUT_US 2000 +static void dpu_encoder_phys_cmd_enable_te(struct dpu_encoder_phys *phys_enc); + static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc) { return (phys_enc->split_role != ENC_ROLE_SLAVE); @@ -565,6 +567,8 @@ static void dpu_encoder_phys_cmd_prepare_for_kickoff( phys_enc->hw_pp->idx - PINGPONG_0); } + dpu_encoder_phys_cmd_enable_te(phys_enc); + DPU_DEBUG_CMDENC(cmd_enc, "pp:%d pending_cnt %d\n", phys_enc->hw_pp->idx - PINGPONG_0, atomic_read(&phys_enc->pending_kickoff_cnt)); @@ -586,8 +590,7 @@ static bool dpu_encoder_phys_cmd_is_ongoing_pptx( return false; } -static void dpu_encoder_phys_cmd_prepare_commit( - struct dpu_encoder_phys *phys_enc) +static void dpu_encoder_phys_cmd_enable_te(struct dpu_encoder_phys *phys_enc) { struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); @@ -732,7 +735,6 @@ static void dpu_encoder_phys_cmd_trigger_start( static void dpu_encoder_phys_cmd_init_ops( struct dpu_encoder_phys_ops *ops) { - ops->prepare_commit = dpu_encoder_phys_cmd_prepare_commit; ops->is_master = dpu_encoder_phys_cmd_is_master; ops->atomic_mode_set = dpu_encoder_phys_cmd_atomic_mode_set; ops->enable = dpu_encoder_phys_cmd_enable; From 51aeb3997feb81d316cb98fdcabafc41c8abf9f0 Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Tue, 21 Feb 2023 10:42:55 -0800 Subject: [PATCH 02/42] drm/msm/dpu: Remove empty prepare_commit() function Now that the TE setup has been moved to prepare_for_kickoff(), we have not prepare_commit() callbacks left. This makes dpu_encoder_prepare_commit() do nothing. Remove prepare_commit() from DPU driver. Changes in V3: - Reworded commit message to be more clear - Corrected spelling mistake in commit message Changes in V4: - Reworded commit message for clarity Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/523606/ Link: https://lore.kernel.org/r/20230221184256.1436-4-quic_jesszhan@quicinc.com [DB: fixed merge conflict] Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 19 ------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 7 ------- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 21 --------------------- 3 files changed, 47 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 450abb14ac2f..e4744565bb47 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2094,25 +2094,6 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) ctl->ops.clear_pending_flush(ctl); } -void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc) -{ - struct dpu_encoder_virt *dpu_enc; - struct dpu_encoder_phys *phys; - int i; - - if (!drm_enc) { - DPU_ERROR("invalid encoder\n"); - return; - } - dpu_enc = to_dpu_encoder_virt(drm_enc); - - for (i = 0; i < dpu_enc->num_phys_encs; i++) { - phys = dpu_enc->phys_encs[i]; - if (phys->ops.prepare_commit) - phys->ops.prepare_commit(phys); - } -} - #ifdef CONFIG_DEBUG_FS static int _dpu_encoder_status_show(struct seq_file *s, void *data) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 9e7236ef34e6..2c9ef8d1b877 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -146,13 +146,6 @@ struct drm_encoder *dpu_encoder_init( int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, struct msm_display_info *disp_info); -/** - * dpu_encoder_prepare_commit - prepare encoder at the very beginning of an - * atomic commit, before any registers are written - * @drm_enc: Pointer to previously created drm encoder structure - */ -void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc); - /** * dpu_encoder_set_idle_timeout - set the idle timeout for video * and command mode encoders. diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 6cd7be500dfe..75faaf4f7547 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -411,26 +411,6 @@ static void dpu_kms_disable_commit(struct msm_kms *kms) pm_runtime_put_sync(&dpu_kms->pdev->dev); } -static void dpu_kms_prepare_commit(struct msm_kms *kms, - struct drm_atomic_state *state) -{ - struct drm_crtc *crtc; - struct drm_crtc_state *crtc_state; - struct drm_encoder *encoder; - int i; - - if (!kms) - return; - - /* Call prepare_commit for all affected encoders */ - for_each_new_crtc_in_state(state, crtc, crtc_state, i) { - drm_for_each_encoder_mask(encoder, crtc->dev, - crtc_state->encoder_mask) { - dpu_encoder_prepare_commit(encoder); - } - } -} - static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask) { struct dpu_kms *dpu_kms = to_dpu_kms(kms); @@ -939,7 +919,6 @@ static const struct msm_kms_funcs kms_funcs = { .irq = dpu_core_irq, .enable_commit = dpu_kms_enable_commit, .disable_commit = dpu_kms_disable_commit, - .prepare_commit = dpu_kms_prepare_commit, .flush_commit = dpu_kms_flush_commit, .wait_flush = dpu_kms_wait_flush, .complete_commit = dpu_kms_complete_commit, From b6dde3a06f2e00d2c4c902a581ef72c101f50bcc Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 9 Jan 2023 11:15:18 +0100 Subject: [PATCH 03/42] dt-bindings: display/msm: document DPU on SM8550 Document the DPU hardware found on the Qualcomm SM8550 platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Patchwork: https://patchwork.freedesktop.org/patch/517511/ Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-mdss-dsi-v3-2-660c3bcb127f@linaro.org [DB: removed interconnect header inclusion] Signed-off-by: Dmitry Baryshkov --- .../bindings/display/msm/qcom,sm8550-dpu.yaml | 133 ++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml new file mode 100644 index 000000000000..ff58a747bb6f --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8550-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Display DPU + +maintainers: + - Neil Armstrong + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sm8550-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display AHB + - description: Display hf axi + - description: Display MDSS ahb + - description: Display lut + - description: Display core + - description: Display vsync + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + display-controller@ae01000 { + compatible = "qcom,sm8550-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8550_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; +... From 83a58b20c9b340000d508181f9d4ecec1437a771 Mon Sep 17 00:00:00 2001 From: Kalyan Thota Date: Fri, 27 Jan 2023 02:14:47 -0800 Subject: [PATCH 04/42] drm/msm/disp/dpu1: add support for dspp sub block flush in sc7280 Flush mechanism for DSPP blocks has changed in sc7280 family, it allows individual sub blocks to be flushed in coordination with master flush control. Representation: master_flush && (PCC_flush | IGC_flush .. etc ) This change adds necessary support for the above design. Changes in v1: - Few nits (Doug, Dmitry) - Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry) Changes in v2: - Move the address offset to flush macro (Dmitry) - Separate ops for the sub block flush (Dmitry) Changes in v3: - Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry) Changes in v4: - Use shorter version for unsigned int (Stephen) Changes in v5: - Spurious patch please ignore. Changes in v6: - Add SOB tag (Doug, Dmitry) Changes in v7: - Cache flush mask per dspp (Dmitry) - Few nits (Marijn) Changes in v8: - Few nits (Marijn) Changes in v9: - Use DSPP enum while accessing flush mask to make it readable (Dmitry) - Few nits (Dmitry) Changes in v10: - Fix white spaces in a separate patch (Dmitry) Changes in v11: - Define a macro for dspp flush selection (Marijn) - Few nits (Marijn) Changes in v12: - Minor comments (reorder macros and a condition) (Marijn) Signed-off-by: Kalyan Thota Tested-by: Douglas Anderson Patchwork: https://patchwork.freedesktop.org/patch/520701/ Link: https://lore.kernel.org/r/1674814487-2112-1-git-send-email-quic_kalyant@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 49 +++++++++++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 5 +- 5 files changed, 58 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index b1ec0c35947b..1bdf78cae12a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -768,7 +768,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc) /* stage config flush mask */ ctl->ops.update_pending_flush_dspp(ctl, - mixer[i].hw_dspp->idx); + mixer[i].hw_dspp->idx, DPU_DSPP_PCC); } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index b39e72a72d58..7b8a5a5cfec7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -66,7 +66,10 @@ (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) #define CTL_SC7280_MASK \ - (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG)) + (BIT(DPU_CTL_ACTIVE_CFG) | \ + BIT(DPU_CTL_FETCH_ACTIVE) | \ + BIT(DPU_CTL_VM_CFG) | \ + BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) #define CTL_SM8550_MASK \ (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index ae85b40e282b..63d7c6b15110 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -169,10 +169,12 @@ enum { * DSPP sub-blocks * @DPU_DSPP_PCC Panel color correction block * @DPU_DSPP_GC Gamma correction block + * @DPU_DSPP_IGC Inverse gamma correction block */ enum { DPU_DSPP_PCC = 0x1, DPU_DSPP_GC, + DPU_DSPP_IGC, DPU_DSPP_MAX }; @@ -200,6 +202,7 @@ enum { * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) * @DPU_CTL_VM_CFG: CTL config to support multiple VMs * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register + * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush * @DPU_CTL_MAX */ enum { @@ -208,6 +211,7 @@ enum { DPU_CTL_FETCH_ACTIVE, DPU_CTL_VM_CFG, DPU_CTL_HAS_LAYER_EXT4, + DPU_CTL_DSPP_SUB_BLOCK_FLUSH, DPU_CTL_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index 6c53ea560ffa..bbdc95ce374a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -26,15 +26,16 @@ #define CTL_SW_RESET 0x030 #define CTL_LAYER_EXTN_OFFSET 0x40 #define CTL_MERGE_3D_ACTIVE 0x0E4 +#define CTL_DSC_ACTIVE 0x0E8 #define CTL_WB_ACTIVE 0x0EC #define CTL_INTF_ACTIVE 0x0F4 +#define CTL_FETCH_PIPE_ACTIVE 0x0FC #define CTL_MERGE_3D_FLUSH 0x100 -#define CTL_DSC_ACTIVE 0x0E8 #define CTL_DSC_FLUSH 0x104 #define CTL_WB_FLUSH 0x108 #define CTL_INTF_FLUSH 0x110 #define CTL_INTF_MASTER 0x134 -#define CTL_FETCH_PIPE_ACTIVE 0x0FC +#define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4)) #define CTL_MIXER_BORDER_OUT BIT(24) #define CTL_FLUSH_MASK_CTL BIT(17) @@ -44,6 +45,7 @@ #define DSC_IDX 22 #define INTF_IDX 31 #define WB_IDX 16 +#define DSPP_IDX 29 /* From DPU hw rev 7.x.x */ #define CTL_INVALID_BIT 0xffff #define CTL_DEFAULT_GROUP_ID 0xf @@ -115,6 +117,9 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx) trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask, dpu_hw_ctl_get_flush_register(ctx)); ctx->pending_flush_mask = 0x0; + + memset(ctx->pending_dspp_flush_mask, 0, + sizeof(ctx->pending_dspp_flush_mask)); } static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx, @@ -132,6 +137,8 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx) static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) { + int dspp; + if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX)) DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH, ctx->pending_merge_3d_flush_mask); @@ -142,6 +149,13 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) DPU_REG_WRITE(&ctx->hw, CTL_WB_FLUSH, ctx->pending_wb_flush_mask); + if (ctx->pending_flush_mask & BIT(DSPP_IDX)) + for (dspp = DSPP_0; dspp < DSPP_MAX; dspp++) { + if (ctx->pending_dspp_flush_mask[dspp - DSPP_0]) + DPU_REG_WRITE(&ctx->hw, + CTL_DSPP_n_FLUSH(dspp - DSPP_0), + ctx->pending_dspp_flush_mask[dspp - DSPP_0]); + } DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask); } @@ -289,7 +303,7 @@ static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx, } static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx, - enum dpu_dspp dspp) + enum dpu_dspp dspp, u32 dspp_sub_blk) { switch (dspp) { case DSPP_0: @@ -309,6 +323,29 @@ static void dpu_hw_ctl_update_pending_flush_dspp(struct dpu_hw_ctl *ctx, } } +static void dpu_hw_ctl_update_pending_flush_dspp_sub_blocks( + struct dpu_hw_ctl *ctx, enum dpu_dspp dspp, u32 dspp_sub_blk) +{ + if (dspp >= DSPP_MAX) + return; + + switch (dspp_sub_blk) { + case DPU_DSPP_IGC: + ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(2); + break; + case DPU_DSPP_PCC: + ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(4); + break; + case DPU_DSPP_GC: + ctx->pending_dspp_flush_mask[dspp - DSPP_0] |= BIT(5); + break; + default: + return; + } + + ctx->pending_flush_mask |= BIT(DSPP_IDX); +} + static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeout_us) { struct dpu_hw_blk_reg_map *c = &ctx->hw; @@ -630,7 +667,11 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->setup_blendstage = dpu_hw_ctl_setup_blendstage; ops->update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp; ops->update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer; - ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp; + if (cap & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) + ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp_sub_blocks; + else + ops->update_pending_flush_dspp = dpu_hw_ctl_update_pending_flush_dspp; + if (cap & BIT(DPU_CTL_FETCH_ACTIVE)) ops->set_active_pipes = dpu_hw_ctl_set_fetch_pipe_active; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index 96c012ec8467..78611a831697 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -152,9 +152,11 @@ struct dpu_hw_ctl_ops { * No effect on hardware * @ctx : ctl path ctx pointer * @blk : DSPP block index + * @dspp_sub_blk : DSPP sub-block index */ void (*update_pending_flush_dspp)(struct dpu_hw_ctl *ctx, - enum dpu_dspp blk); + enum dpu_dspp blk, u32 dspp_sub_blk); + /** * Write the value of the pending_flush_mask to hardware * @ctx : ctl path ctx pointer @@ -242,6 +244,7 @@ struct dpu_hw_ctl { u32 pending_intf_flush_mask; u32 pending_wb_flush_mask; u32 pending_merge_3d_flush_mask; + u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0]; /* ops */ struct dpu_hw_ctl_ops ops; From ffbbed63e6450225972deb75094b3ebe65d9b56b Mon Sep 17 00:00:00 2001 From: Leonard Lausen Date: Tue, 21 Mar 2023 02:58:04 +0000 Subject: [PATCH 05/42] drm/msm/dpu: Add support for AR30 format Commit da7716a249b699978fb5 ("drm/msm/dpu: Add support for XR30 format") enabled support for the 10-bit XR30 color format but missed enabling support for the corresponding per-pixel alpha-blending AR30 color format. Declaring only XR30 but not AR30 color format support can trigger bugs in userspace. KDE KWin compositor versions prior to 5.27.3 for example prefer 10-bit color formats, rendering a 1cm^2 black box around the cursor due to missing per-pixel alpha-blending. Signed-off-by: Leonard Lausen Reviewed-by: Jessica Zhang Tested-by: Jessica Zhang # Trogdor (sc7180) Patchwork: https://patchwork.freedesktop.org/patch/527985/ Link: https://lore.kernel.org/r/6f33219dc848ccd7122bce6933338033aa18c33c@lausen.nl Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 11 +++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 1 + 3 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index d95540309d4d..1e9658537a65 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -536,6 +536,16 @@ static const struct dpu_format dpu_format_map_ubwc[] = { true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED, DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), + /* XRGB2101010 and ARGB2101010 purposely have the same color + * ordering. The hardware only supports ARGB2101010 UBWC + * natively. + */ + INTERLEAVED_RGB_FMT_TILED(ARGB2101010, + COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, + C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, + true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED, + DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), + PSEUDO_YUV_FMT_TILED(NV12, 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, C1_B_Cb, C2_R_Cr, @@ -591,6 +601,7 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt) {DRM_FORMAT_XBGR8888, COLOR_FMT_RGBA8888_UBWC}, {DRM_FORMAT_XRGB8888, COLOR_FMT_RGBA8888_UBWC}, {DRM_FORMAT_ABGR2101010, COLOR_FMT_RGBA1010102_UBWC}, + {DRM_FORMAT_ARGB2101010, COLOR_FMT_RGBA1010102_UBWC}, {DRM_FORMAT_XRGB2101010, COLOR_FMT_RGBA1010102_UBWC}, {DRM_FORMAT_XBGR2101010, COLOR_FMT_RGBA1010102_UBWC}, {DRM_FORMAT_BGR565, COLOR_FMT_RGB565_UBWC}, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 7b8a5a5cfec7..3da3d6223fa2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -192,6 +192,7 @@ static const uint32_t plane_formats[] = { DRM_FORMAT_RGBX8888, DRM_FORMAT_BGRX8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB2101010, DRM_FORMAT_XRGB2101010, DRM_FORMAT_RGB888, DRM_FORMAT_BGR888, @@ -221,6 +222,7 @@ static const uint32_t plane_formats_yuv[] = { DRM_FORMAT_RGBA8888, DRM_FORMAT_BGRX8888, DRM_FORMAT_BGRA8888, + DRM_FORMAT_ARGB2101010, DRM_FORMAT_XRGB2101010, DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index bfd5be89e8b8..0ed6a1a114c7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -69,6 +69,7 @@ static const uint32_t qcom_compressed_supported_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB2101010, DRM_FORMAT_XRGB2101010, DRM_FORMAT_BGR565, From b187794e70d5b0ba953f6964744dd6a67f708e49 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:22 +0300 Subject: [PATCH 06/42] drm/msm/dpu: rename struct dpu_hw_pipe(_cfg) to dpu_hw_sspp(_cfg) For all hardware blocks except SSPP the corresponding struct is named after the block. Rename dpu_hw_pipe (SSPP structure) to dpu_hw_sspp. Also rename struct dpu_hw_pipe_cfg to dpu_hw_sspp_cfg to follow this change. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527312/ Link: https://lore.kernel.org/r/20230316161653.4106395-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 49 +++++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 53 +++++++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 20 ++++---- 3 files changed, 62 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 4246ab0b3bee..3e65bfd65b62 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -136,7 +136,7 @@ #define TS_CLK 19200000 -static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx, +static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx, int s_id, u32 *idx) { @@ -168,7 +168,7 @@ static int _sspp_subblk_offset(struct dpu_hw_pipe *ctx, return rc; } -static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx, +static void dpu_hw_sspp_setup_multirect(struct dpu_hw_sspp *ctx, enum dpu_sspp_multirect_index index, enum dpu_sspp_multirect_mode mode) { @@ -197,7 +197,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask); } -static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx, +static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) { u32 idx; @@ -218,7 +218,7 @@ static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(&ctx->hw, SSPP_VIG_OP_MODE + idx, opmode); } -static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx, +static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) { u32 idx; @@ -239,7 +239,7 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx, /* * Setup source pixel format, flip, */ -static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx, +static void dpu_hw_sspp_setup_format(struct dpu_hw_sspp *ctx, const struct dpu_format *fmt, u32 flags, enum dpu_sspp_multirect_index rect_mode) { @@ -360,7 +360,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31)); } -static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx, +static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, struct dpu_hw_pixel_ext *pe_ext) { struct dpu_hw_blk_reg_map *c; @@ -418,8 +418,8 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_pipe *ctx, tot_req_pixels[3]); } -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *sspp, +static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, + struct dpu_hw_sspp_cfg *sspp, void *scaler_cfg) { u32 idx; @@ -434,7 +434,7 @@ static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_pipe *ctx, sspp->layout.format); } -static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx) +static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx) { u32 idx; @@ -447,8 +447,8 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx) /* * dpu_hw_sspp_setup_rects() */ -static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *cfg, +static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx, + struct dpu_hw_sspp_cfg *cfg, enum dpu_sspp_multirect_index rect_index) { struct dpu_hw_blk_reg_map *c; @@ -516,8 +516,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1); } -static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *cfg, +static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_sspp *ctx, + struct dpu_hw_sspp_cfg *cfg, enum dpu_sspp_multirect_index rect_mode) { int i; @@ -543,7 +543,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx, } } -static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx, +static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data) { u32 idx; @@ -560,7 +560,7 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx, dpu_hw_csc_setup(&ctx->hw, idx, data, csc10); } -static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum +static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_sspp *ctx, u32 color, enum dpu_sspp_multirect_index rect_index) { u32 idx; @@ -575,7 +575,7 @@ static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum color); } -static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx, +static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_sspp *ctx, u32 danger_lut, u32 safe_lut) { @@ -588,7 +588,7 @@ static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT + idx, safe_lut); } -static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx, +static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx, u64 creq_lut) { u32 idx; @@ -605,7 +605,7 @@ static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_pipe *ctx, } } -static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx, +static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, struct dpu_hw_pipe_qos_cfg *cfg) { u32 idx; @@ -630,7 +630,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl); } -static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx, +static void dpu_hw_sspp_setup_cdp(struct dpu_hw_sspp *ctx, struct dpu_hw_cdp_cfg *cfg, enum dpu_sspp_multirect_index index) { @@ -661,7 +661,7 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_hw_pipe *ctx, DPU_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl); } -static void _setup_layer_ops(struct dpu_hw_pipe *c, +static void _setup_layer_ops(struct dpu_hw_sspp *c, unsigned long features) { if (test_bit(DPU_SSPP_SRC, &features)) { @@ -699,7 +699,8 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c, } #ifdef CONFIG_DEBUG_FS -int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry) +int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, + struct dentry *entry) { const struct dpu_sspp_cfg *cfg = hw_pipe->cap; const struct dpu_sspp_sub_blks *sblk = cfg->sblk; @@ -783,10 +784,10 @@ static const struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, return ERR_PTR(-ENOMEM); } -struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, +struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx, void __iomem *addr, const struct dpu_mdss_cfg *catalog) { - struct dpu_hw_pipe *hw_pipe; + struct dpu_hw_sspp *hw_pipe; const struct dpu_sspp_cfg *cfg; if (!addr || !catalog) @@ -812,7 +813,7 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, return hw_pipe; } -void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx) +void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx) { kfree(ctx); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 0c95b7e64f6c..bbff908e6dbe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -10,7 +10,7 @@ #include "dpu_hw_util.h" #include "dpu_formats.h" -struct dpu_hw_pipe; +struct dpu_hw_sspp; /** * Flags @@ -153,7 +153,7 @@ struct dpu_hw_pixel_ext { }; /** - * struct dpu_hw_pipe_cfg : Pipe description + * struct dpu_hw_sspp_cfg : SSPP configuration * @layout: format layout information for programming buffer to hardware * @src_rect: src ROI, caller takes into account the different operations * such as decimation, flip etc to program this field @@ -161,7 +161,7 @@ struct dpu_hw_pixel_ext { * @index: index of the rectangle of SSPP * @mode: parallel or time multiplex multirect mode */ -struct dpu_hw_pipe_cfg { +struct dpu_hw_sspp_cfg { struct dpu_hw_fmt_layout layout; struct drm_rect src_rect; struct drm_rect dst_rect; @@ -214,7 +214,7 @@ struct dpu_hw_sspp_ops { * @flags: Extra flags for format config * @index: rectangle index in multirect */ - void (*setup_format)(struct dpu_hw_pipe *ctx, + void (*setup_format)(struct dpu_hw_sspp *ctx, const struct dpu_format *fmt, u32 flags, enum dpu_sspp_multirect_index index); @@ -224,8 +224,8 @@ struct dpu_hw_sspp_ops { * @cfg: Pointer to pipe config structure * @index: rectangle index in multirect */ - void (*setup_rects)(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *cfg, + void (*setup_rects)(struct dpu_hw_sspp *ctx, + struct dpu_hw_sspp_cfg *cfg, enum dpu_sspp_multirect_index index); /** @@ -233,7 +233,7 @@ struct dpu_hw_sspp_ops { * @ctx: Pointer to pipe context * @pe_ext: Pointer to pixel ext settings */ - void (*setup_pe)(struct dpu_hw_pipe *ctx, + void (*setup_pe)(struct dpu_hw_sspp *ctx, struct dpu_hw_pixel_ext *pe_ext); /** @@ -242,8 +242,8 @@ struct dpu_hw_sspp_ops { * @cfg: Pointer to pipe config structure * @index: rectangle index in multirect */ - void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *cfg, + void (*setup_sourceaddress)(struct dpu_hw_sspp *ctx, + struct dpu_hw_sspp_cfg *cfg, enum dpu_sspp_multirect_index index); /** @@ -251,7 +251,7 @@ struct dpu_hw_sspp_ops { * @ctx: Pointer to pipe context * @data: Pointer to config structure */ - void (*setup_csc)(struct dpu_hw_pipe *ctx, const struct dpu_csc_cfg *data); + void (*setup_csc)(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data); /** * setup_solidfill - enable/disable colorfill @@ -260,7 +260,7 @@ struct dpu_hw_sspp_ops { * @flags: Pipe flags * @index: rectangle index in multirect */ - void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color, + void (*setup_solidfill)(struct dpu_hw_sspp *ctx, u32 color, enum dpu_sspp_multirect_index index); /** @@ -270,7 +270,7 @@ struct dpu_hw_sspp_ops { * @mode: parallel fetch / time multiplex multirect mode */ - void (*setup_multirect)(struct dpu_hw_pipe *ctx, + void (*setup_multirect)(struct dpu_hw_sspp *ctx, enum dpu_sspp_multirect_index index, enum dpu_sspp_multirect_mode mode); @@ -279,7 +279,7 @@ struct dpu_hw_sspp_ops { * @ctx: Pointer to pipe context * @cfg: Pointer to config structure */ - void (*setup_sharpening)(struct dpu_hw_pipe *ctx, + void (*setup_sharpening)(struct dpu_hw_sspp *ctx, struct dpu_hw_sharp_cfg *cfg); /** @@ -289,7 +289,7 @@ struct dpu_hw_sspp_ops { * @safe_lut: LUT for generate safe level based on fill level * */ - void (*setup_danger_safe_lut)(struct dpu_hw_pipe *ctx, + void (*setup_danger_safe_lut)(struct dpu_hw_sspp *ctx, u32 danger_lut, u32 safe_lut); @@ -299,7 +299,7 @@ struct dpu_hw_sspp_ops { * @creq_lut: LUT for generate creq level based on fill level * */ - void (*setup_creq_lut)(struct dpu_hw_pipe *ctx, + void (*setup_creq_lut)(struct dpu_hw_sspp *ctx, u64 creq_lut); /** @@ -308,7 +308,7 @@ struct dpu_hw_sspp_ops { * @cfg: Pointer to pipe QoS configuration * */ - void (*setup_qos_ctrl)(struct dpu_hw_pipe *ctx, + void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx, struct dpu_hw_pipe_qos_cfg *cfg); /** @@ -316,7 +316,7 @@ struct dpu_hw_sspp_ops { * @ctx: Pointer to pipe context * @cfg: Pointer to histogram configuration */ - void (*setup_histogram)(struct dpu_hw_pipe *ctx, + void (*setup_histogram)(struct dpu_hw_sspp *ctx, void *cfg); /** @@ -325,15 +325,15 @@ struct dpu_hw_sspp_ops { * @pipe_cfg: Pointer to pipe configuration * @scaler_cfg: Pointer to scaler configuration */ - void (*setup_scaler)(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *pipe_cfg, + void (*setup_scaler)(struct dpu_hw_sspp *ctx, + struct dpu_hw_sspp_cfg *pipe_cfg, void *scaler_cfg); /** * get_scaler_ver - get scaler h/w version * @ctx: Pointer to pipe context */ - u32 (*get_scaler_ver)(struct dpu_hw_pipe *ctx); + u32 (*get_scaler_ver)(struct dpu_hw_sspp *ctx); /** * setup_cdp - setup client driven prefetch @@ -341,13 +341,13 @@ struct dpu_hw_sspp_ops { * @cfg: Pointer to cdp configuration * @index: rectangle index in multirect */ - void (*setup_cdp)(struct dpu_hw_pipe *ctx, + void (*setup_cdp)(struct dpu_hw_sspp *ctx, struct dpu_hw_cdp_cfg *cfg, enum dpu_sspp_multirect_index index); }; /** - * struct dpu_hw_pipe - pipe description + * struct dpu_hw_sspp - pipe description * @base: hardware block base structure * @hw: block hardware details * @catalog: back pointer to catalog @@ -356,7 +356,7 @@ struct dpu_hw_sspp_ops { * @cap: pointer to layer_cfg * @ops: pointer to operations possible for this pipe */ -struct dpu_hw_pipe { +struct dpu_hw_sspp { struct dpu_hw_blk base; struct dpu_hw_blk_reg_map hw; const struct dpu_mdss_cfg *catalog; @@ -378,7 +378,7 @@ struct dpu_kms; * @addr: Mapped register io address of MDP * @catalog : Pointer to mdss catalog data */ -struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, +struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx, void __iomem *addr, const struct dpu_mdss_cfg *catalog); /** @@ -386,10 +386,11 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, * should be called during Hw pipe cleanup. * @ctx: Pointer to SSPP driver context returned by dpu_hw_sspp_init */ -void dpu_hw_sspp_destroy(struct dpu_hw_pipe *ctx); +void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx); void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root); -int _dpu_hw_sspp_init_debugfs(struct dpu_hw_pipe *hw_pipe, struct dpu_kms *kms, struct dentry *entry); +int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, + struct dentry *entry); #endif /*_DPU_HW_SSPP_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 0ed6a1a114c7..faf56f599a9e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -105,7 +105,7 @@ struct dpu_plane { enum dpu_sspp pipe; - struct dpu_hw_pipe *pipe_hw; + struct dpu_hw_sspp *pipe_hw; uint32_t color_fill; bool is_error; bool is_rt_pipe; @@ -138,7 +138,7 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) */ static void _dpu_plane_calc_bw(struct drm_plane *plane, struct drm_framebuffer *fb, - struct dpu_hw_pipe_cfg *pipe_cfg) + struct dpu_hw_sspp_cfg *pipe_cfg) { struct dpu_plane_state *pstate; struct drm_display_mode *mode; @@ -193,7 +193,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, * Result: Updates calculated clock in the plane state. * Clock equation: dst_w * v_total * fps * (src_h / dst_h) */ -static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_pipe_cfg *pipe_cfg) +static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_sspp_cfg *pipe_cfg) { struct dpu_plane_state *pstate; struct drm_display_mode *mode; @@ -277,7 +277,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, * @pipe_cfg: Pointer to pipe configuration */ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, - struct drm_framebuffer *fb, struct dpu_hw_pipe_cfg *pipe_cfg) + struct drm_framebuffer *fb, struct dpu_hw_sspp_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); const struct dpu_format *fmt = NULL; @@ -420,7 +420,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, * @pipe_cfg: Pointer to pipe configuration */ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, - struct drm_crtc *crtc, struct dpu_hw_pipe_cfg *pipe_cfg) + struct drm_crtc *crtc, struct dpu_hw_sspp_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_vbif_set_ot_params ot_params; @@ -468,7 +468,7 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane) static void _dpu_plane_set_scanout(struct drm_plane *plane, struct dpu_plane_state *pstate, - struct dpu_hw_pipe_cfg *pipe_cfg, + struct dpu_hw_sspp_cfg *pipe_cfg, struct drm_framebuffer *fb) { struct dpu_plane *pdpu = to_dpu_plane(plane); @@ -636,7 +636,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, struct dpu_plane_state *pstate, const struct dpu_format *fmt, bool color_fill, - struct dpu_hw_pipe_cfg *pipe_cfg) + struct dpu_hw_sspp_cfg *pipe_cfg) { const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); struct dpu_hw_scaler3_cfg scaler3_cfg; @@ -692,7 +692,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, const struct dpu_format *fmt; const struct drm_plane *plane = &pdpu->base; struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); - struct dpu_hw_pipe_cfg pipe_cfg; + struct dpu_hw_sspp_cfg pipe_cfg; DPU_DEBUG_PLANE(pdpu, "\n"); @@ -1130,9 +1130,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) bool is_rt_pipe; const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(fb)); - struct dpu_hw_pipe_cfg pipe_cfg; + struct dpu_hw_sspp_cfg pipe_cfg; - memset(&pipe_cfg, 0, sizeof(struct dpu_hw_pipe_cfg)); + memset(&pipe_cfg, 0, sizeof(struct dpu_hw_sspp_cfg)); _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb); From 64caf60dd9f71f25508695ec58abce9ebb15987d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:23 +0300 Subject: [PATCH 07/42] drm/msm/dpu: move SSPP allocation to the RM Follow the example of all other hw blocks and initialize SSPP blocks in Resource Manager. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527313/ Link: https://lore.kernel.org/r/20230316161653.4106395-3-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 17 ++++------------- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 12 ++++++++++++ 3 files changed, 38 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index faf56f599a9e..229f6f3146c5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1276,8 +1276,6 @@ static void dpu_plane_destroy(struct drm_plane *plane) /* this will destroy the states as well */ drm_plane_cleanup(plane); - dpu_hw_sspp_destroy(pdpu->pipe_hw); - kfree(pdpu); } } @@ -1483,14 +1481,10 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, pdpu->pipe = pipe; /* initialize underlying h/w driver */ - pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog); - if (IS_ERR(pdpu->pipe_hw)) { - DPU_ERROR("[%u]SSPP init failed\n", pipe); - ret = PTR_ERR(pdpu->pipe_hw); + pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); + if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { + DPU_ERROR("[%u]SSPP is invalid\n", pipe); goto clean_plane; - } else if (!pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { - DPU_ERROR("[%u]SSPP init returned invalid cfg\n", pipe); - goto clean_sspp; } format_list = pdpu->pipe_hw->cap->sblk->format_list; @@ -1500,7 +1494,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, format_list, num_formats, supported_format_modifiers, type, NULL); if (ret) - goto clean_sspp; + goto clean_plane; pdpu->catalog = kms->catalog; @@ -1533,9 +1527,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, pipe, plane->base.id); return plane; -clean_sspp: - if (pdpu && pdpu->pipe_hw) - dpu_hw_sspp_destroy(pdpu->pipe_hw); clean_plane: kfree(pdpu); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 66c1b70d244f..f4dda88a73f7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -8,6 +8,7 @@ #include "dpu_hw_lm.h" #include "dpu_hw_ctl.h" #include "dpu_hw_pingpong.h" +#include "dpu_hw_sspp.h" #include "dpu_hw_intf.h" #include "dpu_hw_wb.h" #include "dpu_hw_dspp.h" @@ -91,6 +92,9 @@ int dpu_rm_destroy(struct dpu_rm *rm) for (i = 0; i < ARRAY_SIZE(rm->hw_wb); i++) dpu_hw_wb_destroy(rm->hw_wb[i]); + for (i = 0; i < ARRAY_SIZE(rm->hw_sspp); i++) + dpu_hw_sspp_destroy(rm->hw_sspp[i]); + return 0; } @@ -255,6 +259,24 @@ int dpu_rm_init(struct dpu_rm *rm, rm->dsc_blks[dsc->id - DSC_0] = &hw->base; } + for (i = 0; i < cat->sspp_count; i++) { + struct dpu_hw_sspp *hw; + const struct dpu_sspp_cfg *sspp = &cat->sspp[i]; + + if (sspp->id < SSPP_NONE || sspp->id >= SSPP_MAX) { + DPU_ERROR("skip intf %d with invalid id\n", sspp->id); + continue; + } + + hw = dpu_hw_sspp_init(sspp->id, mmio, cat); + if (IS_ERR(hw)) { + rc = PTR_ERR(hw); + DPU_ERROR("failed sspp object creation: err %d\n", rc); + goto fail; + } + rm->hw_sspp[sspp->id - SSPP_NONE] = hw; + } + return 0; fail: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index 59de72b381f9..d62c2edb2460 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -21,6 +21,7 @@ struct dpu_global_state; * @hw_intf: array of intf hardware resources * @hw_wb: array of wb hardware resources * @dspp_blks: array of dspp hardware resources + * @hw_sspp: array of sspp hardware resources */ struct dpu_rm { struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0]; @@ -31,6 +32,7 @@ struct dpu_rm { struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0]; struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0]; struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0]; + struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE]; }; /** @@ -108,5 +110,15 @@ static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_ return rm->hw_wb[wb_idx - WB_0]; } +/** + * dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index. + * @rm: DPU Resource Manager handle + * @sspp_idx: SSPP index + */ +static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx) +{ + return rm->hw_sspp[sspp_idx - SSPP_NONE]; +} + #endif /* __DPU_RM_H__ */ From dab5ace44cdaa6aa2a5795d027b9268dd83a32c0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:24 +0300 Subject: [PATCH 08/42] drm/msm/dpu: move SSPP debugfs creation to dpu_kms.c As SSPP blocks are now visible through dpu_kms->rm.sspp_blocks, move SSPP debugfs creation from dpu_plane to dpu_kms. We are going to break the 1:1 correspondence between planes and SSPPs, so it makes no sense anymore to create SSPP debugfs entries in dpu_plane.c Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527317/ Link: https://lore.kernel.org/r/20230316161653.4106395-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 18 ++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 16 ---------------- 3 files changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index bbff908e6dbe..c30f168b6c0a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -388,7 +388,6 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx, */ void dpu_hw_sspp_destroy(struct dpu_hw_sspp *ctx); -void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root); int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, struct dentry *entry); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 75faaf4f7547..e7b24b21ef1b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -250,6 +250,24 @@ void dpu_debugfs_create_regset32(const char *name, umode_t mode, debugfs_create_file(name, mode, parent, regset, &dpu_regset32_fops); } +static void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root) +{ + struct dentry *entry = debugfs_create_dir("sspp", debugfs_root); + int i; + + if (IS_ERR(entry)) + return; + + for (i = SSPP_NONE; i < SSPP_MAX; i++) { + struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i); + + if (!hw) + continue; + + _dpu_hw_sspp_init_debugfs(hw, dpu_kms, entry); + } +} + static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) { struct dpu_kms *dpu_kms = to_dpu_kms(kms); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 229f6f3146c5..33bb600efde5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1400,22 +1400,6 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL); pm_runtime_put_sync(&dpu_kms->pdev->dev); } - -/* SSPP live inside dpu_plane private data only. Enumerate them here. */ -void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root) -{ - struct drm_plane *plane; - struct dentry *entry = debugfs_create_dir("sspp", debugfs_root); - - if (IS_ERR(entry)) - return; - - drm_for_each_plane(plane, dpu_kms->dev) { - struct dpu_plane *pdpu = to_dpu_plane(plane); - - _dpu_hw_sspp_init_debugfs(pdpu->pipe_hw, dpu_kms, entry); - } -} #endif static bool dpu_plane_format_mod_supported(struct drm_plane *plane, From 5d1b072aa89c73ada5bbe95299c2058990875c99 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:25 +0300 Subject: [PATCH 09/42] drm/msm/dpu: drop EAGAIN check from dpu_format_populate_layout The pipe's layout is not cached, corresponding data structure is zeroed out each time in the dpu_plane_sspp_atomic_update(), right before the call to _dpu_plane_set_scanout() -> dpu_format_populate_layout(). Drop plane_addr comparison against previous layout and corresponding EAGAIN handling. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527314/ Link: https://lore.kernel.org/r/20230316161653.4106395-5-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 10 +--------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +--- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index 1e9658537a65..e366ab134249 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -929,8 +929,7 @@ int dpu_format_populate_layout( struct drm_framebuffer *fb, struct dpu_hw_fmt_layout *layout) { - uint32_t plane_addr[DPU_MAX_PLANES]; - int i, ret; + int ret; if (!fb || !layout) { DRM_ERROR("invalid arguments\n"); @@ -951,9 +950,6 @@ int dpu_format_populate_layout( if (ret) return ret; - for (i = 0; i < DPU_MAX_PLANES; ++i) - plane_addr[i] = layout->plane_addr[i]; - /* Populate the addresses given the fb */ if (DPU_FORMAT_IS_UBWC(layout->format) || DPU_FORMAT_IS_TILE(layout->format)) @@ -961,10 +957,6 @@ int dpu_format_populate_layout( else ret = _dpu_format_populate_addrs_linear(aspace, fb, layout); - /* check if anything changed */ - if (!ret && !memcmp(plane_addr, layout->plane_addr, sizeof(plane_addr))) - ret = -EAGAIN; - return ret; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 33bb600efde5..b91c99f05802 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -477,9 +477,7 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane, int ret; ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); - if (ret == -EAGAIN) - DPU_DEBUG_PLANE(pdpu, "not updating same src addrs\n"); - else if (ret) + if (ret) DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); else if (pdpu->pipe_hw->ops.setup_sourceaddress) { trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx, From 7f38ec140d9c1f257eb55d45d224a7203998d3cc Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:26 +0300 Subject: [PATCH 10/42] drm/msm/dpu: move pipe_hw to dpu_plane_state In preparation to adding fully virtualized planes, move struct dpu_hw_sspp instance from struct dpu_plane to struct dpu_plane_state, as it will become a part of state (variable, changes during runtime) rather than part of a plane (ideally should be statically allocated during boot). The sspp pointer is set at the dpu_plane_reset(), since this is the function which allocates the state. Once we have fully virtual plane<->SSPP relationship, the SSPP will be allocated dynamically in the dpu_plane_atomic_check() function. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527322/ Link: https://lore.kernel.org/r/20230316161653.4106395-6-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 107 ++++++++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 + 2 files changed, 62 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index b91c99f05802..9dfbad6a949f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -105,7 +105,6 @@ struct dpu_plane { enum dpu_sspp pipe; - struct dpu_hw_sspp *pipe_hw; uint32_t color_fill; bool is_error; bool is_rt_pipe; @@ -280,6 +279,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, struct drm_framebuffer *fb, struct dpu_hw_sspp_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); const struct dpu_format *fmt = NULL; u64 qos_lut; u32 total_fl = 0, lut_usage; @@ -311,7 +311,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, fmt ? (char *)&fmt->base.pixel_format : NULL, pdpu->is_rt_pipe, total_fl, qos_lut); - pdpu->pipe_hw->ops.setup_creq_lut(pdpu->pipe_hw, qos_lut); + pstate->hw_sspp->ops.setup_creq_lut(pstate->hw_sspp, qos_lut); } /** @@ -323,6 +323,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, struct drm_framebuffer *fb) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); const struct dpu_format *fmt = NULL; u32 danger_lut, safe_lut; @@ -362,7 +363,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, danger_lut, safe_lut); - pdpu->pipe_hw->ops.setup_danger_safe_lut(pdpu->pipe_hw, + pstate->hw_sspp->ops.setup_danger_safe_lut(pstate->hw_sspp, danger_lut, safe_lut); } @@ -376,14 +377,15 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, bool enable, u32 flags) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { - pipe_qos_cfg.creq_vblank = pdpu->pipe_hw->cap->sblk->creq_vblank; + pipe_qos_cfg.creq_vblank = pstate->hw_sspp->cap->sblk->creq_vblank; pipe_qos_cfg.danger_vblank = - pdpu->pipe_hw->cap->sblk->danger_vblank; + pstate->hw_sspp->cap->sblk->danger_vblank; pipe_qos_cfg.vblank_en = enable; } @@ -409,7 +411,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, pipe_qos_cfg.danger_vblank, pdpu->is_rt_pipe); - pdpu->pipe_hw->ops.setup_qos_ctrl(pdpu->pipe_hw, + pstate->hw_sspp->ops.setup_qos_ctrl(pstate->hw_sspp, &pipe_qos_cfg); } @@ -423,18 +425,19 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, struct drm_crtc *crtc, struct dpu_hw_sspp_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_vbif_set_ot_params ot_params; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); memset(&ot_params, 0, sizeof(ot_params)); - ot_params.xin_id = pdpu->pipe_hw->cap->xin_id; - ot_params.num = pdpu->pipe_hw->idx - SSPP_NONE; + ot_params.xin_id = pstate->hw_sspp->cap->xin_id; + ot_params.num = pstate->hw_sspp->idx - SSPP_NONE; ot_params.width = drm_rect_width(&pipe_cfg->src_rect); ot_params.height = drm_rect_height(&pipe_cfg->src_rect); ot_params.is_wfd = !pdpu->is_rt_pipe; ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); ot_params.vbif_idx = VBIF_RT; - ot_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; + ot_params.clk_ctrl = pstate->hw_sspp->cap->clk_ctrl; ot_params.rd = true; dpu_vbif_set_ot_limit(dpu_kms, &ot_params); @@ -447,14 +450,15 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, static void _dpu_plane_set_qos_remap(struct drm_plane *plane) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_vbif_set_qos_params qos_params; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); memset(&qos_params, 0, sizeof(qos_params)); qos_params.vbif_idx = VBIF_RT; - qos_params.clk_ctrl = pdpu->pipe_hw->cap->clk_ctrl; - qos_params.xin_id = pdpu->pipe_hw->cap->xin_id; - qos_params.num = pdpu->pipe_hw->idx - SSPP_VIG0; + qos_params.clk_ctrl = pstate->hw_sspp->cap->clk_ctrl; + qos_params.xin_id = pstate->hw_sspp->cap->xin_id; + qos_params.num = pstate->hw_sspp->idx - SSPP_VIG0; qos_params.is_rt = pdpu->is_rt_pipe; DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", @@ -479,11 +483,11 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane, ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); if (ret) DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); - else if (pdpu->pipe_hw->ops.setup_sourceaddress) { - trace_dpu_plane_set_scanout(pdpu->pipe_hw->idx, + else if (pstate->hw_sspp->ops.setup_sourceaddress) { + trace_dpu_plane_set_scanout(pstate->hw_sspp->idx, &pipe_cfg->layout, pstate->multirect_index); - pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg, + pstate->hw_sspp->ops.setup_sourceaddress(pstate->hw_sspp, pipe_cfg, pstate->multirect_index); } } @@ -535,7 +539,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, scale_cfg->src_height[i] /= chroma_subsmpl_v; } - if (pdpu->pipe_hw->cap->features & + if (pstate->hw_sspp->cap->features & BIT(DPU_SSPP_SCALER_QSEED4)) { scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; @@ -608,6 +612,7 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt) { + struct dpu_plane_state *pstate = to_dpu_plane_state(pdpu->base.state); const struct dpu_csc_cfg *csc_ptr; if (!pdpu) { @@ -618,7 +623,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons if (!DPU_FORMAT_IS_YUV(fmt)) return NULL; - if (BIT(DPU_SSPP_CSC_10BIT) & pdpu->pipe_hw->cap->features) + if (BIT(DPU_SSPP_CSC_10BIT) & pstate->hw_sspp->cap->features) csc_ptr = &dpu_csc10_YUV2RGB_601L; else csc_ptr = &dpu_csc_YUV2RGB_601L; @@ -661,8 +666,8 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, src_width, src_height, info->hsub, info->vsub); - if (pdpu->pipe_hw->ops.setup_pe) - pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, + if (pstate->hw_sspp->ops.setup_pe) + pstate->hw_sspp->ops.setup_pe(pstate->hw_sspp, &pixel_ext); /** @@ -670,9 +675,9 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, * bypassed. Still we need to update alpha and bitwidth * ONLY for RECT0 */ - if (pdpu->pipe_hw->ops.setup_scaler && + if (pstate->hw_sspp->ops.setup_scaler && pstate->multirect_index != DPU_SSPP_RECT_1) - pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, + pstate->hw_sspp->ops.setup_scaler(pstate->hw_sspp, pipe_cfg, &scaler3_cfg); } @@ -701,8 +706,8 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); /* update sspp */ - if (fmt && pdpu->pipe_hw->ops.setup_solidfill) { - pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw, + if (fmt && pstate->hw_sspp->ops.setup_solidfill) { + pstate->hw_sspp->ops.setup_solidfill(pstate->hw_sspp, (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), pstate->multirect_index); @@ -716,13 +721,13 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, pipe_cfg.src_rect.y2 = drm_rect_height(&pipe_cfg.dst_rect); - if (pdpu->pipe_hw->ops.setup_format) - pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, + if (pstate->hw_sspp->ops.setup_format) + pstate->hw_sspp->ops.setup_format(pstate->hw_sspp, fmt, DPU_SSPP_SOLID_FILL, pstate->multirect_index); - if (pdpu->pipe_hw->ops.setup_rects) - pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, + if (pstate->hw_sspp->ops.setup_rects) + pstate->hw_sspp->ops.setup_rects(pstate->hw_sspp, &pipe_cfg, pstate->multirect_index); @@ -974,8 +979,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, uint32_t min_src_size, max_linewidth; unsigned int rotation; uint32_t supported_rotations; - const struct dpu_sspp_cfg *pipe_hw_caps = pdpu->pipe_hw->cap; - const struct dpu_sspp_sub_blks *sblk = pdpu->pipe_hw->cap->sblk; + const struct dpu_sspp_cfg *pipe_hw_caps = pstate->hw_sspp->cap; + const struct dpu_sspp_sub_blks *sblk = pstate->hw_sspp->cap->sblk; if (new_plane_state->crtc) crtc_state = drm_atomic_get_new_crtc_state(state, @@ -1088,12 +1093,12 @@ void dpu_plane_flush(struct drm_plane *plane) else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); - else if (pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_csc) { + else if (pstate->hw_sspp && pstate->hw_sspp->ops.setup_csc) { const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb)); const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt); if (csc_ptr) - pdpu->pipe_hw->ops.setup_csc(pdpu->pipe_hw, csc_ptr); + pstate->hw_sspp->ops.setup_csc(pstate->hw_sspp, csc_ptr); } /* flag h/w flush complete */ @@ -1163,21 +1168,21 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) return; } - if (pdpu->pipe_hw->ops.setup_rects) { - pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, + if (pstate->hw_sspp->ops.setup_rects) { + pstate->hw_sspp->ops.setup_rects(pstate->hw_sspp, &pipe_cfg, pstate->multirect_index); } _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); - if (pdpu->pipe_hw->ops.setup_multirect) - pdpu->pipe_hw->ops.setup_multirect( - pdpu->pipe_hw, + if (pstate->hw_sspp->ops.setup_multirect) + pstate->hw_sspp->ops.setup_multirect( + pstate->hw_sspp, pstate->multirect_index, pstate->multirect_mode); - if (pdpu->pipe_hw->ops.setup_format) { + if (pstate->hw_sspp->ops.setup_format) { unsigned int rotation = pstate->rotation; src_flags = 0x0; @@ -1192,10 +1197,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) src_flags |= DPU_SSPP_ROT_90; /* update format */ - pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags, + pstate->hw_sspp->ops.setup_format(pstate->hw_sspp, fmt, src_flags, pstate->multirect_index); - if (pdpu->pipe_hw->ops.setup_cdp) { + if (pstate->hw_sspp->ops.setup_cdp) { struct dpu_hw_cdp_cfg cdp_cfg; memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg)); @@ -1209,7 +1214,8 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) DPU_FORMAT_IS_TILE(fmt); cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; - pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg, pstate->multirect_index); + pstate->hw_sspp->ops.setup_cdp(pstate->hw_sspp, &cdp_cfg, + pstate->multirect_index); } } @@ -1349,10 +1355,9 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p, const struct drm_plane_state *state) { const struct dpu_plane_state *pstate = to_dpu_plane_state(state); - const struct dpu_plane *pdpu = to_dpu_plane(state->plane); drm_printf(p, "\tstage=%d\n", pstate->stage); - drm_printf(p, "\tsspp=%s\n", pdpu->pipe_hw->cap->name); + drm_printf(p, "\tsspp=%s\n", pstate->hw_sspp->cap->name); drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode)); drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index)); } @@ -1361,6 +1366,7 @@ static void dpu_plane_reset(struct drm_plane *plane) { struct dpu_plane *pdpu; struct dpu_plane_state *pstate; + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); if (!plane) { DPU_ERROR("invalid plane\n"); @@ -1382,6 +1388,12 @@ static void dpu_plane_reset(struct drm_plane *plane) return; } + /* + * Set the SSPP here until we have proper virtualized DPU planes. + * This is the place where the state is allocated, so fill it fully. + */ + pstate->hw_sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + __drm_atomic_helper_plane_reset(plane, &pstate->base); } @@ -1446,6 +1458,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, struct dpu_plane *pdpu; struct msm_drm_private *priv = dev->dev_private; struct dpu_kms *kms = to_dpu_kms(priv->kms); + struct dpu_hw_sspp *pipe_hw; uint32_t num_formats; uint32_t supported_rotations; int ret = -EINVAL; @@ -1463,14 +1476,14 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, pdpu->pipe = pipe; /* initialize underlying h/w driver */ - pdpu->pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); - if (!pdpu->pipe_hw || !pdpu->pipe_hw->cap || !pdpu->pipe_hw->cap->sblk) { + pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); + if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { DPU_ERROR("[%u]SSPP is invalid\n", pipe); goto clean_plane; } - format_list = pdpu->pipe_hw->cap->sblk->format_list; - num_formats = pdpu->pipe_hw->cap->sblk->num_formats; + format_list = pipe_hw->cap->sblk->format_list; + num_formats = pipe_hw->cap->sblk->num_formats; ret = drm_universal_plane_init(dev, plane, 0xff, &dpu_plane_funcs, format_list, num_formats, @@ -1492,7 +1505,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; - if (pdpu->pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) + if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) supported_rotations |= DRM_MODE_ROTATE_MASK; drm_plane_create_rotation_property(plane, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index b7b1b05199c2..08a4b6a99f51 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -18,6 +18,7 @@ * struct dpu_plane_state: Define dpu extension of drm plane state object * @base: base drm plane state object * @aspace: pointer to address space for input/output buffers + * @hw_sspp: pointer to corresponding SSPP instance * @stage: assigned by crtc blender * @needs_qos_remap: qos remap settings need to be updated * @multirect_index: index of the rectangle of SSPP @@ -31,6 +32,7 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; + struct dpu_hw_sspp *hw_sspp; enum dpu_stage stage; bool needs_qos_remap; uint32_t multirect_index; From 19e98654e7a48ea65bae9fd9bcac453fdb4fda0a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:27 +0300 Subject: [PATCH 11/42] drm/msm/dpu: drop dpu_plane_pipe function There no more need for the dpu_plane_pipe() function, crtc code can access pstate->pipe_hw.idx directly. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527320/ Link: https://lore.kernel.org/r/20230316161653.4106395-7-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 5 ----- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 7 ------- 3 files changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 1bdf78cae12a..b1a6de44a88a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -432,7 +432,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, pstate = to_dpu_plane_state(state); fb = state->fb; - sspp_idx = dpu_plane_pipe(plane); + sspp_idx = pstate->hw_sspp->idx; set_bit(sspp_idx, fetch_active); DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", @@ -1227,7 +1227,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, pstates[cnt].dpu_pstate = dpu_pstate; pstates[cnt].drm_pstate = pstate; pstates[cnt].stage = pstate->normalized_zpos; - pstates[cnt].pipe_id = dpu_plane_pipe(plane); + pstates[cnt].pipe_id = to_dpu_plane_state(pstate)->hw_sspp->idx; dpu_pstate->needs_dirtyfb = needs_dirtyfb; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 9dfbad6a949f..30438b7ce6f7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1443,11 +1443,6 @@ static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { .atomic_update = dpu_plane_atomic_update, }; -enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane) -{ - return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE; -} - /* initialize plane */ struct drm_plane *dpu_plane_init(struct drm_device *dev, uint32_t pipe, enum drm_plane_type type, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 08a4b6a99f51..25e261cabadc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -59,13 +59,6 @@ struct dpu_multirect_plane_states { #define to_dpu_plane_state(x) \ container_of(x, struct dpu_plane_state, base) -/** - * dpu_plane_pipe - return sspp identifier for the given plane - * @plane: Pointer to DRM plane object - * Returns: sspp identifier of the given plane - */ -enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane); - /** * dpu_plane_flush - final plane operations before commit flush * @plane: Pointer to drm plane structure From 3cfcd1307af8f96420dd998c1c3fc07ce1e6d03a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:28 +0300 Subject: [PATCH 12/42] drm/msm/dpu: introduce struct dpu_sw_pipe Wrap SSPP and multirect index/mode into a single structure that represents software view on the pipe used. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527326/ Link: https://lore.kernel.org/r/20230316161653.4106395-8-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 133 ++++++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 6 +- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +- 5 files changed, 90 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index b1a6de44a88a..56da7598d08a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -432,7 +432,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, pstate = to_dpu_plane_state(state); fb = state->fb; - sspp_idx = pstate->hw_sspp->idx; + sspp_idx = pstate->pipe.sspp->idx; set_bit(sspp_idx, fetch_active); DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", @@ -451,11 +451,10 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, stage_cfg->stage[pstate->stage][stage_idx] = sspp_idx; stage_cfg->multirect_index[pstate->stage][stage_idx] = - pstate->multirect_index; + pstate->pipe.multirect_index; trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), state, pstate, stage_idx, - sspp_idx - SSPP_VIG0, format->base.pixel_format, fb ? fb->modifier : 0); @@ -1227,7 +1226,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, pstates[cnt].dpu_pstate = dpu_pstate; pstates[cnt].drm_pstate = pstate; pstates[cnt].stage = pstate->normalized_zpos; - pstates[cnt].pipe_id = to_dpu_plane_state(pstate)->hw_sspp->idx; + pstates[cnt].pipe_id = to_dpu_plane_state(pstate)->pipe.sspp->idx; dpu_pstate->needs_dirtyfb = needs_dirtyfb; @@ -1500,7 +1499,7 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); seq_printf(s, "\tmultirect: mode: %d index: %d\n", - pstate->multirect_mode, pstate->multirect_index); + pstate->pipe.multirect_mode, pstate->pipe.multirect_index); seq_puts(s, "\n"); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index c30f168b6c0a..13d9e04a5153 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -158,15 +158,11 @@ struct dpu_hw_pixel_ext { * @src_rect: src ROI, caller takes into account the different operations * such as decimation, flip etc to program this field * @dest_rect: destination ROI. - * @index: index of the rectangle of SSPP - * @mode: parallel or time multiplex multirect mode */ struct dpu_hw_sspp_cfg { struct dpu_hw_fmt_layout layout; struct drm_rect src_rect; struct drm_rect dst_rect; - enum dpu_sspp_multirect_index index; - enum dpu_sspp_multirect_mode mode; }; /** @@ -201,6 +197,18 @@ struct dpu_hw_pipe_ts_cfg { u64 time; }; +/** + * struct dpu_sw_pipe - software pipe description + * @sspp: backing SSPP pipe + * @index: index of the rectangle of SSPP + * @mode: parallel or time multiplex multirect mode + */ +struct dpu_sw_pipe { + struct dpu_hw_sspp *sspp; + enum dpu_sspp_multirect_index multirect_index; + enum dpu_sspp_multirect_mode multirect_mode; +}; + /** * struct dpu_hw_sspp_ops - interface to the SSPP Hw driver functions * Caller must call the init function to get the pipe context for each pipe diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 30438b7ce6f7..8109ad8f9d0a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -252,7 +252,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, ((src_width + 32) * fmt->bpp); } } else { - if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { + if (pstate->pipe.multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { total_fl = (fixed_buff_size / 2) * 2 / ((src_width + 32) * fmt->bpp); } else { @@ -311,7 +311,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, fmt ? (char *)&fmt->base.pixel_format : NULL, pdpu->is_rt_pipe, total_fl, qos_lut); - pstate->hw_sspp->ops.setup_creq_lut(pstate->hw_sspp, qos_lut); + pstate->pipe.sspp->ops.setup_creq_lut(pstate->pipe.sspp, qos_lut); } /** @@ -363,7 +363,7 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, danger_lut, safe_lut); - pstate->hw_sspp->ops.setup_danger_safe_lut(pstate->hw_sspp, + pstate->pipe.sspp->ops.setup_danger_safe_lut(pstate->pipe.sspp, danger_lut, safe_lut); } @@ -383,9 +383,9 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { - pipe_qos_cfg.creq_vblank = pstate->hw_sspp->cap->sblk->creq_vblank; + pipe_qos_cfg.creq_vblank = pstate->pipe.sspp->cap->sblk->creq_vblank; pipe_qos_cfg.danger_vblank = - pstate->hw_sspp->cap->sblk->danger_vblank; + pstate->pipe.sspp->cap->sblk->danger_vblank; pipe_qos_cfg.vblank_en = enable; } @@ -411,7 +411,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, pipe_qos_cfg.danger_vblank, pdpu->is_rt_pipe); - pstate->hw_sspp->ops.setup_qos_ctrl(pstate->hw_sspp, + pstate->pipe.sspp->ops.setup_qos_ctrl(pstate->pipe.sspp, &pipe_qos_cfg); } @@ -430,14 +430,14 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); memset(&ot_params, 0, sizeof(ot_params)); - ot_params.xin_id = pstate->hw_sspp->cap->xin_id; - ot_params.num = pstate->hw_sspp->idx - SSPP_NONE; + ot_params.xin_id = pstate->pipe.sspp->cap->xin_id; + ot_params.num = pstate->pipe.sspp->idx - SSPP_NONE; ot_params.width = drm_rect_width(&pipe_cfg->src_rect); ot_params.height = drm_rect_height(&pipe_cfg->src_rect); ot_params.is_wfd = !pdpu->is_rt_pipe; ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); ot_params.vbif_idx = VBIF_RT; - ot_params.clk_ctrl = pstate->hw_sspp->cap->clk_ctrl; + ot_params.clk_ctrl = pstate->pipe.sspp->cap->clk_ctrl; ot_params.rd = true; dpu_vbif_set_ot_limit(dpu_kms, &ot_params); @@ -456,9 +456,9 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane) memset(&qos_params, 0, sizeof(qos_params)); qos_params.vbif_idx = VBIF_RT; - qos_params.clk_ctrl = pstate->hw_sspp->cap->clk_ctrl; - qos_params.xin_id = pstate->hw_sspp->cap->xin_id; - qos_params.num = pstate->hw_sspp->idx - SSPP_VIG0; + qos_params.clk_ctrl = pstate->pipe.sspp->cap->clk_ctrl; + qos_params.xin_id = pstate->pipe.sspp->cap->xin_id; + qos_params.num = pstate->pipe.sspp->idx - SSPP_VIG0; qos_params.is_rt = pdpu->is_rt_pipe; DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", @@ -483,12 +483,12 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane, ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); if (ret) DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); - else if (pstate->hw_sspp->ops.setup_sourceaddress) { - trace_dpu_plane_set_scanout(pstate->hw_sspp->idx, + else if (pstate->pipe.sspp->ops.setup_sourceaddress) { + trace_dpu_plane_set_scanout(pstate->pipe.sspp->idx, &pipe_cfg->layout, - pstate->multirect_index); - pstate->hw_sspp->ops.setup_sourceaddress(pstate->hw_sspp, pipe_cfg, - pstate->multirect_index); + pstate->pipe.multirect_index); + pstate->pipe.sspp->ops.setup_sourceaddress(pstate->pipe.sspp, pipe_cfg, + pstate->pipe.multirect_index); } } @@ -539,7 +539,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, scale_cfg->src_height[i] /= chroma_subsmpl_v; } - if (pstate->hw_sspp->cap->features & + if (pstate->pipe.sspp->cap->features & BIT(DPU_SSPP_SCALER_QSEED4)) { scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; @@ -623,7 +623,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons if (!DPU_FORMAT_IS_YUV(fmt)) return NULL; - if (BIT(DPU_SSPP_CSC_10BIT) & pstate->hw_sspp->cap->features) + if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe.sspp->cap->features) csc_ptr = &dpu_csc10_YUV2RGB_601L; else csc_ptr = &dpu_csc_YUV2RGB_601L; @@ -666,8 +666,8 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, src_width, src_height, info->hsub, info->vsub); - if (pstate->hw_sspp->ops.setup_pe) - pstate->hw_sspp->ops.setup_pe(pstate->hw_sspp, + if (pstate->pipe.sspp->ops.setup_pe) + pstate->pipe.sspp->ops.setup_pe(pstate->pipe.sspp, &pixel_ext); /** @@ -675,9 +675,9 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, * bypassed. Still we need to update alpha and bitwidth * ONLY for RECT0 */ - if (pstate->hw_sspp->ops.setup_scaler && - pstate->multirect_index != DPU_SSPP_RECT_1) - pstate->hw_sspp->ops.setup_scaler(pstate->hw_sspp, + if (pstate->pipe.sspp->ops.setup_scaler && + pstate->pipe.multirect_index != DPU_SSPP_RECT_1) + pstate->pipe.sspp->ops.setup_scaler(pstate->pipe.sspp, pipe_cfg, &scaler3_cfg); } @@ -706,10 +706,10 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); /* update sspp */ - if (fmt && pstate->hw_sspp->ops.setup_solidfill) { - pstate->hw_sspp->ops.setup_solidfill(pstate->hw_sspp, + if (fmt && pstate->pipe.sspp->ops.setup_solidfill) { + pstate->pipe.sspp->ops.setup_solidfill(pstate->pipe.sspp, (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), - pstate->multirect_index); + pstate->pipe.multirect_index); /* override scaler/decimation if solid fill */ pipe_cfg.dst_rect = pstate->base.dst; @@ -721,15 +721,15 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, pipe_cfg.src_rect.y2 = drm_rect_height(&pipe_cfg.dst_rect); - if (pstate->hw_sspp->ops.setup_format) - pstate->hw_sspp->ops.setup_format(pstate->hw_sspp, + if (pstate->pipe.sspp->ops.setup_format) + pstate->pipe.sspp->ops.setup_format(pstate->pipe.sspp, fmt, DPU_SSPP_SOLID_FILL, - pstate->multirect_index); + pstate->pipe.multirect_index); - if (pstate->hw_sspp->ops.setup_rects) - pstate->hw_sspp->ops.setup_rects(pstate->hw_sspp, + if (pstate->pipe.sspp->ops.setup_rects) + pstate->pipe.sspp->ops.setup_rects(pstate->pipe.sspp, &pipe_cfg, - pstate->multirect_index); + pstate->pipe.multirect_index); _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg); } @@ -741,8 +741,8 @@ void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state) { struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state); - pstate->multirect_index = DPU_SSPP_RECT_SOLO; - pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; + pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; } int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) @@ -824,8 +824,8 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */ if (parallel_fetch_qualified) { - pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + pstate[R0]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + pstate[R1]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; goto done; } @@ -835,8 +835,8 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) if (dst[R1].y1 >= dst[R0].y2 + buffer_lines || dst[R0].y1 >= dst[R1].y2 + buffer_lines) { - pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; - pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; + pstate[R0]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; + pstate[R1]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; } else { DPU_ERROR( "No multirect mode possible for the planes (%d - %d)\n", @@ -846,13 +846,13 @@ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) } done: - pstate[R0]->multirect_index = DPU_SSPP_RECT_0; - pstate[R1]->multirect_index = DPU_SSPP_RECT_1; + pstate[R0]->pipe.multirect_index = DPU_SSPP_RECT_0; + pstate[R1]->pipe.multirect_index = DPU_SSPP_RECT_1; DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", - pstate[R0]->multirect_mode, pstate[R0]->multirect_index); + pstate[R0]->pipe.multirect_mode, pstate[R0]->pipe.multirect_index); DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n", - pstate[R1]->multirect_mode, pstate[R1]->multirect_index); + pstate[R1]->pipe.multirect_mode, pstate[R1]->pipe.multirect_index); return 0; } @@ -979,8 +979,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, uint32_t min_src_size, max_linewidth; unsigned int rotation; uint32_t supported_rotations; - const struct dpu_sspp_cfg *pipe_hw_caps = pstate->hw_sspp->cap; - const struct dpu_sspp_sub_blks *sblk = pstate->hw_sspp->cap->sblk; + const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap; + const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk; if (new_plane_state->crtc) crtc_state = drm_atomic_get_new_crtc_state(state, @@ -1093,12 +1093,12 @@ void dpu_plane_flush(struct drm_plane *plane) else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); - else if (pstate->hw_sspp && pstate->hw_sspp->ops.setup_csc) { + else if (pstate->pipe.sspp && pstate->pipe.sspp->ops.setup_csc) { const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb)); const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt); if (csc_ptr) - pstate->hw_sspp->ops.setup_csc(pstate->hw_sspp, csc_ptr); + pstate->pipe.sspp->ops.setup_csc(pstate->pipe.sspp, csc_ptr); } /* flag h/w flush complete */ @@ -1128,6 +1128,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) struct dpu_plane *pdpu = to_dpu_plane(plane); struct drm_plane_state *state = plane->state; struct dpu_plane_state *pstate = to_dpu_plane_state(state); + struct dpu_sw_pipe *pipe = &pstate->pipe; struct drm_crtc *crtc = state->crtc; struct drm_framebuffer *fb = state->fb; bool is_rt_pipe; @@ -1168,21 +1169,21 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) return; } - if (pstate->hw_sspp->ops.setup_rects) { - pstate->hw_sspp->ops.setup_rects(pstate->hw_sspp, + if (pipe->sspp->ops.setup_rects) { + pipe->sspp->ops.setup_rects(pipe->sspp, &pipe_cfg, - pstate->multirect_index); + pipe->multirect_index); } _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); - if (pstate->hw_sspp->ops.setup_multirect) - pstate->hw_sspp->ops.setup_multirect( - pstate->hw_sspp, - pstate->multirect_index, - pstate->multirect_mode); + if (pipe->sspp->ops.setup_multirect) + pipe->sspp->ops.setup_multirect( + pipe->sspp, + pipe->multirect_index, + pipe->multirect_mode); - if (pstate->hw_sspp->ops.setup_format) { + if (pipe->sspp->ops.setup_format) { unsigned int rotation = pstate->rotation; src_flags = 0x0; @@ -1197,10 +1198,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) src_flags |= DPU_SSPP_ROT_90; /* update format */ - pstate->hw_sspp->ops.setup_format(pstate->hw_sspp, fmt, src_flags, - pstate->multirect_index); + pipe->sspp->ops.setup_format(pipe->sspp, fmt, src_flags, + pipe->multirect_index); - if (pstate->hw_sspp->ops.setup_cdp) { + if (pipe->sspp->ops.setup_cdp) { struct dpu_hw_cdp_cfg cdp_cfg; memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg)); @@ -1214,8 +1215,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) DPU_FORMAT_IS_TILE(fmt); cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; - pstate->hw_sspp->ops.setup_cdp(pstate->hw_sspp, &cdp_cfg, - pstate->multirect_index); + pipe->sspp->ops.setup_cdp(pipe->sspp, &cdp_cfg, pipe->multirect_index); } } @@ -1243,7 +1243,7 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane) struct dpu_plane_state *pstate = to_dpu_plane_state(state); trace_dpu_plane_disable(DRMID(plane), false, - pstate->multirect_mode); + pstate->pipe.multirect_mode); pstate->pending = true; } @@ -1357,9 +1357,10 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p, const struct dpu_plane_state *pstate = to_dpu_plane_state(state); drm_printf(p, "\tstage=%d\n", pstate->stage); - drm_printf(p, "\tsspp=%s\n", pstate->hw_sspp->cap->name); - drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->multirect_mode)); - drm_printf(p, "\tmultirect_index=%s\n", dpu_get_multirect_index(pstate->multirect_index)); + drm_printf(p, "\tsspp=%s\n", pstate->pipe.sspp->cap->name); + drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->pipe.multirect_mode)); + drm_printf(p, "\tmultirect_index=%s\n", + dpu_get_multirect_index(pstate->pipe.multirect_index)); } static void dpu_plane_reset(struct drm_plane *plane) @@ -1392,7 +1393,7 @@ static void dpu_plane_reset(struct drm_plane *plane) * Set the SSPP here until we have proper virtualized DPU planes. * This is the place where the state is allocated, so fill it fully. */ - pstate->hw_sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); __drm_atomic_helper_plane_reset(plane, &pstate->base); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 25e261cabadc..228db401e905 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -18,7 +18,7 @@ * struct dpu_plane_state: Define dpu extension of drm plane state object * @base: base drm plane state object * @aspace: pointer to address space for input/output buffers - * @hw_sspp: pointer to corresponding SSPP instance + * @pipe: software pipe description * @stage: assigned by crtc blender * @needs_qos_remap: qos remap settings need to be updated * @multirect_index: index of the rectangle of SSPP @@ -32,11 +32,9 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; - struct dpu_hw_sspp *hw_sspp; + struct dpu_sw_pipe pipe; enum dpu_stage stage; bool needs_qos_remap; - uint32_t multirect_index; - uint32_t multirect_mode; bool pending; u64 plane_fetch_bw; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 76169f406505..d7059972499f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -633,9 +633,9 @@ TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl, TRACE_EVENT(dpu_crtc_setup_mixer, TP_PROTO(uint32_t crtc_id, uint32_t plane_id, struct drm_plane_state *state, struct dpu_plane_state *pstate, - uint32_t stage_idx, enum dpu_sspp sspp, uint32_t pixel_format, + uint32_t stage_idx, uint32_t pixel_format, uint64_t modifier), - TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp, + TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, pixel_format, modifier), TP_STRUCT__entry( __field( uint32_t, crtc_id ) @@ -659,9 +659,9 @@ TRACE_EVENT(dpu_crtc_setup_mixer, __entry->dst_rect = drm_plane_state_dest(state); __entry->stage_idx = stage_idx; __entry->stage = pstate->stage; - __entry->sspp = sspp; - __entry->multirect_idx = pstate->multirect_index; - __entry->multirect_mode = pstate->multirect_mode; + __entry->sspp = pstate->pipe.sspp->idx; + __entry->multirect_idx = pstate->pipe.multirect_index; + __entry->multirect_mode = pstate->pipe.multirect_mode; __entry->pixel_format = pixel_format; __entry->modifier = modifier; ), From 74fd7fda0f1ff6157ac2ff922e71b86ffab8ce23 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:29 +0300 Subject: [PATCH 13/42] drm/msm/dpu: use dpu_sw_pipe for dpu_hw_sspp callbacks Where feasible, use dpu_sw_pipe rather than a combo of dpu_hw_sspp and multirect_index/_mode arguments. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527333/ Link: https://lore.kernel.org/r/20230316161653.4106395-9-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 59 +++++++++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 46 +++++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 73 ++++++++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 9 ++- 4 files changed, 84 insertions(+), 103 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 3e65bfd65b62..a1492a7e43ce 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -168,17 +168,16 @@ static int _sspp_subblk_offset(struct dpu_hw_sspp *ctx, return rc; } -static void dpu_hw_sspp_setup_multirect(struct dpu_hw_sspp *ctx, - enum dpu_sspp_multirect_index index, - enum dpu_sspp_multirect_mode mode) +static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) { + struct dpu_hw_sspp *ctx = pipe->sspp; u32 mode_mask; u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; - if (index == DPU_SSPP_RECT_SOLO) { + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { /** * if rect index is RECT_SOLO, we cannot expect a * virtual plane sharing the same SSPP id. So we go @@ -187,8 +186,8 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_hw_sspp *ctx, mode_mask = 0; } else { mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx); - mode_mask |= index; - if (mode == DPU_SSPP_MULTIRECT_TIME_MX) + mode_mask |= pipe->multirect_index; + if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX) mode_mask |= BIT(2); else mode_mask &= ~BIT(2); @@ -239,10 +238,10 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, /* * Setup source pixel format, flip, */ -static void dpu_hw_sspp_setup_format(struct dpu_hw_sspp *ctx, - const struct dpu_format *fmt, u32 flags, - enum dpu_sspp_multirect_index rect_mode) +static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, + const struct dpu_format *fmt, u32 flags) { + struct dpu_hw_sspp *ctx = pipe->sspp; struct dpu_hw_blk_reg_map *c; u32 chroma_samp, unpack, src_format; u32 opmode = 0; @@ -253,7 +252,8 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_sspp *ctx, if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt) return; - if (rect_mode == DPU_SSPP_RECT_SOLO || rect_mode == DPU_SSPP_RECT_0) { + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || + pipe->multirect_index == DPU_SSPP_RECT_0) { op_mode_off = SSPP_SRC_OP_MODE; unpack_pat_off = SSPP_SRC_UNPACK_PATTERN; format_off = SSPP_SRC_FORMAT; @@ -447,10 +447,10 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx) /* * dpu_hw_sspp_setup_rects() */ -static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx, - struct dpu_hw_sspp_cfg *cfg, - enum dpu_sspp_multirect_index rect_index) +static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe, + struct dpu_hw_sspp_cfg *cfg) { + struct dpu_hw_sspp *ctx = pipe->sspp; struct dpu_hw_blk_reg_map *c; u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1; u32 src_size_off, src_xy_off, out_size_off, out_xy_off; @@ -461,7 +461,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx, c = &ctx->hw; - if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) { + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || + pipe->multirect_index == DPU_SSPP_RECT_0) { src_size_off = SSPP_SRC_SIZE; src_xy_off = SSPP_SRC_XY; out_size_off = SSPP_OUT_SIZE; @@ -482,7 +483,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx, dst_size = (drm_rect_height(&cfg->dst_rect) << 16) | drm_rect_width(&cfg->dst_rect); - if (rect_index == DPU_SSPP_RECT_SOLO) { + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { ystride0 = (cfg->layout.plane_pitch[0]) | (cfg->layout.plane_pitch[1] << 16); ystride1 = (cfg->layout.plane_pitch[2]) | @@ -491,7 +492,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx, ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx); ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); - if (rect_index == DPU_SSPP_RECT_0) { + if (pipe->multirect_index == DPU_SSPP_RECT_0) { ystride0 = (ystride0 & 0xFFFF0000) | (cfg->layout.plane_pitch[0] & 0x0000FFFF); ystride1 = (ystride1 & 0xFFFF0000)| @@ -516,21 +517,21 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_sspp *ctx, DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1); } -static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_sspp *ctx, - struct dpu_hw_sspp_cfg *cfg, - enum dpu_sspp_multirect_index rect_mode) +static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, + struct dpu_hw_sspp_cfg *cfg) { + struct dpu_hw_sspp *ctx = pipe->sspp; int i; u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; - if (rect_mode == DPU_SSPP_RECT_SOLO) { + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++) DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, cfg->layout.plane_addr[i]); - } else if (rect_mode == DPU_SSPP_RECT_0) { + } else if (pipe->multirect_index == DPU_SSPP_RECT_0) { DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, cfg->layout.plane_addr[0]); DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, @@ -560,15 +561,16 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, dpu_hw_csc_setup(&ctx->hw, idx, data, csc10); } -static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_sspp *ctx, u32 color, enum - dpu_sspp_multirect_index rect_index) +static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color) { + struct dpu_hw_sspp *ctx = pipe->sspp; u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; - if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || + pipe->multirect_index == DPU_SSPP_RECT_0) DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); else DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx, @@ -630,10 +632,10 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL + idx, qos_ctrl); } -static void dpu_hw_sspp_setup_cdp(struct dpu_hw_sspp *ctx, - struct dpu_hw_cdp_cfg *cfg, - enum dpu_sspp_multirect_index index) +static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, + struct dpu_hw_cdp_cfg *cfg) { + struct dpu_hw_sspp *ctx = pipe->sspp; u32 idx; u32 cdp_cntl = 0; u32 cdp_cntl_offset = 0; @@ -644,7 +646,8 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_hw_sspp *ctx, if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; - if (index == DPU_SSPP_RECT_SOLO || index == DPU_SSPP_RECT_0) + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || + pipe->multirect_index == DPU_SSPP_RECT_0) cdp_cntl_offset = SSPP_CDP_CNTL; else cdp_cntl_offset = SSPP_CDP_CNTL_REC1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 13d9e04a5153..5903413256ea 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -217,24 +217,20 @@ struct dpu_sw_pipe { struct dpu_hw_sspp_ops { /** * setup_format - setup pixel format cropping rectangle, flip - * @ctx: Pointer to pipe context + * @pipe: Pointer to software pipe context * @cfg: Pointer to pipe config structure * @flags: Extra flags for format config - * @index: rectangle index in multirect */ - void (*setup_format)(struct dpu_hw_sspp *ctx, - const struct dpu_format *fmt, u32 flags, - enum dpu_sspp_multirect_index index); + void (*setup_format)(struct dpu_sw_pipe *pipe, + const struct dpu_format *fmt, u32 flags); /** * setup_rects - setup pipe ROI rectangles - * @ctx: Pointer to pipe context + * @pipe: Pointer to software pipe context * @cfg: Pointer to pipe config structure - * @index: rectangle index in multirect */ - void (*setup_rects)(struct dpu_hw_sspp *ctx, - struct dpu_hw_sspp_cfg *cfg, - enum dpu_sspp_multirect_index index); + void (*setup_rects)(struct dpu_sw_pipe *pipe, + struct dpu_hw_sspp_cfg *cfg); /** * setup_pe - setup pipe pixel extension @@ -246,13 +242,11 @@ struct dpu_hw_sspp_ops { /** * setup_sourceaddress - setup pipe source addresses - * @ctx: Pointer to pipe context + * @pipe: Pointer to software pipe context * @cfg: Pointer to pipe config structure - * @index: rectangle index in multirect */ - void (*setup_sourceaddress)(struct dpu_hw_sspp *ctx, - struct dpu_hw_sspp_cfg *cfg, - enum dpu_sspp_multirect_index index); + void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx, + struct dpu_hw_sspp_cfg *cfg); /** * setup_csc - setup color space coversion @@ -263,24 +257,18 @@ struct dpu_hw_sspp_ops { /** * setup_solidfill - enable/disable colorfill - * @ctx: Pointer to pipe context + * @pipe: Pointer to software pipe context * @const_color: Fill color value * @flags: Pipe flags - * @index: rectangle index in multirect */ - void (*setup_solidfill)(struct dpu_hw_sspp *ctx, u32 color, - enum dpu_sspp_multirect_index index); + void (*setup_solidfill)(struct dpu_sw_pipe *pipe, u32 color); /** * setup_multirect - setup multirect configuration - * @ctx: Pointer to pipe context - * @index: rectangle index in multirect - * @mode: parallel fetch / time multiplex multirect mode + * @pipe: Pointer to software pipe context */ - void (*setup_multirect)(struct dpu_hw_sspp *ctx, - enum dpu_sspp_multirect_index index, - enum dpu_sspp_multirect_mode mode); + void (*setup_multirect)(struct dpu_sw_pipe *pipe); /** * setup_sharpening - setup sharpening @@ -345,13 +333,11 @@ struct dpu_hw_sspp_ops { /** * setup_cdp - setup client driven prefetch - * @ctx: Pointer to pipe context + * @pipe: Pointer to software pipe context * @cfg: Pointer to cdp configuration - * @index: rectangle index in multirect */ - void (*setup_cdp)(struct dpu_hw_sspp *ctx, - struct dpu_hw_cdp_cfg *cfg, - enum dpu_sspp_multirect_index index); + void (*setup_cdp)(struct dpu_sw_pipe *pipe, + struct dpu_hw_cdp_cfg *cfg); }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 8109ad8f9d0a..e48e54064e33 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -484,23 +484,21 @@ static void _dpu_plane_set_scanout(struct drm_plane *plane, if (ret) DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); else if (pstate->pipe.sspp->ops.setup_sourceaddress) { - trace_dpu_plane_set_scanout(pstate->pipe.sspp->idx, - &pipe_cfg->layout, - pstate->pipe.multirect_index); - pstate->pipe.sspp->ops.setup_sourceaddress(pstate->pipe.sspp, pipe_cfg, - pstate->pipe.multirect_index); + trace_dpu_plane_set_scanout(&pstate->pipe, + &pipe_cfg->layout); + pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg); } } -static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, - struct dpu_plane_state *pstate, +static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, struct dpu_hw_scaler3_cfg *scale_cfg, const struct dpu_format *fmt, - uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) + uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v, + unsigned int rotation) { uint32_t i; - bool inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90; + bool inline_rotation = rotation & DRM_MODE_ROTATE_90; /* * For inline rotation cases, scaler config is post-rotation, @@ -539,7 +537,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, scale_cfg->src_height[i] /= chroma_subsmpl_v; } - if (pstate->pipe.sspp->cap->features & + if (pipe_hw->cap->features & BIT(DPU_SSPP_SCALER_QSEED4)) { scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; @@ -636,11 +634,12 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons return csc_ptr; } -static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, - struct dpu_plane_state *pstate, +static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, const struct dpu_format *fmt, bool color_fill, - struct dpu_hw_sspp_cfg *pipe_cfg) + struct dpu_hw_sspp_cfg *pipe_cfg, + unsigned int rotation) { + struct dpu_hw_sspp *pipe_hw = pipe->sspp; const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); struct dpu_hw_scaler3_cfg scaler3_cfg; struct dpu_hw_pixel_ext pixel_ext; @@ -654,20 +653,21 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, /* don't chroma subsample if decimating */ /* update scaler. calculate default config for QSEED3 */ - _dpu_plane_setup_scaler3(pdpu, pstate, + _dpu_plane_setup_scaler3(pipe_hw, src_width, src_height, dst_width, dst_height, &scaler3_cfg, fmt, - info->hsub, info->vsub); + info->hsub, info->vsub, + rotation); /* configure pixel extension based on scalar config */ _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, src_width, src_height, info->hsub, info->vsub); - if (pstate->pipe.sspp->ops.setup_pe) - pstate->pipe.sspp->ops.setup_pe(pstate->pipe.sspp, + if (pipe_hw->ops.setup_pe) + pipe_hw->ops.setup_pe(pipe_hw, &pixel_ext); /** @@ -675,9 +675,9 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, * bypassed. Still we need to update alpha and bitwidth * ONLY for RECT0 */ - if (pstate->pipe.sspp->ops.setup_scaler && - pstate->pipe.multirect_index != DPU_SSPP_RECT_1) - pstate->pipe.sspp->ops.setup_scaler(pstate->pipe.sspp, + if (pipe_hw->ops.setup_scaler && + pipe->multirect_index != DPU_SSPP_RECT_1) + pipe_hw->ops.setup_scaler(pipe_hw, pipe_cfg, &scaler3_cfg); } @@ -707,9 +707,8 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, /* update sspp */ if (fmt && pstate->pipe.sspp->ops.setup_solidfill) { - pstate->pipe.sspp->ops.setup_solidfill(pstate->pipe.sspp, - (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), - pstate->pipe.multirect_index); + pstate->pipe.sspp->ops.setup_solidfill(&pstate->pipe, + (color & 0xFFFFFF) | ((alpha & 0xFF) << 24)); /* override scaler/decimation if solid fill */ pipe_cfg.dst_rect = pstate->base.dst; @@ -722,16 +721,14 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, drm_rect_height(&pipe_cfg.dst_rect); if (pstate->pipe.sspp->ops.setup_format) - pstate->pipe.sspp->ops.setup_format(pstate->pipe.sspp, - fmt, DPU_SSPP_SOLID_FILL, - pstate->pipe.multirect_index); + pstate->pipe.sspp->ops.setup_format(&pstate->pipe, + fmt, DPU_SSPP_SOLID_FILL); if (pstate->pipe.sspp->ops.setup_rects) - pstate->pipe.sspp->ops.setup_rects(pstate->pipe.sspp, - &pipe_cfg, - pstate->pipe.multirect_index); + pstate->pipe.sspp->ops.setup_rects(&pstate->pipe, + &pipe_cfg); - _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg); + _dpu_plane_setup_scaler(&pstate->pipe, fmt, true, &pipe_cfg, pstate->rotation); } return 0; @@ -1170,18 +1167,15 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) } if (pipe->sspp->ops.setup_rects) { - pipe->sspp->ops.setup_rects(pipe->sspp, - &pipe_cfg, - pipe->multirect_index); + pipe->sspp->ops.setup_rects(pipe, + &pipe_cfg); } - _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); + _dpu_plane_setup_scaler(pipe, fmt, false, &pipe_cfg, pstate->rotation); if (pipe->sspp->ops.setup_multirect) pipe->sspp->ops.setup_multirect( - pipe->sspp, - pipe->multirect_index, - pipe->multirect_mode); + pipe); if (pipe->sspp->ops.setup_format) { unsigned int rotation = pstate->rotation; @@ -1198,8 +1192,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) src_flags |= DPU_SSPP_ROT_90; /* update format */ - pipe->sspp->ops.setup_format(pipe->sspp, fmt, src_flags, - pipe->multirect_index); + pipe->sspp->ops.setup_format(pipe, fmt, src_flags); if (pipe->sspp->ops.setup_cdp) { struct dpu_hw_cdp_cfg cdp_cfg; @@ -1215,7 +1208,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) DPU_FORMAT_IS_TILE(fmt); cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; - pipe->sspp->ops.setup_cdp(pipe->sspp, &cdp_cfg, pipe->multirect_index); + pipe->sspp->ops.setup_cdp(pipe, &cdp_cfg); } } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index d7059972499f..0ad148cc2fb8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -762,18 +762,17 @@ TRACE_EVENT(dpu_crtc_disable_frame_pending, ); TRACE_EVENT(dpu_plane_set_scanout, - TP_PROTO(enum dpu_sspp index, struct dpu_hw_fmt_layout *layout, - enum dpu_sspp_multirect_index multirect_index), - TP_ARGS(index, layout, multirect_index), + TP_PROTO(struct dpu_sw_pipe *pipe, struct dpu_hw_fmt_layout *layout), + TP_ARGS(pipe, layout), TP_STRUCT__entry( __field( enum dpu_sspp, index ) __field_struct( struct dpu_hw_fmt_layout, layout ) __field( enum dpu_sspp_multirect_index, multirect_index) ), TP_fast_assign( - __entry->index = index; + __entry->index = pipe->sspp->idx; __entry->layout = *layout; - __entry->multirect_index = multirect_index; + __entry->multirect_index = pipe->multirect_index; ), TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} " "multirect_index:%d", __entry->index, __entry->layout.width, From 6edb12d119e2551a52586e3ff45f4176aeac89d7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:30 +0300 Subject: [PATCH 14/42] drm/msm/dpu: pass dpu_format to _dpu_hw_sspp_setup_scaler3() There is no need to pass full dpu_hw_sspp_cfg instance to _dpu_hw_sspp_setup_scaler3, pass just struct dpu_format pointer. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527328/ Link: https://lore.kernel.org/r/20230316161653.4106395-10-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 9 ++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 9 ++++----- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++-- 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index a1492a7e43ce..3030cd3b253a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -419,19 +419,18 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, } static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, - struct dpu_hw_sspp_cfg *sspp, - void *scaler_cfg) + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct dpu_format *format) { u32 idx; - struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg; - if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !sspp + if (_sspp_subblk_offset(ctx, DPU_SSPP_SCALER_QSEED3, &idx) || !scaler3_cfg) return; dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx, ctx->cap->sblk->scaler_blk.version, - sspp->layout.format); + format); } static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 5903413256ea..136b8713943f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -317,13 +317,12 @@ struct dpu_hw_sspp_ops { /** * setup_scaler - setup scaler - * @ctx: Pointer to pipe context - * @pipe_cfg: Pointer to pipe configuration - * @scaler_cfg: Pointer to scaler configuration + * @scaler3_cfg: Pointer to scaler configuration + * @format: pixel format parameters */ void (*setup_scaler)(struct dpu_hw_sspp *ctx, - struct dpu_hw_sspp_cfg *pipe_cfg, - void *scaler_cfg); + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct dpu_format *format); /** * get_scaler_ver - get scaler h/w version diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index e48e54064e33..f9ba6c411be2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -678,8 +678,8 @@ static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, if (pipe_hw->ops.setup_scaler && pipe->multirect_index != DPU_SSPP_RECT_1) pipe_hw->ops.setup_scaler(pipe_hw, - pipe_cfg, - &scaler3_cfg); + &scaler3_cfg, + fmt); } /** From 0cb17768bc6bc9599c48da34626225a6340dbe62 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:31 +0300 Subject: [PATCH 15/42] drm/msm/dpu: clean up SRC addresses when setting up SSPP for solid fill Set SSPP_SRCn_ADDR registers to 0 while setting up solid fill, as we can not be sure that the previous address is still valid. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527324/ Link: https://lore.kernel.org/r/20230316161653.4106395-11-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 3030cd3b253a..0a43c5682b2b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -563,11 +563,16 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color) { struct dpu_hw_sspp *ctx = pipe->sspp; + struct dpu_hw_sspp_cfg cfg; u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; + /* cleanup source addresses */ + memset(&cfg, 0, sizeof(cfg)); + ctx->ops.setup_sourceaddress(pipe, &cfg); + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || pipe->multirect_index == DPU_SSPP_RECT_0) DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); From 62791e695e0370ed4e3200bbf05182443dab09f6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:32 +0300 Subject: [PATCH 16/42] drm/msm/dpu: move stride programming to dpu_hw_sspp_setup_sourceaddress Move stride programming to dpu_hw_sspp_setup_sourceaddress(), so that dpu_hw_sspp_setup_rects() programs only source and destination rectangles. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527330/ Link: https://lore.kernel.org/r/20230316161653.4106395-12-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 57 +++++++++++---------- 1 file changed, 29 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 0a43c5682b2b..ab95f2817378 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -451,7 +451,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe, { struct dpu_hw_sspp *ctx = pipe->sspp; struct dpu_hw_blk_reg_map *c; - u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1; + u32 src_size, src_xy, dst_size, dst_xy; u32 src_size_off, src_xy_off, out_size_off, out_xy_off; u32 idx; @@ -482,44 +482,18 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe, dst_size = (drm_rect_height(&cfg->dst_rect) << 16) | drm_rect_width(&cfg->dst_rect); - if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { - ystride0 = (cfg->layout.plane_pitch[0]) | - (cfg->layout.plane_pitch[1] << 16); - ystride1 = (cfg->layout.plane_pitch[2]) | - (cfg->layout.plane_pitch[3] << 16); - } else { - ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx); - ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); - - if (pipe->multirect_index == DPU_SSPP_RECT_0) { - ystride0 = (ystride0 & 0xFFFF0000) | - (cfg->layout.plane_pitch[0] & 0x0000FFFF); - ystride1 = (ystride1 & 0xFFFF0000)| - (cfg->layout.plane_pitch[2] & 0x0000FFFF); - } else { - ystride0 = (ystride0 & 0x0000FFFF) | - ((cfg->layout.plane_pitch[0] << 16) & - 0xFFFF0000); - ystride1 = (ystride1 & 0x0000FFFF) | - ((cfg->layout.plane_pitch[2] << 16) & - 0xFFFF0000); - } - } - /* rectangle register programming */ DPU_REG_WRITE(c, src_size_off + idx, src_size); DPU_REG_WRITE(c, src_xy_off + idx, src_xy); DPU_REG_WRITE(c, out_size_off + idx, dst_size); DPU_REG_WRITE(c, out_xy_off + idx, dst_xy); - - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0); - DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1); } static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, struct dpu_hw_sspp_cfg *cfg) { struct dpu_hw_sspp *ctx = pipe->sspp; + u32 ystride0, ystride1; int i; u32 idx; @@ -541,6 +515,33 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx, cfg->layout.plane_addr[2]); } + + if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { + ystride0 = (cfg->layout.plane_pitch[0]) | + (cfg->layout.plane_pitch[1] << 16); + ystride1 = (cfg->layout.plane_pitch[2]) | + (cfg->layout.plane_pitch[3] << 16); + } else { + ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx); + ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx); + + if (pipe->multirect_index == DPU_SSPP_RECT_0) { + ystride0 = (ystride0 & 0xFFFF0000) | + (cfg->layout.plane_pitch[0] & 0x0000FFFF); + ystride1 = (ystride1 & 0xFFFF0000)| + (cfg->layout.plane_pitch[2] & 0x0000FFFF); + } else { + ystride0 = (ystride0 & 0x0000FFFF) | + ((cfg->layout.plane_pitch[0] << 16) & + 0xFFFF0000); + ystride1 = (ystride1 & 0x0000FFFF) | + ((cfg->layout.plane_pitch[2] << 16) & + 0xFFFF0000); + } + } + + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx, ystride0); + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx, ystride1); } static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, From dfdc94e4934bc6051545c9283c5c94153ac359d8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:33 +0300 Subject: [PATCH 17/42] drm/msm/dpu: remove dpu_hw_fmt_layout from struct dpu_hw_sspp_cfg Remove dpu_hw_fmt_layout instance from struct dpu_hw_sspp_cfg, leaving only src_rect and dst_rect. This way all the pipes used by the plane will have a common layout instance (as the framebuffer is shared between them), while still keeping a separate src/dst rectangle configuration for each pipe. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527329/ Link: https://lore.kernel.org/r/20230316161653.4106395-13-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 32 ++++++++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 +++---- 3 files changed, 23 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index ab95f2817378..e87c6377f315 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -490,7 +490,7 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe, } static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, - struct dpu_hw_sspp_cfg *cfg) + struct dpu_hw_fmt_layout *layout) { struct dpu_hw_sspp *ctx = pipe->sspp; u32 ystride0, ystride1; @@ -501,41 +501,41 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, return; if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++) + for (i = 0; i < ARRAY_SIZE(layout->plane_addr); i++) DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, - cfg->layout.plane_addr[i]); + layout->plane_addr[i]); } else if (pipe->multirect_index == DPU_SSPP_RECT_0) { DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, - cfg->layout.plane_addr[0]); + layout->plane_addr[0]); DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, - cfg->layout.plane_addr[2]); + layout->plane_addr[2]); } else { DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx, - cfg->layout.plane_addr[0]); + layout->plane_addr[0]); DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx, - cfg->layout.plane_addr[2]); + layout->plane_addr[2]); } if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) { - ystride0 = (cfg->layout.plane_pitch[0]) | - (cfg->layout.plane_pitch[1] << 16); - ystride1 = (cfg->layout.plane_pitch[2]) | - (cfg->layout.plane_pitch[3] << 16); + ystride0 = (layout->plane_pitch[0]) | + (layout->plane_pitch[1] << 16); + ystride1 = (layout->plane_pitch[2]) | + (layout->plane_pitch[3] << 16); } else { ystride0 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE0 + idx); ystride1 = DPU_REG_READ(&ctx->hw, SSPP_SRC_YSTRIDE1 + idx); if (pipe->multirect_index == DPU_SSPP_RECT_0) { ystride0 = (ystride0 & 0xFFFF0000) | - (cfg->layout.plane_pitch[0] & 0x0000FFFF); + (layout->plane_pitch[0] & 0x0000FFFF); ystride1 = (ystride1 & 0xFFFF0000)| - (cfg->layout.plane_pitch[2] & 0x0000FFFF); + (layout->plane_pitch[2] & 0x0000FFFF); } else { ystride0 = (ystride0 & 0x0000FFFF) | - ((cfg->layout.plane_pitch[0] << 16) & + ((layout->plane_pitch[0] << 16) & 0xFFFF0000); ystride1 = (ystride1 & 0x0000FFFF) | - ((cfg->layout.plane_pitch[2] << 16) & + ((layout->plane_pitch[2] << 16) & 0xFFFF0000); } } @@ -564,7 +564,7 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color) { struct dpu_hw_sspp *ctx = pipe->sspp; - struct dpu_hw_sspp_cfg cfg; + struct dpu_hw_fmt_layout cfg; u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 136b8713943f..100d8e06c90d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -154,13 +154,11 @@ struct dpu_hw_pixel_ext { /** * struct dpu_hw_sspp_cfg : SSPP configuration - * @layout: format layout information for programming buffer to hardware * @src_rect: src ROI, caller takes into account the different operations * such as decimation, flip etc to program this field * @dest_rect: destination ROI. */ struct dpu_hw_sspp_cfg { - struct dpu_hw_fmt_layout layout; struct drm_rect src_rect; struct drm_rect dst_rect; }; @@ -243,10 +241,10 @@ struct dpu_hw_sspp_ops { /** * setup_sourceaddress - setup pipe source addresses * @pipe: Pointer to software pipe context - * @cfg: Pointer to pipe config structure + * @layout: format layout information for programming buffer to hardware */ void (*setup_sourceaddress)(struct dpu_sw_pipe *ctx, - struct dpu_hw_sspp_cfg *cfg); + struct dpu_hw_fmt_layout *layout); /** * setup_csc - setup color space coversion diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index f9ba6c411be2..2d2e3bf334dc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -472,21 +472,21 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane) static void _dpu_plane_set_scanout(struct drm_plane *plane, struct dpu_plane_state *pstate, - struct dpu_hw_sspp_cfg *pipe_cfg, struct drm_framebuffer *fb) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); struct msm_gem_address_space *aspace = kms->base.aspace; + struct dpu_hw_fmt_layout layout; int ret; - ret = dpu_format_populate_layout(aspace, fb, &pipe_cfg->layout); + ret = dpu_format_populate_layout(aspace, fb, &layout); if (ret) DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); else if (pstate->pipe.sspp->ops.setup_sourceaddress) { trace_dpu_plane_set_scanout(&pstate->pipe, - &pipe_cfg->layout); - pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, pipe_cfg); + &layout); + pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout); } } @@ -1135,7 +1135,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) memset(&pipe_cfg, 0, sizeof(struct dpu_hw_sspp_cfg)); - _dpu_plane_set_scanout(plane, pstate, &pipe_cfg, fb); + _dpu_plane_set_scanout(plane, pstate, fb); pstate->pending = true; From 0d06fb9068fd61d3b8eaf54370abbb3a6a54fab2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:34 +0300 Subject: [PATCH 18/42] drm/msm/dpu: rename dpu_hw_sspp_cfg to dpu_sw_pipe_cfg As struct dpu_hw_sspp_cfg describes only the source and destination rectangles, it is a software pipe configuration now. Rename it accordingly. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527334/ Link: https://lore.kernel.org/r/20230316161653.4106395-14-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 16 ++++++++-------- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index e87c6377f315..6e5b62f3276f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -447,7 +447,7 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_sspp *ctx) * dpu_hw_sspp_setup_rects() */ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe, - struct dpu_hw_sspp_cfg *cfg) + struct dpu_sw_pipe_cfg *cfg) { struct dpu_hw_sspp *ctx = pipe->sspp; struct dpu_hw_blk_reg_map *c; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 100d8e06c90d..e73d6ac863ad 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -153,12 +153,12 @@ struct dpu_hw_pixel_ext { }; /** - * struct dpu_hw_sspp_cfg : SSPP configuration + * struct dpu_sw_pipe_cfg : software pipe configuration * @src_rect: src ROI, caller takes into account the different operations * such as decimation, flip etc to program this field * @dest_rect: destination ROI. */ -struct dpu_hw_sspp_cfg { +struct dpu_sw_pipe_cfg { struct drm_rect src_rect; struct drm_rect dst_rect; }; @@ -228,7 +228,7 @@ struct dpu_hw_sspp_ops { * @cfg: Pointer to pipe config structure */ void (*setup_rects)(struct dpu_sw_pipe *pipe, - struct dpu_hw_sspp_cfg *cfg); + struct dpu_sw_pipe_cfg *cfg); /** * setup_pe - setup pipe pixel extension diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 2d2e3bf334dc..25233c9ad020 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -137,7 +137,7 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) */ static void _dpu_plane_calc_bw(struct drm_plane *plane, struct drm_framebuffer *fb, - struct dpu_hw_sspp_cfg *pipe_cfg) + struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane_state *pstate; struct drm_display_mode *mode; @@ -192,7 +192,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, * Result: Updates calculated clock in the plane state. * Clock equation: dst_w * v_total * fps * (src_h / dst_h) */ -static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_hw_sspp_cfg *pipe_cfg) +static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane_state *pstate; struct drm_display_mode *mode; @@ -276,7 +276,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, * @pipe_cfg: Pointer to pipe configuration */ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, - struct drm_framebuffer *fb, struct dpu_hw_sspp_cfg *pipe_cfg) + struct drm_framebuffer *fb, struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); @@ -422,7 +422,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, * @pipe_cfg: Pointer to pipe configuration */ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, - struct drm_crtc *crtc, struct dpu_hw_sspp_cfg *pipe_cfg) + struct drm_crtc *crtc, struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); @@ -636,7 +636,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, cons static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, const struct dpu_format *fmt, bool color_fill, - struct dpu_hw_sspp_cfg *pipe_cfg, + struct dpu_sw_pipe_cfg *pipe_cfg, unsigned int rotation) { struct dpu_hw_sspp *pipe_hw = pipe->sspp; @@ -695,7 +695,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, const struct dpu_format *fmt; const struct drm_plane *plane = &pdpu->base; struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); - struct dpu_hw_sspp_cfg pipe_cfg; + struct dpu_sw_pipe_cfg pipe_cfg; DPU_DEBUG_PLANE(pdpu, "\n"); @@ -1131,9 +1131,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) bool is_rt_pipe; const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(fb)); - struct dpu_hw_sspp_cfg pipe_cfg; + struct dpu_sw_pipe_cfg pipe_cfg; - memset(&pipe_cfg, 0, sizeof(struct dpu_hw_sspp_cfg)); + memset(&pipe_cfg, 0, sizeof(struct dpu_sw_pipe_cfg)); _dpu_plane_set_scanout(plane, pstate, fb); From e35f68d18bad460a9af33213d97c90a8d91b49eb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:35 +0300 Subject: [PATCH 19/42] drm/msm/dpu: drop src_split and multirect check from dpu_crtc_atomic_check Neither source split nor multirect are properly supported at this moment. Both of these checks depend on normalized_zpos being equal for several planes (which is never the case for normalized zpos). Drop these checks to simplify dpu_crtc_atomic_check(). The actual support for either of these features is not removed from the backend code (sspp, ctl, etc). Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527332/ Link: https://lore.kernel.org/r/20230316161653.4106395-15-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 168 ++--------------------- 1 file changed, 12 insertions(+), 156 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 56da7598d08a..351b00cf0f5b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1133,13 +1133,6 @@ static void dpu_crtc_enable(struct drm_crtc *crtc, drm_crtc_vblank_on(crtc); } -struct plane_state { - struct dpu_plane_state *dpu_pstate; - const struct drm_plane_state *drm_pstate; - int stage; - u32 pipe_id; -}; - static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate) { struct drm_crtc *crtc = cstate->crtc; @@ -1161,31 +1154,22 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, crtc); struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); - struct plane_state *pstates; const struct drm_plane_state *pstate; struct drm_plane *plane; struct drm_display_mode *mode; - int cnt = 0, rc = 0, mixer_width = 0, i, z_pos; + int rc = 0; - struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2]; - int multirect_count = 0; - const struct drm_plane_state *pipe_staged[SSPP_MAX]; - int left_zpos_cnt = 0, right_zpos_cnt = 0; struct drm_rect crtc_rect = { 0 }; bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state); - pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL); - if (!pstates) - return -ENOMEM; - if (!crtc_state->enable || !crtc_state->active) { DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", crtc->base.id, crtc_state->enable, crtc_state->active); memset(&cstate->new_perf, 0, sizeof(cstate->new_perf)); - goto end; + return 0; } mode = &crtc_state->adjusted_mode; @@ -1195,13 +1179,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, if (crtc_state->active_changed) crtc_state->mode_changed = true; - memset(pipe_staged, 0, sizeof(pipe_staged)); - - if (cstate->num_mixers) { - mixer_width = mode->hdisplay / cstate->num_mixers; - + if (cstate->num_mixers) _dpu_crtc_setup_lm_bounds(crtc, crtc_state); - } crtc_rect.x2 = mode->hdisplay; crtc_rect.y2 = mode->vdisplay; @@ -1210,38 +1189,21 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate); struct drm_rect dst, clip = crtc_rect; + int z_pos; if (IS_ERR_OR_NULL(pstate)) { rc = PTR_ERR(pstate); DPU_ERROR("%s: failed to get plane%d state, %d\n", dpu_crtc->name, plane->base.id, rc); - goto end; + return rc; } - if (cnt >= DPU_STAGE_MAX * 4) - continue; if (!pstate->visible) continue; - pstates[cnt].dpu_pstate = dpu_pstate; - pstates[cnt].drm_pstate = pstate; - pstates[cnt].stage = pstate->normalized_zpos; - pstates[cnt].pipe_id = to_dpu_plane_state(pstate)->pipe.sspp->idx; - dpu_pstate->needs_dirtyfb = needs_dirtyfb; - if (pipe_staged[pstates[cnt].pipe_id]) { - multirect_plane[multirect_count].r0 = - pipe_staged[pstates[cnt].pipe_id]; - multirect_plane[multirect_count].r1 = pstate; - multirect_count++; - - pipe_staged[pstates[cnt].pipe_id] = NULL; - } else { - pipe_staged[pstates[cnt].pipe_id] = pstate; - } - - cnt++; + dpu_plane_clear_multirect(pstate); dst = drm_plane_state_dest(pstate); if (!drm_rect_intersect(&clip, &dst)) { @@ -1249,63 +1211,21 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, DPU_ERROR("display: " DRM_RECT_FMT " plane: " DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect), DRM_RECT_ARG(&dst)); - rc = -E2BIG; - goto end; + return -E2BIG; } - } - for (i = 1; i < SSPP_MAX; i++) { - if (pipe_staged[i]) - dpu_plane_clear_multirect(pipe_staged[i]); - } - - z_pos = -1; - for (i = 0; i < cnt; i++) { - /* reset counts at every new blend stage */ - if (pstates[i].stage != z_pos) { - left_zpos_cnt = 0; - right_zpos_cnt = 0; - z_pos = pstates[i].stage; - } + z_pos = pstate->normalized_zpos; /* verify z_pos setting before using it */ if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) { DPU_ERROR("> %d plane stages assigned\n", DPU_STAGE_MAX - DPU_STAGE_0); - rc = -EINVAL; - goto end; - } else if (pstates[i].drm_pstate->crtc_x < mixer_width) { - if (left_zpos_cnt == 2) { - DPU_ERROR("> 2 planes @ stage %d on left\n", - z_pos); - rc = -EINVAL; - goto end; - } - left_zpos_cnt++; - - } else { - if (right_zpos_cnt == 2) { - DPU_ERROR("> 2 planes @ stage %d on right\n", - z_pos); - rc = -EINVAL; - goto end; - } - right_zpos_cnt++; + return -EINVAL; } - pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0; + to_dpu_plane_state(pstate)->stage = z_pos + DPU_STAGE_0; DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos); - } - for (i = 0; i < multirect_count; i++) { - if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) { - DPU_ERROR( - "multirect validation failed for planes (%d - %d)\n", - multirect_plane[i].r0->plane->base.id, - multirect_plane[i].r1->plane->base.id); - rc = -EINVAL; - goto end; - } } atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref); @@ -1314,74 +1234,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, if (rc) { DPU_ERROR("crtc%d failed performance check %d\n", crtc->base.id, rc); - goto end; + return rc; } - /* validate source split: - * use pstates sorted by stage to check planes on same stage - * we assume that all pipes are in source split so its valid to compare - * without taking into account left/right mixer placement - */ - for (i = 1; i < cnt; i++) { - struct plane_state *prv_pstate, *cur_pstate; - struct drm_rect left_rect, right_rect; - int32_t left_pid, right_pid; - int32_t stage; - - prv_pstate = &pstates[i - 1]; - cur_pstate = &pstates[i]; - if (prv_pstate->stage != cur_pstate->stage) - continue; - - stage = cur_pstate->stage; - - left_pid = prv_pstate->dpu_pstate->base.plane->base.id; - left_rect = drm_plane_state_dest(prv_pstate->drm_pstate); - - right_pid = cur_pstate->dpu_pstate->base.plane->base.id; - right_rect = drm_plane_state_dest(cur_pstate->drm_pstate); - - if (right_rect.x1 < left_rect.x1) { - swap(left_pid, right_pid); - swap(left_rect, right_rect); - } - - /** - * - planes are enumerated in pipe-priority order such that - * planes with lower drm_id must be left-most in a shared - * blend-stage when using source split. - * - planes in source split must be contiguous in width - * - planes in source split must have same dest yoff and height - */ - if (right_pid < left_pid) { - DPU_ERROR( - "invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n", - stage, left_pid, right_pid); - rc = -EINVAL; - goto end; - } else if (right_rect.x1 != drm_rect_width(&left_rect)) { - DPU_ERROR("non-contiguous coordinates for src split. " - "stage: %d left: " DRM_RECT_FMT " right: " - DRM_RECT_FMT "\n", stage, - DRM_RECT_ARG(&left_rect), - DRM_RECT_ARG(&right_rect)); - rc = -EINVAL; - goto end; - } else if (left_rect.y1 != right_rect.y1 || - drm_rect_height(&left_rect) != drm_rect_height(&right_rect)) { - DPU_ERROR("source split at stage: %d. invalid " - "yoff/height: left: " DRM_RECT_FMT " right: " - DRM_RECT_FMT "\n", stage, - DRM_RECT_ARG(&left_rect), - DRM_RECT_ARG(&right_rect)); - rc = -EINVAL; - goto end; - } - } - -end: - kfree(pstates); - return rc; + return 0; } int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) From a1d38f1152c570b882cdf4f96b75113d7c703ab1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:36 +0300 Subject: [PATCH 20/42] drm/msm/dpu: don't use unsupported blend stages The dpu_crtc_atomic_check() compares blending stage with DPU_STAGE_MAX (maximum amount of blending stages supported by the driver), however we should compare it against .max_mixer_blendstages, the maximum blend stage supported by the mixer. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527338/ Link: https://lore.kernel.org/r/20230316161653.4106395-16-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 351b00cf0f5b..94e8bdaeb530 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1154,6 +1154,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, crtc); struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); + struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); const struct drm_plane_state *pstate; struct drm_plane *plane; @@ -1189,7 +1190,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate); struct drm_rect dst, clip = crtc_rect; - int z_pos; + int stage; if (IS_ERR_OR_NULL(pstate)) { rc = PTR_ERR(pstate); @@ -1214,17 +1215,16 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, return -E2BIG; } - z_pos = pstate->normalized_zpos; - - /* verify z_pos setting before using it */ - if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) { + /* verify stage setting before using it */ + stage = DPU_STAGE_0 + pstate->normalized_zpos; + if (stage >= dpu_kms->catalog->caps->max_mixer_blendstages) { DPU_ERROR("> %d plane stages assigned\n", - DPU_STAGE_MAX - DPU_STAGE_0); + dpu_kms->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); return -EINVAL; } - to_dpu_plane_state(pstate)->stage = z_pos + DPU_STAGE_0; - DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos); + to_dpu_plane_state(pstate)->stage = stage; + DRM_DEBUG_ATOMIC("%s: stage %d\n", dpu_crtc->name, stage); } From bbc2c7bd7f19d6ebbf0c0710cd3b1efc667e340c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:37 +0300 Subject: [PATCH 21/42] drm/msm/dpu: move the rest of plane checks to dpu_plane_atomic_check() Move plane state updates from dpu_crtc_atomic_check() to the function where they belong: to dpu_plane_atomic_check(). Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527335/ Link: https://lore.kernel.org/r/20230316161653.4106395-17-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 18 +----------------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 ++++++++++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 6 ------ 3 files changed, 11 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 94e8bdaeb530..094fc113704b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1154,7 +1154,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, crtc); struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); - struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); const struct drm_plane_state *pstate; struct drm_plane *plane; @@ -1186,11 +1185,10 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, crtc_rect.x2 = mode->hdisplay; crtc_rect.y2 = mode->vdisplay; - /* get plane state for all drm planes associated with crtc state */ + /* FIXME: move this to dpu_plane_atomic_check? */ drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate); struct drm_rect dst, clip = crtc_rect; - int stage; if (IS_ERR_OR_NULL(pstate)) { rc = PTR_ERR(pstate); @@ -1204,8 +1202,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, dpu_pstate->needs_dirtyfb = needs_dirtyfb; - dpu_plane_clear_multirect(pstate); - dst = drm_plane_state_dest(pstate); if (!drm_rect_intersect(&clip, &dst)) { DPU_ERROR("invalid vertical/horizontal destination\n"); @@ -1214,18 +1210,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, DRM_RECT_ARG(&dst)); return -E2BIG; } - - /* verify stage setting before using it */ - stage = DPU_STAGE_0 + pstate->normalized_zpos; - if (stage >= dpu_kms->catalog->caps->max_mixer_blendstages) { - DPU_ERROR("> %d plane stages assigned\n", - dpu_kms->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); - return -EINVAL; - } - - to_dpu_plane_state(pstate)->stage = stage; - DRM_DEBUG_ATOMIC("%s: stage %d\n", dpu_crtc->name, stage); - } atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 25233c9ad020..94c0a62ec2d5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -734,14 +734,6 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, return 0; } -void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state) -{ - struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state); - - pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; - pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; -} - int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) { struct dpu_plane_state *pstate[R_MAX]; @@ -995,6 +987,16 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, if (!new_plane_state->visible) return 0; + pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; + pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; + if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { + DPU_ERROR("> %d plane stages assigned\n", + pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); + return -EINVAL; + } + src.x1 = new_plane_state->src_x >> 16; src.y1 = new_plane_state->src_y >> 16; src.x2 = src.x1 + (new_plane_state->src_w >> 16); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 228db401e905..a08b0539513b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -88,12 +88,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, */ int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane); -/** - * dpu_plane_clear_multirect - clear multirect bits for the given pipe - * @drm_state: Pointer to DRM plane state - */ -void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state); - /** * dpu_plane_color_fill - enables color fill on plane * @plane: Pointer to DRM plane object From f2bf133f7fcccc5d0a570deddca39f8a7ed35e27 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:38 +0300 Subject: [PATCH 22/42] drm/msm/dpu: drop redundant plane dst check from dpu_crtc_atomic_check() The helper drm_atomic_helper_check_plane_state() already checks whether the scaled and clipped plane falls into the CRTC visible region (and clears plane_state->visible if it doesn't). Drop the redundant check from dpu_crtc_atomic_check(). Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527343/ Link: https://lore.kernel.org/r/20230316161653.4106395-18-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 094fc113704b..dba5e4fbdb57 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1157,11 +1157,9 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, const struct drm_plane_state *pstate; struct drm_plane *plane; - struct drm_display_mode *mode; int rc = 0; - struct drm_rect crtc_rect = { 0 }; bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state); if (!crtc_state->enable || !crtc_state->active) { @@ -1172,7 +1170,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, return 0; } - mode = &crtc_state->adjusted_mode; DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name); /* force a full mode set if active state changed */ @@ -1182,13 +1179,9 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, if (cstate->num_mixers) _dpu_crtc_setup_lm_bounds(crtc, crtc_state); - crtc_rect.x2 = mode->hdisplay; - crtc_rect.y2 = mode->vdisplay; - /* FIXME: move this to dpu_plane_atomic_check? */ drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate); - struct drm_rect dst, clip = crtc_rect; if (IS_ERR_OR_NULL(pstate)) { rc = PTR_ERR(pstate); @@ -1201,15 +1194,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, continue; dpu_pstate->needs_dirtyfb = needs_dirtyfb; - - dst = drm_plane_state_dest(pstate); - if (!drm_rect_intersect(&clip, &dst)) { - DPU_ERROR("invalid vertical/horizontal destination\n"); - DPU_ERROR("display: " DRM_RECT_FMT " plane: " - DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect), - DRM_RECT_ARG(&dst)); - return -E2BIG; - } } atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref); From 7b5c207a4f1db1fdb09cb53e5f561c6c7121fa7e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:39 +0300 Subject: [PATCH 23/42] drm/msm/dpu: rewrite plane's QoS-related functions to take dpu_sw_pipe and dpu_format Rewrite dpu_plane's QoS related functions to take struct dpu_sw_pipe and struct dpu_format as arguments rather than fetching them from the pstate or drm_framebuffer. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527339/ Link: https://lore.kernel.org/r/20230316161653.4106395-19-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 98 +++++++++++------------ 1 file changed, 47 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 94c0a62ec2d5..0660ceea8eb8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -129,19 +129,18 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) /** * _dpu_plane_calc_bw - calculate bandwidth required for a plane * @plane: Pointer to drm plane. - * @fb: Pointer to framebuffer associated with the given plane + * @fmt: Pointer to source buffer format * @pipe_cfg: Pointer to pipe configuration * Result: Updates calculated bandwidth in the plane state. * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) * Prefill BW Equation: line src bytes * line_time */ static void _dpu_plane_calc_bw(struct drm_plane *plane, - struct drm_framebuffer *fb, + const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane_state *pstate; struct drm_display_mode *mode; - const struct dpu_format *fmt = NULL; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); int src_width, src_height, dst_height, fps; u64 plane_prefill_bw; @@ -153,8 +152,6 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, pstate = to_dpu_plane_state(plane->state); mode = &plane->state->crtc->mode; - fmt = dpu_get_dpu_format_ext(fb->format->format, fb->modifier); - src_width = drm_rect_width(&pipe_cfg->src_rect); src_height = drm_rect_height(&pipe_cfg->src_rect); dst_height = drm_rect_height(&pipe_cfg->dst_rect); @@ -218,25 +215,25 @@ static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_sw_pipe_cfg /** * _dpu_plane_calc_fill_level - calculate fill level of the given source format * @plane: Pointer to drm plane + * @pipe: Pointer to software pipe * @fmt: Pointer to source buffer format * @src_width: width of source buffer * Return: fill level corresponding to the source buffer/format or 0 if error */ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, + struct dpu_sw_pipe *pipe, const struct dpu_format *fmt, u32 src_width) { struct dpu_plane *pdpu; - struct dpu_plane_state *pstate; u32 fixed_buff_size; u32 total_fl; - if (!fmt || !plane->state || !src_width || !fmt->bpp) { + if (!fmt || !pipe || !src_width || !fmt->bpp) { DPU_ERROR("invalid arguments\n"); return 0; } pdpu = to_dpu_plane(plane); - pstate = to_dpu_plane_state(plane->state); fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; /* FIXME: in multirect case account for the src_width of all the planes */ @@ -252,7 +249,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, ((src_width + 32) * fmt->bpp); } } else { - if (pstate->pipe.multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { + if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { total_fl = (fixed_buff_size / 2) * 2 / ((src_width + 32) * fmt->bpp); } else { @@ -262,7 +259,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, } DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n", - pdpu->pipe - SSPP_VIG0, + pipe->sspp->idx - SSPP_VIG0, (char *)&fmt->base.pixel_format, src_width, total_fl); @@ -272,25 +269,22 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, /** * _dpu_plane_set_qos_lut - set QoS LUT of the given plane * @plane: Pointer to drm plane - * @fb: Pointer to framebuffer associated with the given plane + * @pipe: Pointer to software pipe + * @fmt: Pointer to source buffer format * @pipe_cfg: Pointer to pipe configuration */ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, - struct drm_framebuffer *fb, struct dpu_sw_pipe_cfg *pipe_cfg) + struct dpu_sw_pipe *pipe, + const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); - struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); - const struct dpu_format *fmt = NULL; u64 qos_lut; u32 total_fl = 0, lut_usage; if (!pdpu->is_rt_pipe) { lut_usage = DPU_QOS_LUT_USAGE_NRT; } else { - fmt = dpu_get_dpu_format_ext( - fb->format->format, - fb->modifier); - total_fl = _dpu_plane_calc_fill_level(plane, fmt, + total_fl = _dpu_plane_calc_fill_level(plane, pipe, fmt, drm_rect_width(&pipe_cfg->src_rect)); if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) @@ -302,7 +296,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, qos_lut = _dpu_hw_get_qos_lut( &pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); - trace_dpu_perf_set_qos_luts(pdpu->pipe - SSPP_VIG0, + trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0, pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); @@ -311,20 +305,20 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, fmt ? (char *)&fmt->base.pixel_format : NULL, pdpu->is_rt_pipe, total_fl, qos_lut); - pstate->pipe.sspp->ops.setup_creq_lut(pstate->pipe.sspp, qos_lut); + pipe->sspp->ops.setup_creq_lut(pipe->sspp, qos_lut); } /** * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane * @plane: Pointer to drm plane - * @fb: Pointer to framebuffer associated with the given plane + * @pipe: Pointer to software pipe + * @fmt: Pointer to source buffer format */ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, - struct drm_framebuffer *fb) + struct dpu_sw_pipe *pipe, + const struct dpu_format *fmt) { struct dpu_plane *pdpu = to_dpu_plane(plane); - struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); - const struct dpu_format *fmt = NULL; u32 danger_lut, safe_lut; if (!pdpu->is_rt_pipe) { @@ -333,10 +327,6 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, safe_lut = pdpu->catalog->perf->safe_lut_tbl [DPU_QOS_LUT_USAGE_NRT]; } else { - fmt = dpu_get_dpu_format_ext( - fb->format->format, - fb->modifier); - if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) { danger_lut = pdpu->catalog->perf->danger_lut_tbl [DPU_QOS_LUT_USAGE_LINEAR]; @@ -363,29 +353,30 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, danger_lut, safe_lut); - pstate->pipe.sspp->ops.setup_danger_safe_lut(pstate->pipe.sspp, + pipe->sspp->ops.setup_danger_safe_lut(pipe->sspp, danger_lut, safe_lut); } /** * _dpu_plane_set_qos_ctrl - set QoS control of the given plane * @plane: Pointer to drm plane + * @pipe: Pointer to software pipe * @enable: true to enable QoS control * @flags: QoS control mode (enum dpu_plane_qos) */ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, + struct dpu_sw_pipe *pipe, bool enable, u32 flags) { struct dpu_plane *pdpu = to_dpu_plane(plane); - struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { - pipe_qos_cfg.creq_vblank = pstate->pipe.sspp->cap->sblk->creq_vblank; + pipe_qos_cfg.creq_vblank = pipe->sspp->cap->sblk->creq_vblank; pipe_qos_cfg.danger_vblank = - pstate->pipe.sspp->cap->sblk->danger_vblank; + pipe->sspp->cap->sblk->danger_vblank; pipe_qos_cfg.vblank_en = enable; } @@ -411,33 +402,34 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, pipe_qos_cfg.danger_vblank, pdpu->is_rt_pipe); - pstate->pipe.sspp->ops.setup_qos_ctrl(pstate->pipe.sspp, + pipe->sspp->ops.setup_qos_ctrl(pipe->sspp, &pipe_qos_cfg); } /** * _dpu_plane_set_ot_limit - set OT limit for the given plane * @plane: Pointer to drm plane + * @pipe: Pointer to software pipe * @crtc: Pointer to drm crtc * @pipe_cfg: Pointer to pipe configuration */ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, + struct dpu_sw_pipe *pipe, struct drm_crtc *crtc, struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); - struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_vbif_set_ot_params ot_params; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); memset(&ot_params, 0, sizeof(ot_params)); - ot_params.xin_id = pstate->pipe.sspp->cap->xin_id; - ot_params.num = pstate->pipe.sspp->idx - SSPP_NONE; + ot_params.xin_id = pipe->sspp->cap->xin_id; + ot_params.num = pipe->sspp->idx - SSPP_NONE; ot_params.width = drm_rect_width(&pipe_cfg->src_rect); ot_params.height = drm_rect_height(&pipe_cfg->src_rect); ot_params.is_wfd = !pdpu->is_rt_pipe; ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); ot_params.vbif_idx = VBIF_RT; - ot_params.clk_ctrl = pstate->pipe.sspp->cap->clk_ctrl; + ot_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; ot_params.rd = true; dpu_vbif_set_ot_limit(dpu_kms, &ot_params); @@ -446,19 +438,20 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, /** * _dpu_plane_set_qos_remap - set vbif QoS for the given plane * @plane: Pointer to drm plane + * @pipe: Pointer to software pipe */ -static void _dpu_plane_set_qos_remap(struct drm_plane *plane) +static void _dpu_plane_set_qos_remap(struct drm_plane *plane, + struct dpu_sw_pipe *pipe) { struct dpu_plane *pdpu = to_dpu_plane(plane); - struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_vbif_set_qos_params qos_params; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); memset(&qos_params, 0, sizeof(qos_params)); qos_params.vbif_idx = VBIF_RT; - qos_params.clk_ctrl = pstate->pipe.sspp->cap->clk_ctrl; - qos_params.xin_id = pstate->pipe.sspp->cap->xin_id; - qos_params.num = pstate->pipe.sspp->idx - SSPP_VIG0; + qos_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; + qos_params.xin_id = pipe->sspp->cap->xin_id; + qos_params.num = pipe->sspp->idx - SSPP_VIG0; qos_params.is_rt = pdpu->is_rt_pipe; DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n", @@ -1145,7 +1138,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); pdpu->is_rt_pipe = is_rt_pipe; - _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); + _dpu_plane_set_qos_ctrl(plane, pipe, false, DPU_PLANE_QOS_PANIC_CTRL); DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), @@ -1214,20 +1207,20 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) } } - _dpu_plane_set_qos_lut(plane, fb, &pipe_cfg); - _dpu_plane_set_danger_lut(plane, fb); + _dpu_plane_set_qos_lut(plane, pipe, fmt, &pipe_cfg); + _dpu_plane_set_danger_lut(plane, pipe, fmt); if (plane->type != DRM_PLANE_TYPE_CURSOR) { - _dpu_plane_set_qos_ctrl(plane, true, DPU_PLANE_QOS_PANIC_CTRL); - _dpu_plane_set_ot_limit(plane, crtc, &pipe_cfg); + _dpu_plane_set_qos_ctrl(plane, pipe, true, DPU_PLANE_QOS_PANIC_CTRL); + _dpu_plane_set_ot_limit(plane, pipe, crtc, &pipe_cfg); } if (pstate->needs_qos_remap) { pstate->needs_qos_remap = false; - _dpu_plane_set_qos_remap(plane); + _dpu_plane_set_qos_remap(plane, pipe); } - _dpu_plane_calc_bw(plane, fb, &pipe_cfg); + _dpu_plane_calc_bw(plane, fmt, &pipe_cfg); _dpu_plane_calc_clk(plane, &pipe_cfg); } @@ -1264,11 +1257,13 @@ static void dpu_plane_atomic_update(struct drm_plane *plane, static void dpu_plane_destroy(struct drm_plane *plane) { struct dpu_plane *pdpu = plane ? to_dpu_plane(plane) : NULL; + struct dpu_plane_state *pstate; DPU_DEBUG_PLANE(pdpu, "\n"); if (pdpu) { - _dpu_plane_set_qos_ctrl(plane, false, DPU_PLANE_QOS_PANIC_CTRL); + pstate = to_dpu_plane_state(plane->state); + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, false, DPU_PLANE_QOS_PANIC_CTRL); mutex_destroy(&pdpu->lock); @@ -1397,13 +1392,14 @@ static void dpu_plane_reset(struct drm_plane *plane) void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) { struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); if (!pdpu->is_rt_pipe) return; pm_runtime_get_sync(&dpu_kms->pdev->dev); - _dpu_plane_set_qos_ctrl(plane, enable, DPU_PLANE_QOS_PANIC_CTRL); + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable, DPU_PLANE_QOS_PANIC_CTRL); pm_runtime_put_sync(&dpu_kms->pdev->dev); } #endif From 7c68ed04c389691b2f82e7853530096601a55b0c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:40 +0300 Subject: [PATCH 24/42] drm/msm/dpu: make _dpu_plane_calc_clk accept mode directly Rework bandwidth/clock calculation functions to use mode directly rather than fetching it through the plane data. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527344/ Link: https://lore.kernel.org/r/20230316161653.4106395-20-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 39 ++++++++++------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 0660ceea8eb8..5eee845824f7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -128,20 +128,19 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) /** * _dpu_plane_calc_bw - calculate bandwidth required for a plane - * @plane: Pointer to drm plane. + * @catalog: Points to dpu catalog structure * @fmt: Pointer to source buffer format + * @mode: Pointer to drm display mode * @pipe_cfg: Pointer to pipe configuration * Result: Updates calculated bandwidth in the plane state. * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest) * Prefill BW Equation: line src bytes * line_time */ -static void _dpu_plane_calc_bw(struct drm_plane *plane, +static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog, const struct dpu_format *fmt, + const struct drm_display_mode *mode, struct dpu_sw_pipe_cfg *pipe_cfg) { - struct dpu_plane_state *pstate; - struct drm_display_mode *mode; - struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); int src_width, src_height, dst_height, fps; u64 plane_prefill_bw; u64 plane_bw; @@ -149,9 +148,6 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, u64 scale_factor; int vbp, vpw, vfp; - pstate = to_dpu_plane_state(plane->state); - mode = &plane->state->crtc->mode; - src_width = drm_rect_width(&pipe_cfg->src_rect); src_height = drm_rect_height(&pipe_cfg->src_rect); dst_height = drm_rect_height(&pipe_cfg->dst_rect); @@ -159,7 +155,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, vbp = mode->vtotal - mode->vsync_end; vpw = mode->vsync_end - mode->vsync_start; vfp = mode->vsync_start - mode->vdisplay; - hw_latency_lines = dpu_kms->catalog->perf->min_prefill_lines; + hw_latency_lines = catalog->perf->min_prefill_lines; scale_factor = src_height > dst_height ? mult_frac(src_height, 1, dst_height) : 1; @@ -179,37 +175,36 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, do_div(plane_prefill_bw, hw_latency_lines); - pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw); + return max(plane_bw, plane_prefill_bw); } /** * _dpu_plane_calc_clk - calculate clock required for a plane - * @plane: Pointer to drm plane. + * @mode: Pointer to drm display mode * @pipe_cfg: Pointer to pipe configuration * Result: Updates calculated clock in the plane state. * Clock equation: dst_w * v_total * fps * (src_h / dst_h) */ -static void _dpu_plane_calc_clk(struct drm_plane *plane, struct dpu_sw_pipe_cfg *pipe_cfg) +static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode, + struct dpu_sw_pipe_cfg *pipe_cfg) { - struct dpu_plane_state *pstate; - struct drm_display_mode *mode; int dst_width, src_height, dst_height, fps; - - pstate = to_dpu_plane_state(plane->state); - mode = &plane->state->crtc->mode; + u64 plane_clk; src_height = drm_rect_height(&pipe_cfg->src_rect); dst_width = drm_rect_width(&pipe_cfg->dst_rect); dst_height = drm_rect_height(&pipe_cfg->dst_rect); fps = drm_mode_vrefresh(mode); - pstate->plane_clk = + plane_clk = dst_width * mode->vtotal * fps; if (src_height > dst_height) { - pstate->plane_clk *= src_height; - do_div(pstate->plane_clk, dst_height); + plane_clk *= src_height; + do_div(plane_clk, dst_height); } + + return plane_clk; } /** @@ -1220,9 +1215,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) _dpu_plane_set_qos_remap(plane, pipe); } - _dpu_plane_calc_bw(plane, fmt, &pipe_cfg); + pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, &pipe_cfg); - _dpu_plane_calc_clk(plane, &pipe_cfg); + pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, &pipe_cfg); } static void _dpu_plane_atomic_disable(struct drm_plane *plane) From 6e0ce9ec184a1b412d2eb920dbc946c49a998652 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:41 +0300 Subject: [PATCH 25/42] drm/msm/dpu: add dpu_hw_sspp_cfg to dpu_plane_state Now as all accesses to pipe_cfg and pstate have been cleaned, add struct dpu_hw_sspp_cfg to struct dpu_plane_state, so that dpu_plane_atomic_check() and dpu_plane_atomic_update() do not have a chance to disagree about src/dst rectangles (currently dpu_plane_atomic_check() uses unclipped rectangles, while dpu_plane_atomic_update() uses clipped rectangles calculated by drm_atomic_helper_check_plane_state()). Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527352/ Link: https://lore.kernel.org/r/20230316161653.4106395-21-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 66 +++++++++++------------ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 + 2 files changed, 32 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 5eee845824f7..1453d02bf244 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -952,7 +952,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); const struct drm_crtc_state *crtc_state = NULL; const struct dpu_format *fmt; - struct drm_rect src, dst, fb_rect = { 0 }; + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; + struct drm_rect fb_rect = { 0 }; uint32_t min_src_size, max_linewidth; unsigned int rotation; uint32_t supported_rotations; @@ -985,12 +986,15 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return -EINVAL; } - src.x1 = new_plane_state->src_x >> 16; - src.y1 = new_plane_state->src_y >> 16; - src.x2 = src.x1 + (new_plane_state->src_w >> 16); - src.y2 = src.y1 + (new_plane_state->src_h >> 16); + pipe_cfg->src_rect = new_plane_state->src; - dst = drm_plane_state_dest(new_plane_state); + /* state->src is 16.16, src_rect is not */ + pipe_cfg->src_rect.x1 >>= 16; + pipe_cfg->src_rect.x2 >>= 16; + pipe_cfg->src_rect.y1 >>= 16; + pipe_cfg->src_rect.y2 >>= 16; + + pipe_cfg->dst_rect = new_plane_state->dst; fb_rect.x2 = new_plane_state->fb->width; fb_rect.y2 = new_plane_state->fb->height; @@ -1009,30 +1013,31 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return -EINVAL; /* check src bounds */ - } else if (!dpu_plane_validate_src(&src, &fb_rect, min_src_size)) { + } else if (!dpu_plane_validate_src(&pipe_cfg->src_rect, &fb_rect, min_src_size)) { DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", - DRM_RECT_ARG(&src)); + DRM_RECT_ARG(&pipe_cfg->src_rect)); return -E2BIG; /* valid yuv image */ } else if (DPU_FORMAT_IS_YUV(fmt) && - (src.x1 & 0x1 || src.y1 & 0x1 || - drm_rect_width(&src) & 0x1 || - drm_rect_height(&src) & 0x1)) { + (pipe_cfg->src_rect.x1 & 0x1 || pipe_cfg->src_rect.y1 & 0x1 || + drm_rect_width(&pipe_cfg->src_rect) & 0x1 || + drm_rect_height(&pipe_cfg->src_rect) & 0x1)) { DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", - DRM_RECT_ARG(&src)); + DRM_RECT_ARG(&pipe_cfg->src_rect)); return -EINVAL; /* min dst support */ - } else if (drm_rect_width(&dst) < 0x1 || drm_rect_height(&dst) < 0x1) { + } else if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || + drm_rect_height(&pipe_cfg->dst_rect) < 0x1) { DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", - DRM_RECT_ARG(&dst)); + DRM_RECT_ARG(&pipe_cfg->dst_rect)); return -EINVAL; /* check decimated source width */ - } else if (drm_rect_width(&src) > max_linewidth) { + } else if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", - DRM_RECT_ARG(&src), max_linewidth); + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); return -E2BIG; } @@ -1046,7 +1051,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && (rotation & DRM_MODE_ROTATE_90)) { - ret = dpu_plane_check_inline_rotation(pdpu, sblk, src, fmt); + ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt); if (ret) return ret; } @@ -1121,9 +1126,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) bool is_rt_pipe; const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(fb)); - struct dpu_sw_pipe_cfg pipe_cfg; - - memset(&pipe_cfg, 0, sizeof(struct dpu_sw_pipe_cfg)); + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; _dpu_plane_set_scanout(plane, pstate, fb); @@ -1140,16 +1143,6 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) crtc->base.id, DRM_RECT_ARG(&state->dst), (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); - pipe_cfg.src_rect = state->src; - - /* state->src is 16.16, src_rect is not */ - pipe_cfg.src_rect.x1 >>= 16; - pipe_cfg.src_rect.x2 >>= 16; - pipe_cfg.src_rect.y1 >>= 16; - pipe_cfg.src_rect.y2 >>= 16; - - pipe_cfg.dst_rect = state->dst; - /* override for color fill */ if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { /* skip remaining processing on color fill */ @@ -1158,10 +1151,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) if (pipe->sspp->ops.setup_rects) { pipe->sspp->ops.setup_rects(pipe, - &pipe_cfg); + pipe_cfg); } - _dpu_plane_setup_scaler(pipe, fmt, false, &pipe_cfg, pstate->rotation); + _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation); if (pipe->sspp->ops.setup_multirect) pipe->sspp->ops.setup_multirect( @@ -1202,12 +1195,12 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) } } - _dpu_plane_set_qos_lut(plane, pipe, fmt, &pipe_cfg); + _dpu_plane_set_qos_lut(plane, pipe, fmt, &pstate->pipe_cfg); _dpu_plane_set_danger_lut(plane, pipe, fmt); if (plane->type != DRM_PLANE_TYPE_CURSOR) { _dpu_plane_set_qos_ctrl(plane, pipe, true, DPU_PLANE_QOS_PANIC_CTRL); - _dpu_plane_set_ot_limit(plane, pipe, crtc, &pipe_cfg); + _dpu_plane_set_ot_limit(plane, pipe, crtc, &pstate->pipe_cfg); } if (pstate->needs_qos_remap) { @@ -1215,9 +1208,10 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) _dpu_plane_set_qos_remap(plane, pipe); } - pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, &pipe_cfg); + pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, + &crtc->mode, &pstate->pipe_cfg); - pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, &pipe_cfg); + pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, &pstate->pipe_cfg); } static void _dpu_plane_atomic_disable(struct drm_plane *plane) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index a08b0539513b..0ca9002015ff 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -19,6 +19,7 @@ * @base: base drm plane state object * @aspace: pointer to address space for input/output buffers * @pipe: software pipe description + * @pipe_cfg: software pipe configuration * @stage: assigned by crtc blender * @needs_qos_remap: qos remap settings need to be updated * @multirect_index: index of the rectangle of SSPP @@ -33,6 +34,7 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; struct dpu_sw_pipe pipe; + struct dpu_sw_pipe_cfg pipe_cfg; enum dpu_stage stage; bool needs_qos_remap; bool pending; From 55d3f857dde6af2e60385938899f48badd023efe Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:42 +0300 Subject: [PATCH 26/42] drm/msm/dpu: simplify dpu_plane_validate_src() The plane's clipped coordinates has already been validated against FB size in the drm_atomic_plane_check(). There is no need to check them again. Remove corresponding checks and inline dpu_plane_validate_src(). Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527364/ Link: https://lore.kernel.org/r/20230316161653.4106395-22-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 30 ++++++++--------------- 1 file changed, 10 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 1453d02bf244..4221025cd6a2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -895,25 +895,6 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane, old_pstate->needs_dirtyfb); } -static bool dpu_plane_validate_src(struct drm_rect *src, - struct drm_rect *fb_rect, - uint32_t min_src_size) -{ - /* Ensure fb size is supported */ - if (drm_rect_width(fb_rect) > MAX_IMG_WIDTH || - drm_rect_height(fb_rect) > MAX_IMG_HEIGHT) - return false; - - /* Ensure src rect is above the minimum size */ - if (drm_rect_width(src) < min_src_size || - drm_rect_height(src) < min_src_size) - return false; - - /* Ensure src is fully encapsulated in fb */ - return drm_rect_intersect(fb_rect, src) && - drm_rect_equals(fb_rect, src); -} - static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, const struct dpu_sspp_sub_blks *sblk, struct drm_rect src, const struct dpu_format *fmt) @@ -999,6 +980,14 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, fb_rect.x2 = new_plane_state->fb->width; fb_rect.y2 = new_plane_state->fb->height; + /* Ensure fb size is supported */ + if (drm_rect_width(&fb_rect) > MAX_IMG_WIDTH || + drm_rect_height(&fb_rect) > MAX_IMG_HEIGHT) { + DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&fb_rect)); + return -E2BIG; + } + max_linewidth = pdpu->catalog->caps->max_linewidth; fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); @@ -1013,7 +1002,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return -EINVAL; /* check src bounds */ - } else if (!dpu_plane_validate_src(&pipe_cfg->src_rect, &fb_rect, min_src_size)) { + } else if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size || + drm_rect_height(&pipe_cfg->src_rect) < min_src_size) { DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); return -E2BIG; From 27653c574ad47f2fa9cedd0df44fabe23ce4a47f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:43 +0300 Subject: [PATCH 27/42] drm/msm/dpu: rework dpu_plane_sspp_atomic_update() Split pipe-dependent code from dpu_plane_sspp_atomic_update() into the separate function dpu_plane_sspp_update_pipe(). This is one of preparational steps to add r_pipe support. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527337/ Link: https://lore.kernel.org/r/20230316161653.4106395-23-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 113 ++++++++++++---------- 1 file changed, 63 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 4221025cd6a2..a1517748e8e2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -405,12 +405,13 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, * _dpu_plane_set_ot_limit - set OT limit for the given plane * @plane: Pointer to drm plane * @pipe: Pointer to software pipe - * @crtc: Pointer to drm crtc * @pipe_cfg: Pointer to pipe configuration + * @frame_rate: CRTC's frame rate */ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, struct dpu_sw_pipe *pipe, - struct drm_crtc *crtc, struct dpu_sw_pipe_cfg *pipe_cfg) + struct dpu_sw_pipe_cfg *pipe_cfg, + int frame_rate) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_vbif_set_ot_params ot_params; @@ -422,7 +423,7 @@ static void _dpu_plane_set_ot_limit(struct drm_plane *plane, ot_params.width = drm_rect_width(&pipe_cfg->src_rect); ot_params.height = drm_rect_height(&pipe_cfg->src_rect); ot_params.is_wfd = !pdpu->is_rt_pipe; - ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode); + ot_params.frame_rate = frame_rate; ot_params.vbif_idx = VBIF_RT; ot_params.clk_ctrl = pipe->sspp->cap->clk_ctrl; ot_params.rd = true; @@ -458,26 +459,6 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane, dpu_vbif_set_qos_remap(dpu_kms, &qos_params); } -static void _dpu_plane_set_scanout(struct drm_plane *plane, - struct dpu_plane_state *pstate, - struct drm_framebuffer *fb) -{ - struct dpu_plane *pdpu = to_dpu_plane(plane); - struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); - struct msm_gem_address_space *aspace = kms->base.aspace; - struct dpu_hw_fmt_layout layout; - int ret; - - ret = dpu_format_populate_layout(aspace, fb, &layout); - if (ret) - DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); - else if (pstate->pipe.sspp->ops.setup_sourceaddress) { - trace_dpu_plane_set_scanout(&pstate->pipe, - &layout); - pstate->pipe.sspp->ops.setup_sourceaddress(&pstate->pipe, &layout); - } -} - static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, struct dpu_hw_scaler3_cfg *scale_cfg, @@ -1104,35 +1085,25 @@ void dpu_plane_set_error(struct drm_plane *plane, bool error) pdpu->is_error = error; } -static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) +static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, + struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *pipe_cfg, + const struct dpu_format *fmt, + int frame_rate, + struct dpu_hw_fmt_layout *layout) { uint32_t src_flags; struct dpu_plane *pdpu = to_dpu_plane(plane); struct drm_plane_state *state = plane->state; struct dpu_plane_state *pstate = to_dpu_plane_state(state); - struct dpu_sw_pipe *pipe = &pstate->pipe; - struct drm_crtc *crtc = state->crtc; - struct drm_framebuffer *fb = state->fb; - bool is_rt_pipe; - const struct dpu_format *fmt = - to_dpu_format(msm_framebuffer_format(fb)); - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; - _dpu_plane_set_scanout(plane, pstate, fb); - - pstate->pending = true; - - is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); - pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); - pdpu->is_rt_pipe = is_rt_pipe; + if (layout && pipe->sspp->ops.setup_sourceaddress) { + trace_dpu_plane_set_scanout(pipe, layout); + pipe->sspp->ops.setup_sourceaddress(pipe, layout); + } _dpu_plane_set_qos_ctrl(plane, pipe, false, DPU_PLANE_QOS_PANIC_CTRL); - DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT - ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), - crtc->base.id, DRM_RECT_ARG(&state->dst), - (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); - /* override for color fill */ if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { /* skip remaining processing on color fill */ @@ -1185,23 +1156,65 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) } } - _dpu_plane_set_qos_lut(plane, pipe, fmt, &pstate->pipe_cfg); + _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); _dpu_plane_set_danger_lut(plane, pipe, fmt); if (plane->type != DRM_PLANE_TYPE_CURSOR) { _dpu_plane_set_qos_ctrl(plane, pipe, true, DPU_PLANE_QOS_PANIC_CTRL); - _dpu_plane_set_ot_limit(plane, pipe, crtc, &pstate->pipe_cfg); + _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate); } - if (pstate->needs_qos_remap) { - pstate->needs_qos_remap = false; + if (pstate->needs_qos_remap) _dpu_plane_set_qos_remap(plane, pipe); - } +} + +static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) +{ + struct dpu_plane *pdpu = to_dpu_plane(plane); + struct drm_plane_state *state = plane->state; + struct dpu_plane_state *pstate = to_dpu_plane_state(state); + struct dpu_sw_pipe *pipe = &pstate->pipe; + struct drm_crtc *crtc = state->crtc; + struct drm_framebuffer *fb = state->fb; + bool is_rt_pipe; + const struct dpu_format *fmt = + to_dpu_format(msm_framebuffer_format(fb)); + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; + + struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); + struct msm_gem_address_space *aspace = kms->base.aspace; + struct dpu_hw_fmt_layout layout; + bool layout_valid = false; + int ret; + + ret = dpu_format_populate_layout(aspace, fb, &layout); + if (ret) + DPU_ERROR_PLANE(pdpu, "failed to get format layout, %d\n", ret); + else + layout_valid = true; + + pstate->pending = true; + + is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT); + pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe); + pdpu->is_rt_pipe = is_rt_pipe; + + DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT + ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), + crtc->base.id, DRM_RECT_ARG(&state->dst), + (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); + + dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, + drm_mode_vrefresh(&crtc->mode), + layout_valid ? &layout : NULL); + + if (pstate->needs_qos_remap) + pstate->needs_qos_remap = false; pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt, - &crtc->mode, &pstate->pipe_cfg); + &crtc->mode, pipe_cfg); - pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, &pstate->pipe_cfg); + pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); } static void _dpu_plane_atomic_disable(struct drm_plane *plane) From 6d7e1ca701df8b3e77c5e79c5b5672eda0b27da1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:44 +0300 Subject: [PATCH 28/42] drm/msm/dpu: rework dpu_plane_atomic_check() Split pipe-dependent code from dpu_plane_atomic_check() into the separate function dpu_plane_atomic_check_pipe(). This is one of preparational steps to add r_pipe support. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527336/ Link: https://lore.kernel.org/r/20230316161653.4106395-24-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 91 ++++++++++++++--------- 1 file changed, 55 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index a1517748e8e2..8e34018aea6a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -904,6 +904,53 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, return 0; } +static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, + struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *pipe_cfg, + const struct dpu_format *fmt) +{ + uint32_t min_src_size; + + min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; + + if (DPU_FORMAT_IS_YUV(fmt) && + (!(pipe->sspp->cap->features & DPU_SSPP_SCALER) || + !(pipe->sspp->cap->features & DPU_SSPP_CSC_ANY))) { + DPU_DEBUG_PLANE(pdpu, + "plane doesn't have scaler/csc for yuv\n"); + return -EINVAL; + } + + /* check src bounds */ + if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size || + drm_rect_height(&pipe_cfg->src_rect) < min_src_size) { + DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect)); + return -E2BIG; + } + + /* valid yuv image */ + if (DPU_FORMAT_IS_YUV(fmt) && + (pipe_cfg->src_rect.x1 & 0x1 || + pipe_cfg->src_rect.y1 & 0x1 || + drm_rect_width(&pipe_cfg->src_rect) & 0x1 || + drm_rect_height(&pipe_cfg->src_rect) & 0x1)) { + DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect)); + return -EINVAL; + } + + /* min dst support */ + if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || + drm_rect_height(&pipe_cfg->dst_rect) < 0x1) { + DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->dst_rect)); + return -EINVAL; + } + + return 0; +} + static int dpu_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { @@ -916,7 +963,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, const struct dpu_format *fmt; struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; struct drm_rect fb_rect = { 0 }; - uint32_t min_src_size, max_linewidth; + uint32_t max_linewidth; unsigned int rotation; uint32_t supported_rotations; const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap; @@ -971,47 +1018,19 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, max_linewidth = pdpu->catalog->caps->max_linewidth; - fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); - - min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; - - if (DPU_FORMAT_IS_YUV(fmt) && - (!(pipe_hw_caps->features & DPU_SSPP_SCALER) || - !(pipe_hw_caps->features & DPU_SSPP_CSC_ANY))) { - DPU_DEBUG_PLANE(pdpu, - "plane doesn't have scaler/csc for yuv\n"); - return -EINVAL; - - /* check src bounds */ - } else if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size || - drm_rect_height(&pipe_cfg->src_rect) < min_src_size) { - DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n", - DRM_RECT_ARG(&pipe_cfg->src_rect)); - return -E2BIG; - - /* valid yuv image */ - } else if (DPU_FORMAT_IS_YUV(fmt) && - (pipe_cfg->src_rect.x1 & 0x1 || pipe_cfg->src_rect.y1 & 0x1 || - drm_rect_width(&pipe_cfg->src_rect) & 0x1 || - drm_rect_height(&pipe_cfg->src_rect) & 0x1)) { - DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n", - DRM_RECT_ARG(&pipe_cfg->src_rect)); - return -EINVAL; - - /* min dst support */ - } else if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 || - drm_rect_height(&pipe_cfg->dst_rect) < 0x1) { - DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", - DRM_RECT_ARG(&pipe_cfg->dst_rect)); - return -EINVAL; - /* check decimated source width */ - } else if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { + if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); return -E2BIG; } + fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); + + ret = dpu_plane_atomic_check_pipe(pdpu, &pstate->pipe, pipe_cfg, fmt); + if (ret) + return ret; + supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) From ea2d3612fdf9d51dc3747362633d438b5c216894 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:45 +0300 Subject: [PATCH 29/42] drm/msm/dpu: rework plane CSC setting Rework the code flushing CSC settings for the plane. Separate out the pipe and pipe_cfg as a preparation for r_pipe support. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527347/ Link: https://lore.kernel.org/r/20230316161653.4106395-25-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 47 +++++++++++++---------- 1 file changed, 27 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 8e34018aea6a..b8084c2fa132 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -577,29 +577,19 @@ static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,}, }; -static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_plane *pdpu, const struct dpu_format *fmt) +static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, + const struct dpu_format *fmt) { - struct dpu_plane_state *pstate = to_dpu_plane_state(pdpu->base.state); const struct dpu_csc_cfg *csc_ptr; - if (!pdpu) { - DPU_ERROR("invalid plane\n"); - return NULL; - } - if (!DPU_FORMAT_IS_YUV(fmt)) return NULL; - if (BIT(DPU_SSPP_CSC_10BIT) & pstate->pipe.sspp->cap->features) + if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features) csc_ptr = &dpu_csc10_YUV2RGB_601L; else csc_ptr = &dpu_csc_YUV2RGB_601L; - DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", - csc_ptr->csc_mv[0], - csc_ptr->csc_mv[1], - csc_ptr->csc_mv[2]); - return csc_ptr; } @@ -1052,6 +1042,28 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return 0; } +static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) +{ + const struct dpu_format *format = + to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb)); + const struct dpu_csc_cfg *csc_ptr; + + if (!pipe->sspp || !pipe->sspp->ops.setup_csc) + return; + + csc_ptr = _dpu_plane_get_csc(pipe, format); + if (!csc_ptr) + return; + + DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n", + csc_ptr->csc_mv[0], + csc_ptr->csc_mv[1], + csc_ptr->csc_mv[2]); + + pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr); + +} + void dpu_plane_flush(struct drm_plane *plane) { struct dpu_plane *pdpu; @@ -1075,13 +1087,8 @@ void dpu_plane_flush(struct drm_plane *plane) else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); - else if (pstate->pipe.sspp && pstate->pipe.sspp->ops.setup_csc) { - const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(plane->state->fb)); - const struct dpu_csc_cfg *csc_ptr = _dpu_plane_get_csc(pdpu, fmt); - - if (csc_ptr) - pstate->pipe.sspp->ops.setup_csc(pstate->pipe.sspp, csc_ptr); - } + else + dpu_plane_flush_csc(pdpu, &pstate->pipe); /* flag h/w flush complete */ if (plane->state) From 6270e5240227bc014c452720220776c30ff3765b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:46 +0300 Subject: [PATCH 30/42] drm/msm/dpu: rework static color fill code Rework static color fill code to separate the pipe / pipe_cfg handling. This is a preparation for the r_pipe support. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527340/ Link: https://lore.kernel.org/r/20230316161653.4106395-26-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 69 +++++++++++++---------- 1 file changed, 40 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index b8084c2fa132..8a66261ddfd9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -641,20 +641,52 @@ static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, fmt); } +static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, + struct dpu_sw_pipe *pipe, + struct drm_rect *dst_rect, + u32 fill_color, + const struct dpu_format *fmt) +{ + struct dpu_sw_pipe_cfg pipe_cfg; + + /* update sspp */ + if (!pipe->sspp->ops.setup_solidfill) + return; + + pipe->sspp->ops.setup_solidfill(pipe, fill_color); + + /* override scaler/decimation if solid fill */ + pipe_cfg.dst_rect = *dst_rect; + + pipe_cfg.src_rect.x1 = 0; + pipe_cfg.src_rect.y1 = 0; + pipe_cfg.src_rect.x2 = + drm_rect_width(&pipe_cfg.dst_rect); + pipe_cfg.src_rect.y2 = + drm_rect_height(&pipe_cfg.dst_rect); + + if (pipe->sspp->ops.setup_format) + pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL); + + if (pipe->sspp->ops.setup_rects) + pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); + + _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation); +} + /** * _dpu_plane_color_fill - enables color fill on plane * @pdpu: Pointer to DPU plane object * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red * @alpha: 8-bit fill alpha value, 255 selects 100% alpha - * Returns: 0 on success */ -static int _dpu_plane_color_fill(struct dpu_plane *pdpu, +static void _dpu_plane_color_fill(struct dpu_plane *pdpu, uint32_t color, uint32_t alpha) { const struct dpu_format *fmt; const struct drm_plane *plane = &pdpu->base; struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); - struct dpu_sw_pipe_cfg pipe_cfg; + u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); DPU_DEBUG_PLANE(pdpu, "\n"); @@ -663,34 +695,13 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, * h/w only supports RGB variants */ fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); + /* should not happen ever */ + if (!fmt) + return; /* update sspp */ - if (fmt && pstate->pipe.sspp->ops.setup_solidfill) { - pstate->pipe.sspp->ops.setup_solidfill(&pstate->pipe, - (color & 0xFFFFFF) | ((alpha & 0xFF) << 24)); - - /* override scaler/decimation if solid fill */ - pipe_cfg.dst_rect = pstate->base.dst; - - pipe_cfg.src_rect.x1 = 0; - pipe_cfg.src_rect.y1 = 0; - pipe_cfg.src_rect.x2 = - drm_rect_width(&pipe_cfg.dst_rect); - pipe_cfg.src_rect.y2 = - drm_rect_height(&pipe_cfg.dst_rect); - - if (pstate->pipe.sspp->ops.setup_format) - pstate->pipe.sspp->ops.setup_format(&pstate->pipe, - fmt, DPU_SSPP_SOLID_FILL); - - if (pstate->pipe.sspp->ops.setup_rects) - pstate->pipe.sspp->ops.setup_rects(&pstate->pipe, - &pipe_cfg); - - _dpu_plane_setup_scaler(&pstate->pipe, fmt, true, &pipe_cfg, pstate->rotation); - } - - return 0; + _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, + fill_color, fmt); } int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) From dc0b5a61d2d5b682a84ed76fdb16a7c8b7e08533 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:47 +0300 Subject: [PATCH 31/42] drm/msm/dpu: split pipe handling from _dpu_crtc_blend_setup_mixer Rework _dpu_crtc_blend_setup_mixer() to split away pipe handling to a separate functon. This is a preparation for the r_pipe support. Reviewed-by: Abhinav Kumar Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527354/ Link: https://lore.kernel.org/r/20230316161653.4106395-27-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 79 +++++++++++++++--------- 1 file changed, 50 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index dba5e4fbdb57..1636347d674c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -401,6 +401,46 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) } } +static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, + struct drm_plane *plane, + struct dpu_crtc_mixer *mixer, + u32 num_mixers, + enum dpu_stage stage, + struct dpu_format *format, + uint64_t modifier, + struct dpu_sw_pipe *pipe, + unsigned int stage_idx, + struct dpu_hw_stage_cfg *stage_cfg + ) +{ + uint32_t lm_idx; + enum dpu_sspp sspp_idx; + struct drm_plane_state *state; + + sspp_idx = pipe->sspp->idx; + + state = plane->state; + + trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), + state, to_dpu_plane_state(state), stage_idx, + format->base.pixel_format, + modifier); + + DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", + crtc->base.id, + stage, + plane->base.id, + sspp_idx - SSPP_NONE, + state->fb ? state->fb->base.id : -1); + + stage_cfg->stage[stage][stage_idx] = sspp_idx; + stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index; + + /* blend config update */ + for (lm_idx = 0; lm_idx < num_mixers; lm_idx++) + mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx); +} + static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer, struct dpu_hw_stage_cfg *stage_cfg) @@ -413,15 +453,12 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, struct dpu_format *format; struct dpu_hw_ctl *ctl = mixer->lm_ctl; - uint32_t stage_idx, lm_idx; - int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 }; + uint32_t lm_idx; bool bg_alpha_enable = false; DECLARE_BITMAP(fetch_active, SSPP_MAX); memset(fetch_active, 0, sizeof(fetch_active)); drm_atomic_crtc_for_each_plane(plane, crtc) { - enum dpu_sspp sspp_idx; - state = plane->state; if (!state) continue; @@ -432,39 +469,21 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, pstate = to_dpu_plane_state(state); fb = state->fb; - sspp_idx = pstate->pipe.sspp->idx; - set_bit(sspp_idx, fetch_active); - - DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", - crtc->base.id, - pstate->stage, - plane->base.id, - sspp_idx - SSPP_VIG0, - state->fb ? state->fb->base.id : -1); - format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable = true; - stage_idx = zpos_cnt[pstate->stage]++; - stage_cfg->stage[pstate->stage][stage_idx] = - sspp_idx; - stage_cfg->multirect_index[pstate->stage][stage_idx] = - pstate->pipe.multirect_index; - - trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), - state, pstate, stage_idx, - format->base.pixel_format, - fb ? fb->modifier : 0); + set_bit(pstate->pipe.sspp->idx, fetch_active); + _dpu_crtc_blend_setup_pipe(crtc, plane, + mixer, cstate->num_mixers, + pstate->stage, + format, fb ? fb->modifier : 0, + &pstate->pipe, 0, stage_cfg); /* blend config update */ for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { - _dpu_crtc_setup_blend_cfg(mixer + lm_idx, - pstate, format); - - mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, - sspp_idx); + _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format); if (bg_alpha_enable && !format->alpha_enable) mixer[lm_idx].mixer_op_mode = 0; @@ -1322,6 +1341,8 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); + seq_printf(s, "\tsspp:%s\n", + pstate->pipe.sspp->cap->name); seq_printf(s, "\tmultirect: mode: %d index: %d\n", pstate->pipe.multirect_mode, pstate->pipe.multirect_index); From 80e8ae3b38ab99a0648e07966595ba06c6302d2e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:48 +0300 Subject: [PATCH 32/42] drm/msm/dpu: add support for wide planes It is possible to use multirect feature and split source to use the SSPP to output two consecutive rectangles. This commit brings in this capability to support wider screen resolutions. Tested-by: Abhinav Kumar # sc7280 Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/527358/ Link: https://lore.kernel.org/r/20230316161653.4106395-28-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 19 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 142 +++++++++++++++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 + 3 files changed, 145 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 1636347d674c..ffc87662ce0b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -481,6 +481,15 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, format, fb ? fb->modifier : 0, &pstate->pipe, 0, stage_cfg); + if (pstate->r_pipe.sspp) { + set_bit(pstate->r_pipe.sspp->idx, fetch_active); + _dpu_crtc_blend_setup_pipe(crtc, plane, + mixer, cstate->num_mixers, + pstate->stage, + format, fb ? fb->modifier : 0, + &pstate->r_pipe, 1, stage_cfg); + } + /* blend config update */ for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format); @@ -1341,10 +1350,16 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); - seq_printf(s, "\tsspp:%s\n", + seq_printf(s, "\tsspp[0]:%s\n", pstate->pipe.sspp->cap->name); - seq_printf(s, "\tmultirect: mode: %d index: %d\n", + seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n", pstate->pipe.multirect_mode, pstate->pipe.multirect_index); + if (pstate->r_pipe.sspp) { + seq_printf(s, "\tsspp[1]:%s\n", + pstate->r_pipe.sspp->cap->name); + seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n", + pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index); + } seq_puts(s, "\n"); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 8a66261ddfd9..8fa4fafe7f17 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -702,6 +702,10 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu, /* update sspp */ _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect, fill_color, fmt); + + if (pstate->r_pipe.sspp) + _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect, + fill_color, fmt); } int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) @@ -960,9 +964,12 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, int ret = 0, min_scale; struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); + struct dpu_sw_pipe *pipe = &pstate->pipe; + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; const struct drm_crtc_state *crtc_state = NULL; const struct dpu_format *fmt; struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; struct drm_rect fb_rect = { 0 }; uint32_t max_linewidth; unsigned int rotation; @@ -986,8 +993,11 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, if (!new_plane_state->visible) return 0; - pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; - pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; + pipe->multirect_index = DPU_SSPP_RECT_SOLO; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + r_pipe->sspp = NULL; pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { @@ -1017,21 +1027,67 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return -E2BIG; } - max_linewidth = pdpu->catalog->caps->max_linewidth; - - /* check decimated source width */ - if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; - } - fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); - ret = dpu_plane_atomic_check_pipe(pdpu, &pstate->pipe, pipe_cfg, fmt); + max_linewidth = pdpu->catalog->caps->max_linewidth; + + if (drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { + /* + * In parallel multirect case only the half of the usual width + * is supported for tiled formats. If we are here, we know that + * full width is more than max_linewidth, thus each rect is + * wider than allowed. + */ + if (DPU_FORMAT_IS_UBWC(fmt)) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } + + if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } + + if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || + drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || + (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && + !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || + DPU_FORMAT_IS_YUV(fmt)) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } + + /* + * Use multirect for wide plane. We do not support dynamic + * assignment of SSPPs, so we know the configuration. + */ + pipe->multirect_index = DPU_SSPP_RECT_0; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + + r_pipe->sspp = pipe->sspp; + r_pipe->multirect_index = DPU_SSPP_RECT_1; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + + *r_pipe_cfg = *pipe_cfg; + pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; + pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; + r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; + r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; + } + + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt); if (ret) return ret; + if (r_pipe->sspp) { + ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt); + if (ret) + return ret; + } + supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) @@ -1098,8 +1154,10 @@ void dpu_plane_flush(struct drm_plane *plane) else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); - else + else { dpu_plane_flush_csc(pdpu, &pstate->pipe); + dpu_plane_flush_csc(pdpu, &pstate->r_pipe); + } /* flag h/w flush complete */ if (plane->state) @@ -1211,13 +1269,14 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) struct drm_plane_state *state = plane->state; struct dpu_plane_state *pstate = to_dpu_plane_state(state); struct dpu_sw_pipe *pipe = &pstate->pipe; + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; struct drm_crtc *crtc = state->crtc; struct drm_framebuffer *fb = state->fb; bool is_rt_pipe; const struct dpu_format *fmt = to_dpu_format(msm_framebuffer_format(fb)); struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; - + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); struct msm_gem_address_space *aspace = kms->base.aspace; struct dpu_hw_fmt_layout layout; @@ -1245,6 +1304,12 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) drm_mode_vrefresh(&crtc->mode), layout_valid ? &layout : NULL); + if (r_pipe->sspp) { + dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, + drm_mode_vrefresh(&crtc->mode), + layout_valid ? &layout : NULL); + } + if (pstate->needs_qos_remap) pstate->needs_qos_remap = false; @@ -1252,16 +1317,31 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) &crtc->mode, pipe_cfg); pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); + + if (r_pipe->sspp) { + pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg); + + pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg)); + } } static void _dpu_plane_atomic_disable(struct drm_plane *plane) { struct drm_plane_state *state = plane->state; struct dpu_plane_state *pstate = to_dpu_plane_state(state); + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; trace_dpu_plane_disable(DRMID(plane), false, pstate->pipe.multirect_mode); + if (r_pipe->sspp) { + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + if (r_pipe->sspp->ops.setup_multirect) + r_pipe->sspp->ops.setup_multirect(r_pipe); + } + pstate->pending = true; } @@ -1294,6 +1374,9 @@ static void dpu_plane_destroy(struct drm_plane *plane) pstate = to_dpu_plane_state(plane->state); _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, false, DPU_PLANE_QOS_PANIC_CTRL); + if (pstate->r_pipe.sspp) + _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, false, DPU_PLANE_QOS_PANIC_CTRL); + mutex_destroy(&pdpu->lock); /* this will destroy the states as well */ @@ -1374,12 +1457,29 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p, const struct drm_plane_state *state) { const struct dpu_plane_state *pstate = to_dpu_plane_state(state); + const struct dpu_sw_pipe *pipe = &pstate->pipe; + const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; + const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; + const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; drm_printf(p, "\tstage=%d\n", pstate->stage); - drm_printf(p, "\tsspp=%s\n", pstate->pipe.sspp->cap->name); - drm_printf(p, "\tmultirect_mode=%s\n", dpu_get_multirect_mode(pstate->pipe.multirect_mode)); - drm_printf(p, "\tmultirect_index=%s\n", - dpu_get_multirect_index(pstate->pipe.multirect_index)); + + drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); + drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode)); + drm_printf(p, "\tmultirect_index[0]=%s\n", + dpu_get_multirect_index(pipe->multirect_index)); + drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); + drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); + + if (r_pipe->sspp) { + drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name); + drm_printf(p, "\tmultirect_mode[1]=%s\n", + dpu_get_multirect_mode(r_pipe->multirect_mode)); + drm_printf(p, "\tmultirect_index[1]=%s\n", + dpu_get_multirect_index(r_pipe->multirect_index)); + drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect)); + drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect)); + } } static void dpu_plane_reset(struct drm_plane *plane) @@ -1413,6 +1513,10 @@ static void dpu_plane_reset(struct drm_plane *plane) * This is the place where the state is allocated, so fill it fully. */ pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; + pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + pstate->r_pipe.sspp = NULL; __drm_atomic_helper_plane_reset(plane, &pstate->base); } @@ -1429,6 +1533,8 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) pm_runtime_get_sync(&dpu_kms->pdev->dev); _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable, DPU_PLANE_QOS_PANIC_CTRL); + if (pstate->r_pipe.sspp) + _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable, DPU_PLANE_QOS_PANIC_CTRL); pm_runtime_put_sync(&dpu_kms->pdev->dev); } #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 0ca9002015ff..7490ffd94d03 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -19,7 +19,9 @@ * @base: base drm plane state object * @aspace: pointer to address space for input/output buffers * @pipe: software pipe description + * @r_pipe: software pipe description of the second pipe * @pipe_cfg: software pipe configuration + * @r_pipe_cfg: software pipe configuration for the second pipe * @stage: assigned by crtc blender * @needs_qos_remap: qos remap settings need to be updated * @multirect_index: index of the rectangle of SSPP @@ -34,7 +36,9 @@ struct dpu_plane_state { struct drm_plane_state base; struct msm_gem_address_space *aspace; struct dpu_sw_pipe pipe; + struct dpu_sw_pipe r_pipe; struct dpu_sw_pipe_cfg pipe_cfg; + struct dpu_sw_pipe_cfg r_pipe_cfg; enum dpu_stage stage; bool needs_qos_remap; bool pending; From 8b409996ebdce009777dfb17e542c06f749b02d5 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:49 +0300 Subject: [PATCH 33/42] drm/msm/dpu: populate SmartDMA features in hw catalog Downstream driver uses dpu->caps->smart_dma_rev to update sspp->cap->features with the bit corresponding to the supported SmartDMA version. Upstream driver does not do this, resulting in SSPP subdriver not enabling setup_multirect callback. Add corresponding SmartDMA SSPP feature bits to dpu hw catalog. Per Abhinav's request enable the SmartDMA features only on the platforms where the multirect was actually verified visually (sdm845 and sm8250). An (untested) enablement on the rest of the platforms comes in the next patch. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527362/ Link: https://lore.kernel.org/r/20230316161653.4106395-29-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 55 ++++++++++++------- 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 3da3d6223fa2..78844cff1c8a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -27,9 +27,15 @@ #define VIG_SDM845_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) +#define VIG_SDM845_MASK_SDMA \ + (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + #define VIG_SC7180_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) +#define VIG_SC7180_MASK_SDMA \ + (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) #define DMA_MSM8998_MASK \ @@ -40,6 +46,9 @@ #define VIG_SC7280_MASK \ (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION)) +#define VIG_SC7280_MASK_SDMA \ + (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + #define DMA_SDM845_MASK \ (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ @@ -48,6 +57,12 @@ #define DMA_CURSOR_SDM845_MASK \ (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) +#define DMA_SDM845_MASK_SDMA \ + (DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + +#define DMA_CURSOR_SDM845_MASK_SDMA \ + (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + #define DMA_CURSOR_MSM8998_MASK \ (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) @@ -1202,21 +1217,21 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { }; static const struct dpu_sspp_cfg sdm845_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK, + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK_SDMA, sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK, + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK_SDMA, sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK, + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK_SDMA, sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK, + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK_SDMA, sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK_SDMA, sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK_SDMA, sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK_SDMA, sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK_SDMA, sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), }; @@ -1257,21 +1272,21 @@ static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_cfg sm8250_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK_SDMA, sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK_SDMA, sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK_SDMA, sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK_SDMA, sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK_SDMA, sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK_SDMA, sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK_SDMA, sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK_SDMA, sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), }; @@ -1338,13 +1353,13 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { }; static const struct dpu_sspp_cfg sc7280_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK, + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK_SDMA, sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK_SDMA, sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK_SDMA, sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK_SDMA, sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), }; From dcb3f7c9042d1c1aa637b58d47bd45c00b2ac153 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Mar 2023 19:16:51 +0300 Subject: [PATCH 34/42] drm/msm/dpu: drop smart_dma_rev from dpu_caps The code doesn't use dpu_caps::smart_dma_rev field. It checks if the corresponding feature is enabled in the SSPP features. Drop the smart_dma_rev field completely. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527369/ Link: https://lore.kernel.org/r/20230316161653.4106395-31-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 13 ------------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- 2 files changed, 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 78844cff1c8a..6840b22a4159 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -323,7 +323,6 @@ static const struct dpu_caps msm8998_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V1, .ubwc_version = DPU_HW_UBWC_VER_10, .has_src_split = true, .has_dim_layer = true, @@ -338,7 +337,6 @@ static const struct dpu_caps msm8998_dpu_caps = { static const struct dpu_caps qcm2290_dpu_caps = { .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, .has_dim_layer = true, .has_idle_pc = true, .max_linewidth = 2160, @@ -349,7 +347,6 @@ static const struct dpu_caps sdm845_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_20, .has_src_split = true, .has_dim_layer = true, @@ -365,7 +362,6 @@ static const struct dpu_caps sc7180_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x9, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_20, .has_dim_layer = true, .has_idle_pc = true, @@ -377,7 +373,6 @@ static const struct dpu_caps sm6115_dpu_caps = { .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, .max_mixer_blendstages = 0x4, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_10, .has_dim_layer = true, .has_idle_pc = true, @@ -389,7 +384,6 @@ static const struct dpu_caps sm8150_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_30, .has_src_split = true, .has_dim_layer = true, @@ -405,7 +399,6 @@ static const struct dpu_caps sc8180x_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_30, .has_src_split = true, .has_dim_layer = true, @@ -421,7 +414,6 @@ static const struct dpu_caps sc8280xp_dpu_caps = { .max_mixer_width = 2560, .max_mixer_blendstages = 11, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, .has_dim_layer = true, @@ -435,7 +427,6 @@ static const struct dpu_caps sm8250_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, .has_dim_layer = true, @@ -449,7 +440,6 @@ static const struct dpu_caps sm8350_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, .has_dim_layer = true, @@ -463,7 +453,6 @@ static const struct dpu_caps sm8450_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, .has_dim_layer = true, @@ -477,7 +466,6 @@ static const struct dpu_caps sm8550_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ .ubwc_version = DPU_HW_UBWC_VER_40, .has_src_split = true, .has_dim_layer = true, @@ -491,7 +479,6 @@ static const struct dpu_caps sc7280_dpu_caps = { .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0x7, .qseed_type = DPU_SSPP_SCALER_QSEED4, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_30, .has_dim_layer = true, .has_idle_pc = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 63d7c6b15110..6b8fe0b7e467 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -399,7 +399,6 @@ struct dpu_rotation_cfg { * @max_mixer_blendstages max layer mixer blend stages or * supported z order * @qseed_type qseed2 or qseed3 support. - * @smart_dma_rev Supported version of SmartDMA feature. * @ubwc_version UBWC feature version (0x0 for not supported) * @has_src_split source split feature status * @has_dim_layer dim layer feature status @@ -414,7 +413,6 @@ struct dpu_caps { u32 max_mixer_width; u32 max_mixer_blendstages; u32 qseed_type; - u32 smart_dma_rev; u32 ubwc_version; bool has_src_split; bool has_dim_layer; From b7bb8967aa1249d682b1b99fae2891f3dfea53e6 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Thu, 16 Mar 2023 19:16:52 +0300 Subject: [PATCH 35/42] drm/msm/dpu: log the multirect_index in _dpu_crtc_blend_setup_pipe Lets print the multirect_index as well in _dpu_crtc_blend_setup_pipe() as it will give the complete information of the sw_pipe as well. Signed-off-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527350/ Link: https://lore.kernel.org/r/20230316161653.4106395-32-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index ffc87662ce0b..b6afb1cd711a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -426,12 +426,13 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, format->base.pixel_format, modifier); - DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", + DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n", crtc->base.id, stage, plane->base.id, sspp_idx - SSPP_NONE, - state->fb ? state->fb->base.id : -1); + state->fb ? state->fb->base.id : -1, + pipe->multirect_index); stage_cfg->stage[stage][stage_idx] = sspp_idx; stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index; From 27cfd5d7340e2ca49cb541fee3bdcc581c5359db Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Thu, 16 Mar 2023 19:16:53 +0300 Subject: [PATCH 36/42] drm/msm/dpu: remove unused dpu_plane_validate_multirect_v2 function After cleaning up the older multirect support the function dpu_plane_validate_multirect_v2() is unused. Lets remove it. Signed-off-by: Abhinav Kumar [DB: also drop struct dpu_multirect_plane_states and R0/R1/R_MAX] Signed-off-by: Dmitry Baryshkov Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/527348/ Link: https://lore.kernel.org/r/20230316161653.4106395-33-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 118 ---------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 17 ---- 2 files changed, 135 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 8fa4fafe7f17..14b5cfe30611 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -47,13 +47,6 @@ #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) #define DPU_ZPOS_MAX 255 -/* multirect rect index */ -enum { - R0, - R1, - R_MAX -}; - /* * Default Preload Values */ @@ -708,117 +701,6 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu, fill_color, fmt); } -int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) -{ - struct dpu_plane_state *pstate[R_MAX]; - const struct drm_plane_state *drm_state[R_MAX]; - struct drm_rect src[R_MAX], dst[R_MAX]; - struct dpu_plane *dpu_plane[R_MAX]; - const struct dpu_format *fmt[R_MAX]; - int i, buffer_lines; - unsigned int max_tile_height = 1; - bool parallel_fetch_qualified = true; - bool has_tiled_rect = false; - - for (i = 0; i < R_MAX; i++) { - const struct msm_format *msm_fmt; - - drm_state[i] = i ? plane->r1 : plane->r0; - msm_fmt = msm_framebuffer_format(drm_state[i]->fb); - fmt[i] = to_dpu_format(msm_fmt); - - if (DPU_FORMAT_IS_UBWC(fmt[i])) { - has_tiled_rect = true; - if (fmt[i]->tile_height > max_tile_height) - max_tile_height = fmt[i]->tile_height; - } - } - - for (i = 0; i < R_MAX; i++) { - int width_threshold; - - pstate[i] = to_dpu_plane_state(drm_state[i]); - dpu_plane[i] = to_dpu_plane(drm_state[i]->plane); - - if (pstate[i] == NULL) { - DPU_ERROR("DPU plane state of plane id %d is NULL\n", - drm_state[i]->plane->base.id); - return -EINVAL; - } - - src[i].x1 = drm_state[i]->src_x >> 16; - src[i].y1 = drm_state[i]->src_y >> 16; - src[i].x2 = src[i].x1 + (drm_state[i]->src_w >> 16); - src[i].y2 = src[i].y1 + (drm_state[i]->src_h >> 16); - - dst[i] = drm_plane_state_dest(drm_state[i]); - - if (drm_rect_calc_hscale(&src[i], &dst[i], 1, 1) != 1 || - drm_rect_calc_vscale(&src[i], &dst[i], 1, 1) != 1) { - DPU_ERROR_PLANE(dpu_plane[i], - "scaling is not supported in multirect mode\n"); - return -EINVAL; - } - - if (DPU_FORMAT_IS_YUV(fmt[i])) { - DPU_ERROR_PLANE(dpu_plane[i], - "Unsupported format for multirect mode\n"); - return -EINVAL; - } - - /** - * SSPP PD_MEM is split half - one for each RECT. - * Tiled formats need 5 lines of buffering while fetching - * whereas linear formats need only 2 lines. - * So we cannot support more than half of the supported SSPP - * width for tiled formats. - */ - width_threshold = dpu_plane[i]->catalog->caps->max_linewidth; - if (has_tiled_rect) - width_threshold /= 2; - - if (parallel_fetch_qualified && - drm_rect_width(&src[i]) > width_threshold) - parallel_fetch_qualified = false; - - } - - /* Validate RECT's and set the mode */ - - /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */ - if (parallel_fetch_qualified) { - pstate[R0]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - pstate[R1]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - - goto done; - } - - /* TIME_MX Mode */ - buffer_lines = 2 * max_tile_height; - - if (dst[R1].y1 >= dst[R0].y2 + buffer_lines || - dst[R0].y1 >= dst[R1].y2 + buffer_lines) { - pstate[R0]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; - pstate[R1]->pipe.multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; - } else { - DPU_ERROR( - "No multirect mode possible for the planes (%d - %d)\n", - drm_state[R0]->plane->base.id, - drm_state[R1]->plane->base.id); - return -EINVAL; - } - -done: - pstate[R0]->pipe.multirect_index = DPU_SSPP_RECT_0; - pstate[R1]->pipe.multirect_index = DPU_SSPP_RECT_1; - - DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", - pstate[R0]->pipe.multirect_mode, pstate[R0]->pipe.multirect_index); - DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n", - pstate[R1]->pipe.multirect_mode, pstate[R1]->pipe.multirect_index); - return 0; -} - static int dpu_plane_prepare_fb(struct drm_plane *plane, struct drm_plane_state *new_state) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 7490ffd94d03..abd6b21a049b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -50,16 +50,6 @@ struct dpu_plane_state { unsigned int rotation; }; -/** - * struct dpu_multirect_plane_states: Defines multirect pair of drm plane states - * @r0: drm plane configured on rect 0 - * @r1: drm plane configured on rect 1 - */ -struct dpu_multirect_plane_states { - const struct drm_plane_state *r0; - const struct drm_plane_state *r1; -}; - #define to_dpu_plane_state(x) \ container_of(x, struct dpu_plane_state, base) @@ -87,13 +77,6 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, uint32_t pipe, enum drm_plane_type type, unsigned long possible_crtcs); -/** - * dpu_plane_validate_multirecti_v2 - validate the multirect planes - * against hw limitations - * @plane: drm plate states of the multirect pair - */ -int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane); - /** * dpu_plane_color_fill - enables color fill on plane * @plane: Pointer to DRM plane object From 4760be481dc075cd13f95f4650f5d5b53b4b336d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 6 Mar 2023 10:06:33 +0100 Subject: [PATCH 37/42] drm/msm/dpu: Fix bit-shifting UB in DPU_HW_VER() macro With gcc-5 and CONFIG_UBSAN_SHIFT=y: drivers/gpu/drm/msm/msm_mdss.c: In function 'msm_mdss_enable': drivers/gpu/drm/msm/msm_mdss.c:296:2: error: case label does not reduce to an integer constant case DPU_HW_VER_800: ^ drivers/gpu/drm/msm/msm_mdss.c:299:2: error: case label does not reduce to an integer constant case DPU_HW_VER_810: ^ drivers/gpu/drm/msm/msm_mdss.c:300:2: error: case label does not reduce to an integer constant case DPU_HW_VER_900: ^ This happens because for major revisions 8 or greather, the non-sign bit of the major revision number is shifted into bit 31 of a signed integer, which is undefined behavior. Fix this by casting the major revision number to unsigned int. Fixes: efcd0107727c4f04 ("drm/msm/dpu: add support for SM8550") Fixes: 4a352c2fc15aec1e ("drm/msm/dpu: Introduce SC8280XP") Fixes: 100d7ef6995d1f86 ("drm/msm/dpu: add support for SM8450") Signed-off-by: Geert Uytterhoeven Reviewed-by: Randy Dunlap Reviewed-by: Rob Clark Patchwork: https://patchwork.freedesktop.org/patch/525152/ Link: https://lore.kernel.org/r/20230306090633.65918-1-geert+renesas@glider.be Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 6b8fe0b7e467..2f532543848c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -19,8 +19,9 @@ */ #define MAX_BLOCKS 12 -#define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ - ((MINOR & 0xFFF) << 16) |\ +#define DPU_HW_VER(MAJOR, MINOR, STEP) \ + ((((unsigned int)MAJOR & 0xF) << 28) | \ + ((MINOR & 0xFFF) << 16) | \ (STEP & 0xFFFF)) #define DPU_HW_MAJOR(rev) ((rev) >> 28) From 8aa22aaa1fc316b93a39209299227d5f78434828 Mon Sep 17 00:00:00 2001 From: Kalyan Thota Date: Mon, 13 Feb 2023 03:11:42 -0800 Subject: [PATCH 38/42] drm/msm/dpu: add DSPPs into reservation upon a CTM request Add DSPP blocks into the topology for reservation, if there is a CTM request for that composition. Signed-off-by: Kalyan Thota Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/522445/ Link: https://lore.kernel.org/r/1676286704-818-3-git-send-email-quic_kalyant@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index e4744565bb47..6a6df8a2e15f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -545,7 +545,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) static struct msm_display_topology dpu_encoder_get_topology( struct dpu_encoder_virt *dpu_enc, struct dpu_kms *dpu_kms, - struct drm_display_mode *mode) + struct drm_display_mode *mode, + struct drm_crtc_state *crtc_state) { struct msm_display_topology topology = {0}; int i, intf_count = 0; @@ -563,8 +564,7 @@ static struct msm_display_topology dpu_encoder_get_topology( * 1 LM, 1 INTF * 2 LM, 1 INTF (stream merge to support high resolution interfaces) * - * Adding color blocks only to primary interface if available in - * sufficient number + * Add dspps to the reservation requirements if ctm is requested */ if (intf_count == 2) topology.num_lm = 2; @@ -573,11 +573,8 @@ static struct msm_display_topology dpu_encoder_get_topology( else topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; - if (dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_DSI) { - if (dpu_kms->catalog->dspp && - (dpu_kms->catalog->dspp_count >= topology.num_lm)) - topology.num_dspp = topology.num_lm; - } + if (crtc_state->ctm) + topology.num_dspp = topology.num_lm; topology.num_intf = intf_count; @@ -642,7 +639,7 @@ static int dpu_encoder_virt_atomic_check( } } - topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode); + topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state); /* Reserve dynamic resources now. */ if (!ret) { From f4eddf1d78744d9e4d1664236ad6c9b76be9a877 Mon Sep 17 00:00:00 2001 From: Kalyan Thota Date: Mon, 13 Feb 2023 03:11:43 -0800 Subject: [PATCH 39/42] drm/msm/dpu: avoid unnecessary check in DPU reservations Return immediately on failure, this will make dpu reservations part look cleaner. Signed-off-by: Kalyan Thota Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/522442/ Link: https://lore.kernel.org/r/1676286704-818-4-git-send-email-quic_kalyant@quicinc.com [DB: fixed merge conflict with b6975693846b, retain those changes] Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 23 +++++++++------------ 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 6a6df8a2e15f..1dc5dbe58572 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -635,25 +635,22 @@ static int dpu_encoder_virt_atomic_check( if (ret) { DPU_ERROR_ENC(dpu_enc, "mode unsupported, phys idx %d\n", i); - break; + return ret; } } topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state); - /* Reserve dynamic resources now. */ - if (!ret) { - /* - * Release and Allocate resources on every modeset - * Dont allocate when active is false. - */ - if (drm_atomic_crtc_needs_modeset(crtc_state)) { - dpu_rm_release(global_state, drm_enc); + /* + * Release and Allocate resources on every modeset + * Dont allocate when active is false. + */ + if (drm_atomic_crtc_needs_modeset(crtc_state)) { + dpu_rm_release(global_state, drm_enc); - if (!crtc_state->active_changed || crtc_state->enable) - ret = dpu_rm_reserve(&dpu_kms->rm, global_state, - drm_enc, crtc_state, topology); - } + if (!crtc_state->active_changed || crtc_state->enable) + ret = dpu_rm_reserve(&dpu_kms->rm, global_state, + drm_enc, crtc_state, topology); } trace_dpu_enc_atomic_check_flags(DRMID(drm_enc), adj_mode->flags); From 82836692d5d7424660f8fb5f52432cfe2d9e633c Mon Sep 17 00:00:00 2001 From: Kalyan Thota Date: Mon, 13 Feb 2023 03:11:44 -0800 Subject: [PATCH 40/42] drm/msm/dpu: manage DPU resources if CTM is requested Allow modeset to be triggered during CTM enable/disable. In the modeset callbacks, DPU resources required for the CTM feature are managed appropriately. Signed-off-by: Kalyan Thota Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/522448/ Link: https://lore.kernel.org/r/1676286704-818-5-git-send-email-quic_kalyant@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_atomic.c | 18 ++++++++++++++++++ drivers/gpu/drm/msm/msm_drv.c | 2 +- drivers/gpu/drm/msm/msm_drv.h | 1 + 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index 608a969efea2..d77fa9793c54 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -179,6 +179,24 @@ static unsigned get_crtc_mask(struct drm_atomic_state *state) return mask; } +int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) +{ + struct drm_crtc_state *old_crtc_state, *new_crtc_state; + struct drm_crtc *crtc; + int i; + + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + if ((old_crtc_state->ctm && !new_crtc_state->ctm) || + (!old_crtc_state->ctm && new_crtc_state->ctm)) { + new_crtc_state->mode_changed = true; + state->allow_modeset = true; + } + } + + return drm_atomic_helper_check(dev, state); +} + void msm_atomic_commit_tail(struct drm_atomic_state *state) { struct drm_device *dev = state->dev; diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 9b6f17b1261f..ecf42f40f289 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -55,7 +55,7 @@ static const struct drm_mode_config_funcs mode_config_funcs = { .fb_create = msm_framebuffer_create, .output_poll_changed = drm_fb_helper_output_poll_changed, - .atomic_check = drm_atomic_helper_check, + .atomic_check = msm_atomic_check, .atomic_commit = drm_atomic_helper_commit, }; diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 9f0c184b02a0..aefee23adea1 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -261,6 +261,7 @@ int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, struct msm_kms *kms, int crtc_idx); void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); void msm_atomic_commit_tail(struct drm_atomic_state *state); +int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); void msm_atomic_state_clear(struct drm_atomic_state *state); void msm_atomic_state_free(struct drm_atomic_state *state); From 501bd8dea55d641422d2a06b94f7276f21f7be21 Mon Sep 17 00:00:00 2001 From: Vinod Polimera Date: Fri, 31 Mar 2023 19:28:32 +0530 Subject: [PATCH 41/42] drm/msm/dpu: set dirty_fb flag while in self refresh mode While in virtual terminal mode with PSR enabled, there will be no atomic commits triggered without dirty_fb being set. This will create a notion of no screen update. Allow atomic commit when dirty_fb ioctl is issued, so that it can trigger a PSR exit and shows update on the screen. Reported-by: Bjorn Andersson Link: https://lore.kernel.org/all/20230326162723.3lo6pnsfdwzsvbhj@ripper/ Signed-off-by: Vinod Polimera Reviewed-by: Dmitry Baryshkov Tested-by: Douglas Anderson Patchwork: https://patchwork.freedesktop.org/patch/530206/ Link: https://lore.kernel.org/r/1680271114-1534-2-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index b6afb1cd711a..bdafbbd40967 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1167,6 +1167,9 @@ static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate) struct drm_crtc *crtc = cstate->crtc; struct drm_encoder *encoder; + if (cstate->self_refresh_active) + return true; + drm_for_each_encoder_mask (encoder, crtc->dev, cstate->encoder_mask) { if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_CMD) { return true; From c6c6556857e229c8c117c3b7aaee33b6f5d03c57 Mon Sep 17 00:00:00 2001 From: Vinod Polimera Date: Fri, 31 Mar 2023 19:28:33 +0530 Subject: [PATCH 42/42] msm/disp/dpu: allow atomic_check in PSR usecase Certain flags like dirty_fb will be updated into the plane state during crtc atomic_check. Allow those updates during PSR commit. Reported-by: Bjorn Andersson Link: https://lore.kernel.org/all/20230326162723.3lo6pnsfdwzsvbhj@ripper/ Signed-off-by: Vinod Polimera Reviewed-by: Dmitry Baryshkov Tested-by: Douglas Anderson Patchwork: https://patchwork.freedesktop.org/patch/530208/ Link: https://lore.kernel.org/r/1680271114-1534-3-git-send-email-quic_vpolimer@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index bdafbbd40967..cc66ddffe672 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1194,7 +1194,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state); - if (!crtc_state->enable || !crtc_state->active) { + if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state)) { DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", crtc->base.id, crtc_state->enable, crtc_state->active);