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drm/i915: add INTEL_NUM_PIPES() and use it
Abstract away direct access to ->num_pipes to allow further refactoring. No functional changes. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190911092608.13009-1-jani.nikula@intel.com
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parent
023a125d1d
commit
249778704c
6 changed files with 16 additions and 14 deletions
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@ -7190,7 +7190,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
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}
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}
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if (INTEL_INFO(dev_priv)->num_pipes == 2)
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if (INTEL_NUM_PIPES(dev_priv) == 2)
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return 0;
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/* Ivybridge 3 pipe is really complicated */
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@ -9574,7 +9574,7 @@ static void ironlake_compute_dpll(struct intel_crtc *crtc,
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* clear if it''s a win or loss power wise. No point in doing
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* this on ILK at all since it has a fixed DPLL<->pipe mapping.
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*/
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if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
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if (INTEL_NUM_PIPES(dev_priv) == 3 &&
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intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
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dpll |= DPLL_SDVO_HIGH_SPEED;
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@ -13899,7 +13899,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
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if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
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entries,
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INTEL_INFO(dev_priv)->num_pipes, i))
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INTEL_NUM_PIPES(dev_priv), i))
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continue;
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updated |= cmask;
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@ -16258,8 +16258,8 @@ int intel_modeset_init(struct drm_device *dev)
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}
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DRM_DEBUG_KMS("%d display pipe%s available.\n",
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INTEL_INFO(dev_priv)->num_pipes,
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INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
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INTEL_NUM_PIPES(dev_priv),
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INTEL_NUM_PIPES(dev_priv) > 1 ? "s" : "");
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for_each_pipe(dev_priv, pipe) {
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ret = intel_crtc_init(dev_priv, pipe);
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@ -17352,7 +17352,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
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if (!error)
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return;
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err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
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err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv));
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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err_printf(m, "PWR_WELL_CTL2: %08x\n",
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error->power_well_driver);
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@ -307,10 +307,10 @@ enum phy_fia {
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};
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#define for_each_pipe(__dev_priv, __p) \
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for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
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for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
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for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) \
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for_each_if((__mask) & BIT(__p))
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#define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
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@ -114,7 +114,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
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pinfo.size_data = sizeof(*pdata);
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pinfo.dma_mask = DMA_BIT_MASK(32);
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pdata->num_pipes = INTEL_INFO(dev_priv)->num_pipes;
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pdata->num_pipes = INTEL_NUM_PIPES(dev_priv);
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pdata->num_ports = IS_CHERRYVIEW(dev_priv) ? 3 : 2; /* B,C,D or B,C */
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pdata->port[0].pipe = -1;
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pdata->port[1].pipe = -1;
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@ -340,7 +340,7 @@ static int i915_driver_modeset_probe(struct drm_device *dev)
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if (HAS_DISPLAY(dev_priv)) {
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ret = drm_vblank_init(&dev_priv->drm,
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INTEL_INFO(dev_priv)->num_pipes);
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INTEL_NUM_PIPES(dev_priv));
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if (ret)
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goto out;
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}
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@ -2188,7 +2188,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define GT_FREQUENCY_MULTIPLIER 50
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#define GEN9_FREQ_SCALER 3
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#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->num_pipes > 0)
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#define INTEL_NUM_PIPES(dev_priv) (INTEL_INFO(dev_priv)->num_pipes)
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#define HAS_DISPLAY(dev_priv) (INTEL_NUM_PIPES(dev_priv) > 0)
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static inline bool intel_vtd_active(void)
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{
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@ -1909,7 +1909,7 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
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for (level = 0; level < wm_state->num_levels; level++) {
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const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
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const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
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const int sr_fifo_size = INTEL_NUM_PIPES(dev_priv) * 512 - 1;
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if (!vlv_raw_crtc_wm_is_valid(crtc_state, level))
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break;
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@ -2648,7 +2648,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
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/* HSW allows LP1+ watermarks even with multiple pipes */
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if (level == 0 || config->num_pipes_active > 1) {
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fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
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fifo_size /= INTEL_NUM_PIPES(dev_priv);
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/*
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* For some reason the non self refresh
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@ -9733,7 +9733,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
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dev_priv->display.update_wm = i9xx_update_wm;
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dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
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} else if (IS_GEN(dev_priv, 2)) {
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if (INTEL_INFO(dev_priv)->num_pipes == 1) {
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if (INTEL_NUM_PIPES(dev_priv) == 1) {
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dev_priv->display.update_wm = i845_update_wm;
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dev_priv->display.get_fifo_size = i845_get_fifo_size;
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} else {
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