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MIPS: Loongson64: DeviceTree for LS7A PCH
Add DeviceTree files for Classic Loongson64 Quad Core + LS7A boards and Generic Loongson64 Quad Core + LS7A boards. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Tested-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Jiaxun Yang
Thomas Bogendoerfer
parent
a6aa35e30a
commit
24af105962
6 changed files with 512 additions and 1 deletions
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@ -1,4 +1,7 @@
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# SPDX_License_Identifier: GPL_2.0
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dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb loongson64c_8core_rs780e.dtb
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dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_ls7a.dtb
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dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb
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dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb
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dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb
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obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
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37
arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
Normal file
37
arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
Normal file
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@ -0,0 +1,37 @@
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include "loongson64c-package.dtsi"
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#include "ls7a-pch.dtsi"
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/ {
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compatible = "loongson,loongson64c-4core-ls7a";
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};
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&package0 {
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htvec: interrupt-controller@efdfb000080 {
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compatible = "loongson,htvec-1.0";
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reg = <0xefd 0xfb000080 0x40>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&liointc>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
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<25 IRQ_TYPE_LEVEL_HIGH>,
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<26 IRQ_TYPE_LEVEL_HIGH>,
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<27 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&pch {
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msi: msi-controller@2ff00000 {
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compatible = "loongson,pch-msi-1.0";
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reg = <0 0x2ff00000 0 0x8>;
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interrupt-controller;
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msi-controller;
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loongson,msi-base-vec = <64>;
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loongson,msi-num-vecs = <64>;
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interrupt-parent = <&htvec>;
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};
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};
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61
arch/mips/boot/dts/loongson/loongson64g-package.dtsi
Normal file
61
arch/mips/boot/dts/loongson/loongson64g-package.dtsi
Normal file
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@ -0,0 +1,61 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpuintc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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package0: bus@1fe00000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
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0 0x3ff00000 0 0x3ff00000 0x100000
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0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
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liointc: interrupt-controller@3ff01400 {
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compatible = "loongson,liointc-1.0";
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reg = <0 0x3ff01400 0x64>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>, <3>;
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interrupt-names = "int0", "int1";
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loongson,parent_int_map = <0x00ffffff>, /* int0 */
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<0xff000000>, /* int1 */
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<0x00000000>, /* int2 */
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<0x00000000>; /* int3 */
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};
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cpu_uart0: serial@1fe001e0 {
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compatible = "ns16550a";
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reg = <0 0x1fe00100 0x10>;
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clock-frequency = <100000000>;
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interrupt-parent = <&liointc>;
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interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
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no-loopback-test;
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};
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cpu_uart1: serial@1fe001e8 {
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status = "disabled";
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compatible = "ns16550a";
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reg = <0 0x1fe00110 0x10>;
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clock-frequency = <100000000>;
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interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&liointc>;
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no-loopback-test;
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};
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};
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};
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37
arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
Normal file
37
arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
Normal file
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@ -0,0 +1,37 @@
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// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include "loongson64g-package.dtsi"
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#include "ls7a-pch.dtsi"
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/ {
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compatible = "loongson,loongson64g-4core-ls7a";
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};
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&package0 {
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htvec: interrupt-controller@efdfb000080 {
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compatible = "loongson,htvec-1.0";
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reg = <0xefd 0xfb000080 0x40>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&liointc>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
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<25 IRQ_TYPE_LEVEL_HIGH>,
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<26 IRQ_TYPE_LEVEL_HIGH>,
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<27 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&pch {
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msi: msi-controller@2ff00000 {
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compatible = "loongson,pch-msi-1.0";
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reg = <0 0x2ff00000 0 0x8>;
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interrupt-controller;
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msi-controller;
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loongson,msi-base-vec = <64>;
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loongson,msi-num-vecs = <128>;
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interrupt-parent = <&htvec>;
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};
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};
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371
arch/mips/boot/dts/loongson/ls7a-pch.dtsi
Normal file
371
arch/mips/boot/dts/loongson/ls7a-pch.dtsi
Normal file
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@ -0,0 +1,371 @@
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// SPDX-License-Identifier: GPL-2.0
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/ {
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pch: bus@10000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
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0 0x20000000 0 0x20000000 0 0x10000000
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0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
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0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
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pic: interrupt-controller@10000000 {
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compatible = "loongson,pch-pic-1.0";
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reg = <0 0x10000000 0 0x400>;
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interrupt-controller;
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interrupt-parent = <&htvec>;
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loongson,pic-base-vec = <0>;
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#interrupt-cells = <2>;
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};
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pci@1a000000 {
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compatible = "loongson,ls7a-pci";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <2>;
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msi-parent = <&msi>;
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reg = <0 0x1a000000 0 0x02000000>,
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<0xefe 0x00000000 0 0x20000000>;
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ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
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<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
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ohci@4,0 {
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compatible = "pci0014,7a24.0",
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"pci0014,7a24",
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"pciclass0c0310",
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"pciclass0c03";
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reg = <0x2000 0x0 0x0 0x0 0x0>;
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interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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};
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ehci@4,1 {
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compatible = "pci0014,7a14.0",
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"pci0014,7a14",
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"pciclass0c0320",
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"pciclass0c03";
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reg = <0x2100 0x0 0x0 0x0 0x0>;
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interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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};
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ohci@5,0 {
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compatible = "pci0014,7a24.0",
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"pci0014,7a24",
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"pciclass0c0310",
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"pciclass0c03";
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reg = <0x2800 0x0 0x0 0x0 0x0>;
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interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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};
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ehci@5,1 {
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compatible = "pci0014,7a14.0",
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"pci0014,7a14",
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"pciclass0c0320",
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"pciclass0c03";
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reg = <0x2900 0x0 0x0 0x0 0x0>;
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interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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};
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sata@8,0 {
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compatible = "pci0014,7a08.0",
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"pci0014,7a08",
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"pciclass010601",
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"pciclass0106";
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reg = <0x4000 0x0 0x0 0x0 0x0>;
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interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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};
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sata@8,1 {
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compatible = "pci0014,7a08.0",
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"pci0014,7a08",
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"pciclass010601",
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"pciclass0106";
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reg = <0x4100 0x0 0x0 0x0 0x0>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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};
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sata@8,2 {
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compatible = "pci0014,7a08.0",
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"pci0014,7a08",
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"pciclass010601",
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"pciclass0106";
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reg = <0x4200 0x0 0x0 0x0 0x0>;
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interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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};
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gpu@6,0 {
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compatible = "pci0014,7a15.0",
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"pci0014,7a15",
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"pciclass030200",
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"pciclass0302";
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reg = <0x3000 0x0 0x0 0x0 0x0>;
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interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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};
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dc@6,1 {
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compatible = "pci0014,7a06.0",
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"pci0014,7a06",
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"pciclass030000",
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"pciclass0300";
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reg = <0x3100 0x0 0x0 0x0 0x0>;
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interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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};
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hda@7,0 {
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compatible = "pci0014,7a07.0",
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"pci0014,7a07",
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"pciclass040300",
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"pciclass0403";
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reg = <0x3800 0x0 0x0 0x0 0x0>;
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interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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};
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gmac@3,0 {
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compatible = "pci0014,7a03.0",
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"pci0014,7a03",
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"pciclass020000",
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"pciclass0200";
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reg = <0x1800 0x0 0x0 0x0 0x0>;
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interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
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<13 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq", "eth_lpi";
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interrupt-parent = <&pic>;
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phy-mode = "rgmii";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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gmac@3,1 {
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compatible = "pci0014,7a03.0",
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"pci0014,7a03",
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"pciclass020000",
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"pciclass0200";
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reg = <0x1900 0x0 0x0 0x0 0x0>;
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interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
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<15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq", "eth_lpi";
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interrupt-parent = <&pic>;
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phy-mode = "rgmii";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy1: ethernet-phy@1 {
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reg = <0>;
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};
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};
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};
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pci_bridge@9,0 {
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compatible = "pci0014,7a19.1",
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"pci0014,7a19",
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"pciclass060400",
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"pciclass0604";
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reg = <0x4800 0x0 0x0 0x0 0x0>;
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interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
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};
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pci_bridge@a,0 {
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compatible = "pci0014,7a09.1",
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"pci0014,7a09",
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"pciclass060400",
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"pciclass0604";
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reg = <0x5000 0x0 0x0 0x0 0x0>;
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interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
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};
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pci_bridge@b,0 {
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compatible = "pci0014,7a09.1",
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"pci0014,7a09",
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"pciclass060400",
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"pciclass0604";
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reg = <0x5800 0x0 0x0 0x0 0x0>;
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interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
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};
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pci_bridge@c,0 {
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compatible = "pci0014,7a09.1",
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"pci0014,7a09",
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"pciclass060400",
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"pciclass0604";
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reg = <0x6000 0x0 0x0 0x0 0x0>;
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interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
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};
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pci_bridge@d,0 {
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compatible = "pci0014,7a19.1",
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"pci0014,7a19",
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"pciclass060400",
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"pciclass0604";
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reg = <0x6800 0x0 0x0 0x0 0x0>;
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interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
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};
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pci_bridge@e,0 {
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compatible = "pci0014,7a09.1",
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"pci0014,7a09",
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"pciclass060400",
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"pciclass0604";
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reg = <0x7000 0x0 0x0 0x0 0x0>;
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interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
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};
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pci_bridge@f,0 {
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compatible = "pci0014,7a29.1",
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"pci0014,7a29",
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"pciclass060400",
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"pciclass0604";
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reg = <0x7800 0x0 0x0 0x0 0x0>;
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interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&pic>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
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};
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pci_bridge@10,0 {
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compatible = "pci0014,7a19.1",
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||||
"pci0014,7a19",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x8000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@11,0 {
|
||||
compatible = "pci0014,7a29.1",
|
||||
"pci0014,7a29",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x8800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@12,0 {
|
||||
compatible = "pci0014,7a19.1",
|
||||
"pci0014,7a19",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x9000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@13,0 {
|
||||
compatible = "pci0014,7a29.1",
|
||||
"pci0014,7a29",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x9800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@14,0 {
|
||||
compatible = "pci0014,7a19.1",
|
||||
"pci0014,7a19",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0xa000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -8,6 +8,8 @@
|
|||
#ifndef __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
|
||||
#define __ASM_MACH_LOONGSON64_BUILTIN_DTBS_H_
|
||||
|
||||
extern u32 __dtb_loongson64c_4core_ls7a_begin[];
|
||||
extern u32 __dtb_loongson64c_4core_rs780e_begin[];
|
||||
extern u32 __dtb_loongson64c_8core_rs780e_begin[];
|
||||
extern u32 __dtb_loongson64g_4core_ls7a_begin[];
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue