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i2c: designware: Fix spelling typos in the comments
Fix spelling typos in the comments with help of `codespell`. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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5 changed files with 8 additions and 8 deletions
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel BayTrail PMIC I2C bus semaphore implementaion
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* Intel BayTrail PMIC I2C bus semaphore implementation
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* Copyright (c) 2014, Intel Corporation.
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*/
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#include <linux/device.h>
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@ -102,7 +102,7 @@ int i2c_dw_set_reg_access(struct dw_i2c_dev *dev)
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i2c_dw_release_lock(dev);
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if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
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/* Configure register endianess access */
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/* Configure register endianness access */
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dev->flags |= ACCESS_SWAP;
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} else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
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/* Configure register access mode 16bit */
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@ -190,10 +190,10 @@ int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)
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/*
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* Workaround for avoiding TX arbitration lost in case I2C
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* slave pulls SDA down "too quickly" after falling egde of
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* slave pulls SDA down "too quickly" after falling edge of
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* SCL by enabling non-zero SDA RX hold. Specification says it
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* extends incoming SDA low to high transition while SCL is
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* high but it apprears to help also above issue.
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* high but it appears to help also above issue.
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*/
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if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
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dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
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@ -378,7 +378,7 @@ void i2c_dw_disable(struct dw_i2c_dev *dev)
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/* Disable controller */
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__i2c_dw_disable(dev);
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/* Disable all interupts */
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/* Disable all interrupts */
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dw_writel(dev, 0, DW_IC_INTR_MASK);
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dw_readl(dev, DW_IC_CLR_INTR);
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}
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@ -521,7 +521,7 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
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/*
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* The IC_INTR_STAT register just indicates "enabled" interrupts.
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* Ths unmasked raw version of interrupt status bits are available
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* The unmasked raw version of interrupt status bits is available
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* in the IC_RAW_INTR_STAT register.
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*
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* That is,
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@ -109,7 +109,7 @@ static int mfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
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static int mrfld_setup(struct pci_dev *pdev, struct dw_pci_controller *c)
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{
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/*
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* On Intel Merrifield the user visible i2c busses are enumerated
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* On Intel Merrifield the user visible i2c buses are enumerated
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* [1..7]. So, we add 1 to shift the default range. Besides that the
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* first PCI slot provides 4 functions, that's why we have to add 0 to
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* the first slot and 4 to the next one.
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@ -107,7 +107,7 @@ static u32 i2c_dw_read_clear_intrbits_slave(struct dw_i2c_dev *dev)
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/*
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* The IC_INTR_STAT register just indicates "enabled" interrupts.
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* Ths unmasked raw version of interrupt status bits are available
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* The unmasked raw version of interrupt status bits is available
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* in the IC_RAW_INTR_STAT register.
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*
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* That is,
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