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ptp: clockmatrix: reset device and check BOOT_STATUS
SM_RESET device only when loading full configuration and check for BOOT_STATUS. Also remove polling for write trigger done in _idtcm_settime(). Changes since v1: -Correct warnings from strict checkpatch Signed-off-by: Min Li <min.li.xe@renesas.com> Acked-by: Richard Cochran <richardcochran@gmail.com> Link: https://lore.kernel.org/r/1607442117-13661-1-git-send-email-min.li.xe@renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Min Li
Jakub Kicinski
parent
9125abe7b9
commit
251f4fe224
3 changed files with 124 additions and 36 deletions
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@ -103,6 +103,7 @@
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#define SM_RESET_CMD 0x5A
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#define GENERAL_STATUS 0xc014
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#define BOOT_STATUS 0x0000
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#define HW_REV_ID 0x000A
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#define BOND_ID 0x000B
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#define HW_CSR_ID 0x000C
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@ -33,6 +33,43 @@ module_param(firmware, charp, 0);
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#define SETTIME_CORRECTION (0)
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static int contains_full_configuration(const struct firmware *fw)
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{
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s32 full_count = FULL_FW_CFG_BYTES - FULL_FW_CFG_SKIPPED_BYTES;
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struct idtcm_fwrc *rec = (struct idtcm_fwrc *)fw->data;
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s32 count = 0;
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u16 regaddr;
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u8 loaddr;
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s32 len;
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/* If the firmware contains 'full configuration' SM_RESET can be used
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* to ensure proper configuration.
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*
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* Full configuration is defined as the number of programmable
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* bytes within the configuration range minus page offset addr range.
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*/
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for (len = fw->size; len > 0; len -= sizeof(*rec)) {
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regaddr = rec->hiaddr << 8;
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regaddr |= rec->loaddr;
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loaddr = rec->loaddr;
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rec++;
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/* Top (status registers) and bottom are read-only */
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if (regaddr < GPIO_USER_CONTROL || regaddr >= SCRATCH)
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continue;
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/* Page size 128, last 4 bytes of page skipped */
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if ((loaddr > 0x7b && loaddr <= 0x7f) || loaddr > 0xfb)
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continue;
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count++;
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}
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return (count >= full_count);
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}
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static long set_write_phase_ready(struct ptp_clock_info *ptp)
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{
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struct idtcm_channel *channel =
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@ -261,6 +298,53 @@ static int idtcm_write(struct idtcm *idtcm,
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return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true);
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}
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static int clear_boot_status(struct idtcm *idtcm)
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{
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int err;
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u8 buf[4] = {0};
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err = idtcm_write(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
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return err;
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}
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static int read_boot_status(struct idtcm *idtcm, u32 *status)
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{
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int err;
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u8 buf[4] = {0};
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err = idtcm_read(idtcm, GENERAL_STATUS, BOOT_STATUS, buf, sizeof(buf));
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*status = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
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return err;
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}
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static int wait_for_boot_status_ready(struct idtcm *idtcm)
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{
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u32 status = 0;
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u8 i = 30; /* 30 * 100ms = 3s */
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int err;
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do {
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err = read_boot_status(idtcm, &status);
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if (err)
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return err;
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if (status == 0xA0)
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return 0;
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msleep(100);
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i--;
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} while (i);
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dev_warn(&idtcm->client->dev, "%s timed out\n", __func__);
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return -EBUSY;
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}
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static int _idtcm_gettime(struct idtcm_channel *channel,
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struct timespec64 *ts)
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{
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@ -670,7 +754,7 @@ static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
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if (err)
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return err;
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if (cmd == 0)
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if ((cmd & TOD_WRITE_SELECTION_MASK) == 0)
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break;
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if (++count > 20) {
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@ -684,39 +768,16 @@ static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
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}
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static int _idtcm_settime(struct idtcm_channel *channel,
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struct timespec64 const *ts,
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enum hw_tod_write_trig_sel wr_trig)
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struct timespec64 const *ts)
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{
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struct idtcm *idtcm = channel->idtcm;
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int err;
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int i;
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u8 trig_sel;
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err = _idtcm_set_dpll_hw_tod(channel, ts, wr_trig);
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if (err)
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return err;
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/* Wait for the operation to complete. */
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for (i = 0; i < 10000; i++) {
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err = idtcm_read(idtcm, channel->hw_dpll_n,
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HW_DPLL_TOD_CTRL_1, &trig_sel,
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sizeof(trig_sel));
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if (err)
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return err;
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if (trig_sel == 0x4a)
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break;
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err = 1;
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}
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err = _idtcm_set_dpll_hw_tod(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
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if (err) {
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dev_err(&idtcm->client->dev,
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"Failed at line %d in func %s!\n",
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__LINE__,
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__func__);
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"%s: Set HW ToD failed\n", __func__);
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return err;
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}
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@ -891,7 +952,7 @@ static int _idtcm_adjtime(struct idtcm_channel *channel, s64 delta)
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ts = ns_to_timespec64(now);
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err = _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
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err = _idtcm_settime(channel, &ts);
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}
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return err;
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@ -899,13 +960,31 @@ static int _idtcm_adjtime(struct idtcm_channel *channel, s64 delta)
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static int idtcm_state_machine_reset(struct idtcm *idtcm)
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{
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int err;
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u8 byte = SM_RESET_CMD;
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u32 status = 0;
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int err;
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u8 i;
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clear_boot_status(idtcm);
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err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte));
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if (!err)
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msleep_interruptible(POST_SM_RESET_DELAY_MS);
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if (!err) {
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for (i = 0; i < 30; i++) {
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msleep_interruptible(100);
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read_boot_status(idtcm, &status);
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if (status == 0xA0) {
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dev_dbg(&idtcm->client->dev,
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"SM_RESET completed in %d ms\n",
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i * 100);
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break;
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}
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}
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if (!status)
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dev_err(&idtcm->client->dev, "Timed out waiting for CM_RESET to complete\n");
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}
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return err;
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}
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@ -1099,7 +1178,7 @@ static int idtcm_load_firmware(struct idtcm *idtcm,
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rec = (struct idtcm_fwrc *) fw->data;
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if (fw->size > 0)
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if (contains_full_configuration(fw))
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idtcm_state_machine_reset(idtcm);
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for (len = fw->size; len > 0; len -= sizeof(*rec)) {
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@ -1379,7 +1458,7 @@ static int idtcm_settime(struct ptp_clock_info *ptp,
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mutex_lock(&idtcm->reg_lock);
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err = _idtcm_settime(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
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err = _idtcm_settime(channel, ts);
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if (err)
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dev_err(&idtcm->client->dev,
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@ -1810,7 +1889,7 @@ static int idtcm_enable_tod(struct idtcm_channel *channel)
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if (err)
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return err;
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return _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
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return _idtcm_settime(channel, &ts);
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}
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static void idtcm_display_version_info(struct idtcm *idtcm)
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@ -2102,6 +2181,9 @@ static int idtcm_probe(struct i2c_client *client,
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dev_warn(&idtcm->client->dev,
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"loading firmware failed with %d\n", err);
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if (wait_for_boot_status_ready(idtcm))
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dev_warn(&idtcm->client->dev, "BOOT_STATUS != 0xA0\n");
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if (idtcm->tod_mask) {
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for (i = 0; i < MAX_TOD; i++) {
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if (idtcm->tod_mask & (1 << i)) {
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@ -53,9 +53,14 @@
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#define OUTPUT_MODULE_FROM_INDEX(index) (OUTPUT_0 + (index) * 0x10)
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#define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef)
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#define PEROUT_ENABLE_OUTPUT_MASK (0xdeadbeef)
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#define IDTCM_MAX_WRITE_COUNT (512)
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#define IDTCM_MAX_WRITE_COUNT (512)
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#define FULL_FW_CFG_BYTES (SCRATCH - GPIO_USER_CONTROL)
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#define FULL_FW_CFG_SKIPPED_BYTES (((SCRATCH >> 7) \
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- (GPIO_USER_CONTROL >> 7)) \
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* 4) /* 4 bytes skipped every 0x80 */
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/* Values of DPLL_N.DPLL_MODE.PLL_MODE */
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enum pll_mode {
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