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Merge branch 'bcmgenet-irq-coalesce'
Florian Fainelli says: ==================== net: bcmgenet: Interrupt coalescing This patch series adds support for interrupt coalescing for GENET adapters. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
25354001d0
2 changed files with 154 additions and 5 deletions
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@ -205,6 +205,23 @@ enum dma_reg {
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DMA_INDEX2RING_5,
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DMA_INDEX2RING_6,
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DMA_INDEX2RING_7,
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DMA_RING0_TIMEOUT,
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DMA_RING1_TIMEOUT,
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DMA_RING2_TIMEOUT,
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DMA_RING3_TIMEOUT,
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DMA_RING4_TIMEOUT,
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DMA_RING5_TIMEOUT,
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DMA_RING6_TIMEOUT,
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DMA_RING7_TIMEOUT,
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DMA_RING8_TIMEOUT,
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DMA_RING9_TIMEOUT,
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DMA_RING10_TIMEOUT,
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DMA_RING11_TIMEOUT,
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DMA_RING12_TIMEOUT,
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DMA_RING13_TIMEOUT,
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DMA_RING14_TIMEOUT,
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DMA_RING15_TIMEOUT,
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DMA_RING16_TIMEOUT,
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};
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static const u8 bcmgenet_dma_regs_v3plus[] = {
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@ -216,6 +233,23 @@ static const u8 bcmgenet_dma_regs_v3plus[] = {
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[DMA_PRIORITY_0] = 0x30,
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[DMA_PRIORITY_1] = 0x34,
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[DMA_PRIORITY_2] = 0x38,
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[DMA_RING0_TIMEOUT] = 0x2C,
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[DMA_RING1_TIMEOUT] = 0x30,
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[DMA_RING2_TIMEOUT] = 0x34,
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[DMA_RING3_TIMEOUT] = 0x38,
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[DMA_RING4_TIMEOUT] = 0x3c,
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[DMA_RING5_TIMEOUT] = 0x40,
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[DMA_RING6_TIMEOUT] = 0x44,
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[DMA_RING7_TIMEOUT] = 0x48,
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[DMA_RING8_TIMEOUT] = 0x4c,
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[DMA_RING9_TIMEOUT] = 0x50,
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[DMA_RING10_TIMEOUT] = 0x54,
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[DMA_RING11_TIMEOUT] = 0x58,
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[DMA_RING12_TIMEOUT] = 0x5c,
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[DMA_RING13_TIMEOUT] = 0x60,
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[DMA_RING14_TIMEOUT] = 0x64,
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[DMA_RING15_TIMEOUT] = 0x68,
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[DMA_RING16_TIMEOUT] = 0x6C,
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[DMA_INDEX2RING_0] = 0x70,
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[DMA_INDEX2RING_1] = 0x74,
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[DMA_INDEX2RING_2] = 0x78,
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@ -235,6 +269,23 @@ static const u8 bcmgenet_dma_regs_v2[] = {
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[DMA_PRIORITY_0] = 0x34,
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[DMA_PRIORITY_1] = 0x38,
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[DMA_PRIORITY_2] = 0x3C,
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[DMA_RING0_TIMEOUT] = 0x2C,
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[DMA_RING1_TIMEOUT] = 0x30,
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[DMA_RING2_TIMEOUT] = 0x34,
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[DMA_RING3_TIMEOUT] = 0x38,
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[DMA_RING4_TIMEOUT] = 0x3c,
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[DMA_RING5_TIMEOUT] = 0x40,
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[DMA_RING6_TIMEOUT] = 0x44,
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[DMA_RING7_TIMEOUT] = 0x48,
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[DMA_RING8_TIMEOUT] = 0x4c,
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[DMA_RING9_TIMEOUT] = 0x50,
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[DMA_RING10_TIMEOUT] = 0x54,
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[DMA_RING11_TIMEOUT] = 0x58,
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[DMA_RING12_TIMEOUT] = 0x5c,
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[DMA_RING13_TIMEOUT] = 0x60,
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[DMA_RING14_TIMEOUT] = 0x64,
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[DMA_RING15_TIMEOUT] = 0x68,
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[DMA_RING16_TIMEOUT] = 0x6C,
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};
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static const u8 bcmgenet_dma_regs_v1[] = {
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@ -245,6 +296,23 @@ static const u8 bcmgenet_dma_regs_v1[] = {
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[DMA_PRIORITY_0] = 0x34,
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[DMA_PRIORITY_1] = 0x38,
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[DMA_PRIORITY_2] = 0x3C,
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[DMA_RING0_TIMEOUT] = 0x2C,
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[DMA_RING1_TIMEOUT] = 0x30,
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[DMA_RING2_TIMEOUT] = 0x34,
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[DMA_RING3_TIMEOUT] = 0x38,
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[DMA_RING4_TIMEOUT] = 0x3c,
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[DMA_RING5_TIMEOUT] = 0x40,
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[DMA_RING6_TIMEOUT] = 0x44,
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[DMA_RING7_TIMEOUT] = 0x48,
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[DMA_RING8_TIMEOUT] = 0x4c,
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[DMA_RING9_TIMEOUT] = 0x50,
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[DMA_RING10_TIMEOUT] = 0x54,
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[DMA_RING11_TIMEOUT] = 0x58,
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[DMA_RING12_TIMEOUT] = 0x5c,
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[DMA_RING13_TIMEOUT] = 0x60,
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[DMA_RING14_TIMEOUT] = 0x64,
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[DMA_RING15_TIMEOUT] = 0x68,
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[DMA_RING16_TIMEOUT] = 0x6C,
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};
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/* Set at runtime once bcmgenet version is known */
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@ -498,6 +566,86 @@ static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
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priv->msg_enable = level;
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}
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static int bcmgenet_get_coalesce(struct net_device *dev,
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struct ethtool_coalesce *ec)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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ec->tx_max_coalesced_frames =
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bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
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DMA_MBUF_DONE_THRESH);
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ec->rx_max_coalesced_frames =
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bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
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DMA_MBUF_DONE_THRESH);
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ec->rx_coalesce_usecs =
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bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
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return 0;
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}
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static int bcmgenet_set_coalesce(struct net_device *dev,
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struct ethtool_coalesce *ec)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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unsigned int i;
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u32 reg;
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/* Base system clock is 125Mhz, DMA timeout is this reference clock
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* divided by 1024, which yields roughly 8.192us, our maximum value
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* has to fit in the DMA_TIMEOUT_MASK (16 bits)
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*/
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if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
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ec->tx_max_coalesced_frames == 0 ||
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ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
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ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
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return -EINVAL;
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if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
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return -EINVAL;
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/* GENET TDMA hardware does not support a configurable timeout, but will
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* always generate an interrupt either after MBDONE packets have been
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* transmitted, or when the ring is emtpy.
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*/
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if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
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ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_high ||
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ec->tx_coalesce_usecs_low)
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return -EOPNOTSUPP;
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/* Program all TX queues with the same values, as there is no
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* ethtool knob to do coalescing on a per-queue basis
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*/
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for (i = 0; i < priv->hw_params->tx_queues; i++)
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bcmgenet_tdma_ring_writel(priv, i,
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ec->tx_max_coalesced_frames,
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DMA_MBUF_DONE_THRESH);
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bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
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ec->tx_max_coalesced_frames,
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DMA_MBUF_DONE_THRESH);
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for (i = 0; i < priv->hw_params->rx_queues; i++) {
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bcmgenet_rdma_ring_writel(priv, i,
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ec->rx_max_coalesced_frames,
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DMA_MBUF_DONE_THRESH);
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reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
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reg &= ~DMA_TIMEOUT_MASK;
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reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
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bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
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}
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bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
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ec->rx_max_coalesced_frames,
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DMA_MBUF_DONE_THRESH);
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reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
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reg &= ~DMA_TIMEOUT_MASK;
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reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
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bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
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return 0;
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}
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/* standard ethtool support functions. */
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enum bcmgenet_stat_type {
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BCMGENET_STAT_NETDEV = -1,
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@ -844,6 +992,8 @@ static struct ethtool_ops bcmgenet_ethtool_ops = {
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.get_eee = bcmgenet_get_eee,
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.set_eee = bcmgenet_set_eee,
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.nway_reset = bcmgenet_nway_reset,
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.get_coalesce = bcmgenet_get_coalesce,
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.set_coalesce = bcmgenet_set_coalesce,
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};
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/* Power down the unimac, based on mode. */
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@ -304,13 +304,12 @@ struct bcmgenet_mib_counters {
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#define UMAC_IRQ_RXDMA_MBDONE (1 << 13)
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#define UMAC_IRQ_RXDMA_PDONE (1 << 14)
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#define UMAC_IRQ_RXDMA_BDONE (1 << 15)
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#define UMAC_IRQ_RXDMA_DONE (UMAC_IRQ_RXDMA_PDONE | \
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UMAC_IRQ_RXDMA_BDONE)
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#define UMAC_IRQ_RXDMA_DONE UMAC_IRQ_RXDMA_MBDONE
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#define UMAC_IRQ_TXDMA_MBDONE (1 << 16)
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#define UMAC_IRQ_TXDMA_PDONE (1 << 17)
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#define UMAC_IRQ_TXDMA_BDONE (1 << 18)
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#define UMAC_IRQ_TXDMA_DONE (UMAC_IRQ_TXDMA_PDONE | \
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UMAC_IRQ_TXDMA_BDONE)
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#define UMAC_IRQ_TXDMA_DONE UMAC_IRQ_TXDMA_MBDONE
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/* Only valid for GENETv3+ */
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#define UMAC_IRQ_MDIO_DONE (1 << 23)
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#define UMAC_IRQ_MDIO_ERROR (1 << 24)
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@ -386,7 +385,7 @@ struct bcmgenet_mib_counters {
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#define DMA_RING_BUFFER_SIZE_MASK 0xFFFF
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/* DMA interrupt threshold register */
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#define DMA_INTR_THRESHOLD_MASK 0x00FF
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#define DMA_INTR_THRESHOLD_MASK 0x01FF
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/* DMA XON/XOFF register */
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#define DMA_XON_THREHOLD_MASK 0xFFFF
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